SU1357960A1 - Device for checking quantity of units of binary code by modulus k - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to build reliable devices for processing discrete information. The purpose of the invention is to increase the speed of the device. The binary code is processed by a multi-channel parallel-to-serial code converter. The signals from the information output of the first channel of the converter through the OR element are fed to the counting input of the counter modulo K. The signals from the information outputs of the other channels of the converter are fed to the summing inputs of the corresponding unit counting units of the KU group. The operation of the multichannel converter is clocked by a clock pulse generator. At the end of the multichannel converter operation, the trigger is set to one state, the signal from the direct output of which allows the passage through the elements of the AND group of clock pulses. Each previous unit of counting units modulo the K group, if there is a code different from zero in it, allows the passage of clock pulses through the corresponding AND group element and prohibits the passage of clock pulses through the remaining And group elements. The signals from the output of an open element AND of the group are received through the element OR to the counting input of the counter modulo K and to the subtracting input of the corresponding unit unit counting unit. As soon as the code in the unit counting unit of the group becomes zero, the passage of clock pulses through the corresponding AND group element is closed and their passage through the remaining AND group elements is allowed. As soon as the reading of the contents of all units of the group is counted, the output signal of the device is formed at the output of the element And. The number of units of the binary code modulo K is stored on the counter modulo K. 1 cp f-ly, 2 ill. i with with sd with a

Description

This invention relates to automation. Ke and computer technology and can be used to build reliable devices for processing discrete information.

 the invention is to increase the speed of the device.

Figure 1 shows the functional

counting units modulo the K group. Thus, upon completion of the work of the multichannel converter 1 (the conversion is performed with the power of the signals from the generator output of 3 clocks) on the counter modulo K and on the reversible counters 12 modulo K all blocks under

device layout; FIG. 2 shows the function of 10 units of account modulo K group 9 and the scheme of the unit counting unit modulo K.

The device for controlling the number of binary code units modulo K (Fig. 1) contains a multichannel preamplifier of 1 parallel code into a sequence, an OR 2 element, a 3 clock pulse generator, a group of 4 information inputs converts a code equal to the number of ones in separate groups of bits before the binary source code

Thereafter, the contents of the revolving counters 12 modulo K of all the units of moduli of units Modulo K of group 9 to the contents of counter 11 modulo k, are sequentially reset to zero.

tel, information output 5 devices, a group of 6 elements And, trigger 7, element And 8, group 9 units of unit count K, output 10 of the end of the device, counter 11 modulo K.

The unit Counting units modulo K group 9 contains a reversible counter 12 modulo K, the element OR 13 and the element NOT 14.

The device DP control the number of units of binary code modulo K works as follows.

At the start of operation, the trigger 7, the counter 11 modulo K, and the reversible counters 12 modulo K of all units of counting units of group 9 are set to the zero state (the initial setting circuit is not shown). The source binary code enters the information inputs of group 4 of the device.

In the multichannel converter of parallel code to serial, the processing of the source binary code begins; from the information output of the first channel of multichannel converter 1, signals arrive at the first input of the element OR 2, from the output of which goes to the counting input of counter 11 modulo K. the number of units in the first channel of multichannel converter 1 is counted.

The signals from the information outputs of other channels of the multichannel converter 1 are fed to the summing inputs of reversible counters 12 modulo K of the corresponding blocks

counting units modulo K of group 9. Thus, after the end of operation of multichannel converter 1 (conversion is carried out using signals from the generator of 3 clock pulses) on counter 11 modulo K and on reversible counters 12 modulo K of all blocks for counting units modulo K group 9

contains a code equal to the number of units in separate groups of bits of the source binary code modulo K.

Thereafter, the contents of the reversible counters 12 modulo K of all units of units modulo K of group 9 to the contents of counter 11 modulo K, which is done later, are sequentially reset.

five

0

blowing way.

The output signal of the end of operation of the multichannel converter 1 sets trigger 1 to one state, the signal from the direct output 5 of which opens AND elements of group 6 for passing signals from the output of the 3 clock pulse generator. If on the reversible counter 12 of the first unit counting unit modulo K of group 9, the code is different from zero, then a single signal from the second output of this block allows the passage of clock pulses through the first element of group 6, while the zero signal from the first output of the first counting unit units modulo K group 9 closes all elements AND group 6, starting with the second.

The signals from the output of the first element AND of group 6 through the element OR 2 are fed to the counting input of counter 11 modulo K and simultaneously to the subtracting input of the first unit of unit count modulo K of group 9. When 5 through the first element of group 6 passes the number of clock pulses equal to If the code containing on the reversible counter 12 of the first unit counting unit modulo K of group 9, then a zero code is set on this reversible counter 12. At this point on the counter 11 modulo K there will be a code equal to the sum modulo K of the initial contents of counter 11 and the contents of the reversible counter 12 of the first unit counting unit modulo K of group 9.

Then the zero signal from the second output of the first unit of counting units

0

five

modulo to group 9 closes the first element AND of group 6, and a single signal from the first off-line of this block permits the passage of clock pulses through the remaining elements of AND 6, the addition to counter 11 modulo the content of the reversible counter I2 of the second unit of counting K groups 9.

Upon completion of the addition of the contents of counter II modulo K with the contents of the reversible counters 12 of all units of counting units modulo K of group 9, the output signal of the device 8 is generated at the output of element 8. By this time, the counter I1 contains a code equal to the number of units of binary code modulo K.

Claims (2)

1. A device for controlling the number of units of binary code modulo K, containing a counter modulo K, 25 is the information output of the device element AND, the element OR, the group of elements AND, the clock generator, the output of the generator of clock pulses connected to the first inputs of all the elements AND groups, which, in order to increase the speed of the device, have introduced a multi-channel parallel code converter into a serial one, a group of units of units modulo K and a trigger, with the information group Parallel Code to Serial Multi-channel Converter is a group of information inputs of the device, the information output of the first channel of the multi-channel parallel code to serial converter is connected to the first input of the OR element, the output of the end of the operation of the multi-channel parallel code to serial converter is connected to a single trigger input, direct output whose first exit o five 0 The units of all units of module K are connected to the corresponding inputs of the element I, the output of which is the output of the device’s end of operation, the information output of each i-ro channel of the multichannel parallel code to serial converter (where n is the number of channels of the multichannel parallel code converter to serial ) connected to the summing input (il) -ro of the unit counting unit modulo K, the direct trigger output is connected to the second inputs of all AND elements of the group, the second output of each j-ro counting unit units modulo K group is connected to the third input of the j-ro element AND group (), the output of which is connected to the subtractive input j-ro of the unit of calculation of units modulo K group AND (j + l) -M input of the OR element, the output of which is connected to the counting input of the modulo K counter, the information output of Which device, the first output of each tth unit counting unit modulo K group is connected to the (t + 3) -th inputs of each 1st element And group (, tj +), output clock generator connected to the clock input of the multichannel parallel code converter in sequential. 2. The device according to claim 1, characterized in that the unit of counting units modulo K group contains a reversible counter modulo K, the element OR and the element NOT, and the summing and subtracting inputs of the reversible counter modulo K are respectively summing and subtracted By the block inputs, the outputs of the bits of the reversible counter modulo K are connected to the inputs of the OR element, the output of which is connected to the input of the element NOT, the output of which is the first output of the block, the output of the OR element is the second output of the block. Editor I. Shulla FIG. g Compiled by V.Grechnev Tehred L. Serdyukova Proofreader L. Pilipenko Order 6000/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4