SU1259246A1 - Device for ordering data - Google Patents

Abstract

The invention relates to computing and can be used in high reliability computing systems for communicating a processor with external devices or with another processor. The purpose of the invention is to increase the reliability of the device by monitoring incoming information. The device contains a group of input registers, a group of registers, a number of operand numbers, a group of comparison circuits, first and second groups of blocks of elements I, a group of output registers, a shift register whose input is connected to the clock input of the device, and outputs to the inputs of the corresponding registers of the operand number groups whose outputs are connected to the first inputs of all comparison circuits; groups, the second inputs of which are connected to the first outputs of the corresponding input registers, the second outputs of which are connected to the first inputs of the corresponding the second group of inputs, the second inputs of which are connected to the outputs of the corresponding group comparison circuits, the outputs of the blocks of elements of the second group, are combined and connected to the second inputs of all the blocks of elements AND of the first group whose outputs are connected to the inputs of the corresponding output registers of the group whose outputs are connected with the corresponding. output group of the device outputs. New is the introduction of the register of the standard, the comparison unit, the third group of AND blocks, the STI element and the subtracting counter, t Il. I (L with you ate with 1C 4 O)

Description

The invention relates to computing technology and can be used in computing systems of high reliability for communicating processors with external devices or with another processor.

The purpose of the invention. - increasing the quality of the device’s acceptance by monitoring incoming information.

 The drawing shows the functional scheme on the device.

The device contains a shift register 1, a group of registers 2 numbers of operands, a group of input registers 3j a group of comparison circuits 4, a first tS group of blocks of elements AND 5, a second group of blocks of elements AND 6, a group of output registers 7, a register 8 of the standard, a block 9 of comparison, a third a group of 10 elements, And, an element OR 11, a subtracting 20 counter 12, informational inputs 13 of the device, an input 14 specifying a reference value of the device code, a clock input 15 of the device, informational outputs 16 of the device and an output 17 of the number of errors. 35 devices.

The principle of operation of the device is based on the sequential sampling of operands, which is found in registers 3 in accordance with their sequence number, 30, and consists in the sequential comparison of the order of numbers recorded in registers 2 with the indicative parts of all operands , and the selected operands after comparison at block 9 of the comparison with the valid value of the operand are written sequentially in registers 7. Except. In addition, on the counter 12, the number of the selected operands 40 is compared with the required number recorded in the counter 12.

The device works as follows.

Counter 12 records (chains 45. Records are not shown) the amount of data required for loading. Operands with registers 3 are supplied with operands with indicative parts representing their sequence numbers sO operands. In registers 2, the numbers of operands are sequentially recorded. The clock input 15 of the device is supplied with a sequence of clock pulses which are fed to the input of the register jg of the 1st shift. And record 1 is recorded in the first register bit of the shift 1 and bitwise serial shift

her to the last bit. Thus, at shift 1, signal 1 appears at the corresponding output of the shift register. This signal is fed to the read input of the corresponding register 2, and the information contained in this register is fed to the inputs of all comparison circuits A simultaneously. Thus, the inputs of all the comparison circuits 4 sequentially receive the numbers of the operands contained in the registers 2 of the numbers of the operands. The second input of each comparison circuit 4 is supplied with the operand number from the corresponding register 3. At the output of that comparison circuit 4, in which the operand numbers coincide, an output signal is generated, according to which the operand from register 3 through And 6 blocks of elements enters on. the moves of the blocks of elements And 5, at the same time, the value of the selected operand arrives at block 9 comparing, where it is compared with the value recorded in register 8. Comparison at the output of block 9 produces a signal which, together with the present clock pulse signal at one of the shift register 1 outputs .formiruet output corresponding block elements 10 and unit level, according to which an operand via the respective block elements 5 and 7 is recorded in the register.

At the same time, the pulse from the output of the block of elements. AND 10 through the element OR 11 enters the counting input of the counter 12, at which the unit is subtracted from the contents of the counter.

The device operation cycle is completed when the required number of clock pulses is received.

As a result of the operation of the device, an irregular sequence of operands at the inputs 13 of the device is converted into a series of operands recorded in registers 7 in accordance with their own serial numbers, and thus, the operands are ready for recording in the computer memory or for transfer to the microprocessor.

If the numbers of the operands in registers 2 and 3 do not match, i.e., e. If one or several operands in register 3 are not output, the contents of counter 12 are not O, but indicate the number of / unsent operands. In addition, when incomparable

The operand with a valid value at block 9 of the comparison is not compressed signal, and the operand is not transmitted to the output, and the contents of counter 12 are not zero. Thus, after completing the operation, the number of errors in the transmission of operands is recorded in counter 12, and the processor decides whether it is possible to work with these operands.

The duration of the signal at the clock input of the device must be longer than the delay time on elements 1, 2, 4, 6 and 9. Registers 2 must be implemented on chips with an open collector or in three states (for example, 589 IR12), elements AND 6 - similarly (for example, 155 ЛВ8). Information at input 14 can be changed promptly (for each clock pulse). At block 9 of the comparison it is possible to organize the modes More, Less, Equal - depending on the required range of comparison (the chain of organization of the modes is not shown).

Formula of invention

A device for ordering data containing a group of input registers, a group of output registers, a group of comparison circuits, two groups of AND blocks, a group of registers of operand numbers, a shift register, the inputs of the group of input registers being information inputs of the device, and their outputs of information bits connected to the first inputs of blocks of elements AND of the first group, the second inputs of which are connected to the outputs of the group of comparison circuits, the first

ten

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and the second inputs of which are connected respectively to the outputs of the bits of the operand number of the group of input registers and the outputs of the group of registers of operand numbers whose inputs are connected to the outputs of the shift register, whose input is connected to the clock input of the device, the outputs of the element blocks of the first group are connected to the first inputs of the element blocks And the second group, the outputs of which are connected to the inputs of the group of output registers, the outputs of which are informational outputs of the device, are tl and -. I see that, in order to increase the reliability of work, the standard register, the comparison block, the OR element, the subtracting counter, and the third group of AND blocks are entered into it, and the information of the standard register forms the input specifying the device code reference value, the sync input and the group of outputs of the register of the standard is connected respectively to the clock input of the device and the first group of inputs of the comparison block, the second group of inputs of which is connected to the outputs of the blocks of the And elements of the first group, the output of the comparison block is connected to the first inputs of blocks of elements AND of the third group, the second and third inputs of which are connected respectively to the clock input of the device and the outputs of the shift register, the outputs of blocks of elements AND of the third group are connected to the second inputs of blocks of elements AND of the second group and inputs of the OR element whose output is connected to the counting input calculate the counter whose output is the output of the number of device errors.

Editor O. Yurkovetska

Compiled by I.Khazov

Tehred I.Popovich Proofreader T.Kolb

Order 5122/46 Circulation 671 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

, „., - -.-. -.-Production and printing company, Uzhgorod, ul “Projectna, 4,

Claims (1)

Claim A device for organizing data containing a group of input registers, a group of output registers /, a group of comparison circuits, two groups of blocks of AND elements, a group of registers of operand numbers, a shift register, and the inputs of the group of input registers are information inputs of the device, and their outputs are information discharges are connected to the first inputs of blocks of elements AND of the first group, the second inputs of which are connected to the outputs of the group of comparison circuits, the first and second inputs of which are connected respectively to the outputs of the digits of the number the operand of the group of input registers and the outputs of the group of registers of the numbers of operands whose inputs are connected to the outputs of the shift register, the input of which is connected to the clock input of the device, the outputs of the blocks of elements AND of the first group are connected to the first inputs of the blocks of elements AND of the second group, the outputs of which are connected to the inputs of the output group registers, the outputs of which are the information outputs of the device, about l and -. characterized in that, in order to increase the reliability of the operation, a reference register, a comparison unit, an OR element, a subtracting counter and a third group of AND blocks are introduced into it, and the information inputs of the reference register form the input for setting the reference value of the device code, the sync input and the group of outputs the reference register are connected respectively to the clock input of the device and the first group of inputs of the comparison unit, the second group of inputs of which is connected to the outputs of the blocks of elements And of the first group, the output of the comparison unit is connected to the inputs of the blocks of elements AND of the third group, the second and third inputs of which are connected respectively to the clock input of the device and the outputs of the shift register, the outputs of the blocks of elements of the third group are connected to the second inputs of the blocks of elements of the second group and the inputs of the OR element, the output of which is connected to the counting input subtracting counter, the output of which is the output of the number of device errors.