SU1254484A1 - Device for loading data in computer system - Google Patents

Abstract

The invention relates to computing and can be used in computing systems for communicating processors with external devices or memory devices with a multi-format data representation. The purpose of the invention is to expand the functionality of the device due to the simultaneous arrangement of operands and control the format of the output data. The device contains groups of input and output registers, a decoder, groups of elements SH, (n-1) operand select nodes, a format of output data , a group of comparison circuits, a group of blocks of elements I. In the device, the formation of an output ordered array in accordance with a predetermined order of placement is performed in one step. This allows you to further perform simultaneous recording of the output data into the memory, allowing simultaneous access via several channels. Records, the number of which is set in the output format register, by means of which you can also set the format of the data, subtract | 1 (their records. 1 il. (L

Description

The invention relates to computing and can be used in computing systems for communicating processors with out-of-computer or auxiliary devices with multi-format data representation,

The purpose of the invention is to enhance the functional capabilities by simultaneously arranging operands and controlling the format of the output data.

The drawing shows a block diagram of the device.

The device contains a group of 1 operand numbers 1, an output format register 2, a group of input registers 3, operand selection nodes 4, a group of comparison circuits 5 and blocks of elements B of the operand selection node 4, a decoder 7, a group of elements OR 8, a group of blocks elements 9, the group of output registers 10, the group of inputs 11 of the device, the group of inputs 12 of the device operand number, the input 13 of the format of the output data of the device, the clock input 14 of the device, the group of outputs 15 of the device,

The device works as follows.

Through inputs 11, registers 3 are supplied with operands with indicative parts representing the order numbers of the operands. Registers 1 successively write the numbers of the operands in order to place them in the output registers 10. Thus, in register 1, the number of the operand to be placed in register 10, from register 35 in which the number of the operand is written.

one

corresponding to the number in register B, register 2, input 13 enters the size (format) of the output array, i.e. the number of output registers 10, in which the source data from registers 3 should be placed by means of a decoder a, the number of outputs of which is equal to the number of input (output) registers, using the elements of SH8 8, receive control single signals (see table),

The table shows that if the seventh output is excited in the decoder 7, then single signals are formed by all seven elements OR 8, the output signals of which open seven blocks of elements AND 9 through the first control inputs. Through the selector 4 of operand 4, it is transmitted single content outputs

from registers 3 on the control signal from the comparison circuit 5 in which the operand number from register 1 and the value of one of the registers 3 match. At the same time, output signals are generated simultaneously in all nodes 4 of operand selection.

thirty

35

40

45

I The appearance of the output signals of nodes 4 at the information inputs of the blocks of elements AND 9 is determined by the time of transients in nodes 4 after receiving information in registers 3 and 4. According to the clock signal received at input 14, the information from the outputs of nodes 4 is applied on that weekend registers 10, the number of which is determined by the number of excited outputs of the SHSh 8 elements,

f

Thus, the formation of the output ordered array in accordance with a given order of placement is performed in one step. This allows you to further perform simultaneous recording of output data into a memory allowing simultaneous access via several recording channels, the number of which can be specified in register 2,

In addition, when using a device for placing data in a multi-format memory by means of register 2, it is possible to set-i. format the data to be subject to. pion. So, if the minimum format of the 55 operand is one byte, then the data can be written to the memory by a resolution of one byte, specified in register 2,

50

Claims (1)

Invention Formula A device for loading data in a computing system containing a group of input registers whose inputs are the inputs of operands and their device features, a group of registers of the operand number, a group of output registers whose outputs are the group of outputs of the device, the first operand selector node from the group of comparison circuits and the group of blocks of elements I, the group of blocks of elements I, and the output of the first register of the operand number of the group are connected to the first inputs of all the schemes of comparison of the group of the first operand selection node in The second inputs of which are connected to the first outputs of the corresponding input registers of the group, the second outputs of the input registers of the group are connected to the information inputs of the corresponding blocks of elements AND groups of the first operand selection node, whose control inputs are connected to the outputs of the corresponding comparison circuits of the group of their operand selection node And the groups of the first node of choice about Geranda are combined and connected to the information inputs of the first block by the elements of the group, the outputs of the blocks of elements AND the group of with the inputs of the corresponding output registers of the group, differing from the fact that, in order to extend the functionality by simultaneously arranging the operands and controlling the format of the output data, 2544844 it entered the output format register, the input of which is the device format input, the decoder, a group of OR elements and n − 1 rand select nodes, with the first outputs of the i-th input group register (where, 2, ten iS 20 25 ten 15 ...,,P; n is the number of input operands) are connected to the second inputs of the i-th group comparison circuit in each of the p-1 operand selection nodes, the first inputs of the comparison circuit of the j-ro group of the operand selection node (where j 2,3, ..., p) connected to the outputs of the J-th register of the number, the first outputs of the i-ro input register of the group are connected to the second inputs of the comparison circuit of the group of all operand selection nodes, starting with the second., the second outputs of the i-ro input register of the group are connected to the information inputs of the i-ro block elehteKTOB AND the j-ro group of the one-choice selection node, the outputs of which are connected to the information The jyo inputs of the j-ro block of elements AND groups, the outputs of the output data format register are connected to the inputs of the decoder, the k-input of the i-ro element OR of the group (where k 1,2, ..., p- (i- 1)) is connected to The input (k + i-1) -ro of the element OR of the group, the output of which is connected to the first control input of the i-ro block of elements AND of the group, the first control input of the last block of elements of the AND group is connected to the last output of the decoder, the second control of the blocks elements and groups are connected to the clock input of the device. Editor I. Casarda Order 4722/53 Compiled by M. Kudr Shev Tehred I.Popovich Proofreader L, Pilipenko Circulation 671. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4