SU1434449A2 - Computing apparatus - Google Patents

Abstract

This invention relates to digital computing and can be used to build reliable arithmetic devices. The aim of the invention is to increase the fault tolerance of the device. For this purpose, a device containing a block of RAM, two adders, a data multiplexer chip, two shifters, two result registers, a block of W and S elements, and I are entered into the third sou, the fifth and sixth data multiplexers, the third gatel, third result register and decoder of failures. 1 ill., 1 tab.

Description

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with

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The invention relates to digital computing, can be used in the construction of reliable arithmetic devices and is an improvement of the invention according to the author. St. No. 1336022,

The aim of the invention is to increase the resiliency of the device.

The drawing shows the functional diagram of the device.

The device contains a block of 1 RAM, six data multiplexers 2-7, three adders 8-10, three shifters 11-13, three registers 14-16 of the result, block 17 elements OR, element AND 18, a decoder 19 failures, and the decoder inputs 19 is connected to the outputs of K-signals of the signs of comparison of the results of operations, the sum of Tors 8-10, and the outputs of the decoder 19 are connected to the enable inputs of registers 14-16 o The device has the first and second inputs 20, 21 of the operand addresses, the input 22 of the receive resolution first and second inputs 23 and 24 of the choice of operands, input 25 operation of the mouth oystva, the shift direction control input 26, control input 27, the result record, informatsionish output 28, output 29, an error flag,

The device works as follows.

The basis of all operations performed in this device is the basic operator of the form

: A 1: A2 2 - “A

one

where the values of the operands

placed at addresses A and A, the sign of the performance of one of the arithmetic or logical operators} o m is the shift coefficient. The implementation of this operator takes four cycles. In the first cycle of block 1, addresses A (input 20) and A (input 21) simultaneously read both operands and, through open control signals (inputs 22–23), the first inputs multiplexers are fed to the inputs of the adders 8-10. In the second cycle, in the accumulators 8–10, an arithmetic or logical operation is performed in parallel and synchronously in accordance with the micro-command code received at the input 25. B.

O

five

p g.

five

In the same cycle, the result of the operation from the outputs of the adders 8-10 enters the inputs of the shifters 11-13, in which, in accordance with the input signal from input 26, the information is shifted by the value of m and then it is written to the registers 1416. In the third clock cycle control signals (inputs 23, 24) open the second inputs of multiplexers 2-7, and the results of the operation performed in each adder from the codes of registers 14-16 are fed to the inputs of adders 8-10,

Starting from the third cycle, the adders 8-10 operate in the comparator mode, performed a pair-wise comparison of the results of the operation, and generate signals of the comparison signs K, which are received from the second outputs of the adders 8-10 to the inputs of the decoder 19 and the PI element 18, the output of which is connected to the device output 29, while the state of the registers 14-16 is unchanged. In the case of comparing the results of the operation in the sum of the curtains 8-10, the element 18 and the signal enable the NIN, according to which the results of the operation from the registers 14 are recorded in the fourth cycle. 15 or 16 through block 17 to block 1 of the memory on the control signal at input 22 of the reception enable. The results of the operation are recorded in block 1 at address A synchronously supplied to inputs 20, 21.

If one of the computational nodes of the device fails or fails in the corresponding adders, the operation results are incomparable (see table), the decoder 19 identifies the number of the failed compute node and eliminates it from the computational process, prohibiting the issuance of information from the result register of the failed node by submitting at the entrance of the permit for issuing a register of prohibition, which transfers it to the third state. In this case, the calculation process is not interrupted, and the recording of the correct result of the operation in memory block 1 is performed through the block

17, so in the previous case.

In the event of failure or failure of two computational nodes in all adders, the operation results are incomparable, the output of the element And 18 forms a prohibition signal, a record in

block 1 in the fourth clock cycle is not performed, the operation code is not changed, and it is repeated. When the number of permissible repetitions is exceeded, monitoring tests are included to determine the failed computation node, and the control signals (inputs 23, 24) are switched to the operation mode with a single computation node.

Claims (1)

Invention Formula y Computing device auth. St. No. 1336022, which is based on the fact that, in order to increase fault tolerance, it contains the third adder, the fifth and sixth data multiplexers, the third shifter, the 20th result register is connected the third result register and the fault decoder; the first second and third inputs of which are connected to the error sign outputs of the first, second and third adders, respectively; the first, second and third outputs of the error decoder are connected to the resolution outputs of the first, second and third result registers, respectively, the first information inputs the fifth and sixth data multiplexers are connected respectively to the first, second outputs of the RAM unit, the first and second information inputs, the control input and and the formation output of the third adder is connected respectively to the outputs of the fifth and sixth data multiplexers, the input of the operation of the device and the information input of the third sBIGater, the control input and output of which are connected respectively to the control input of the device shift direction and the information input of the third result register, the synchronous input of which is connected to the synchronous input of the device, the output of the first register of the result is connected to the first input of the block of the OR elements and the second information inputs of the first and sixth multiplexers data, the output of the second result register is connected to the second input of the OR block and the second information inputs of the second and third data multiplexers, and the output is the third input of the OR block and the second information inputs of the fourth and fifth data multiplexers, 2li Compiled by G.Vitaliyev Editor M.Tsitkina Tehred L.Oliynyk Proofreader M.Vasilyeva Order 6636 Circulation 704 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, st. Project, 4 Z5 Z6 27 Subscription