SU1179273A1 - Programmed control device - Google Patents

Abstract

A SOFTWARE DEVICE, CONTROL, containing an input unit connected by the first and second outputs respectively to the first information input and input Record, a memory block connected by the first input to the information input of the output unit, and the second output to the first inputs of the comparison unit connected by the second inputs to the output of the switch connected by the first and second information inputs to the bits of the first and second pulse counters, respectively, of the control unit containing the first, second, third and fourth And the clock elements, the clock generator, connected by the first output to the first inputs of the first and second elements, and the address register and the address counter, which is so that, in order to improve performance and expand the functionality of the device By providing simultaneous switching of actuators within one clock cycle, a code-to-code converter is entered into it, and a matching block, first, is entered into the control unit. the second and third OR elements and the start-up unit connected by the output. Initial installation to the first inputs of the first and second OR elements and to the zero inputs of the second pulse counter and output unit, the input to the output of the third AND element, and the Start output to the input of the clock generator. connected by a second output to the counting input of the first pulse counter and to the first input of the fourth element I connected to the control input of the switch and the PTO input to the output of the matching unit to the second input of the second element I LI, to the second input of the second element And, to the counting input of the second pulse counter and to the first input of the third element And connected by the second input to the output of the comparison unit, to the control input of the output unit and to the second input of the first element And connected by the output to the first input of the third element OR, connected by the second input. To the control input of the address register and to the second output of the input block, and the output to the counting input of the address counter connected to the zero input to the output of the first OR element, and the bit outputs to the address inputs of the memory block, to the information inputs of the address register and to the first inputs of the match block connected by the second inputs to the output of the address register, with the outputs of the second OR element and the second AND element connected respectively to the zeroing input of the first

Description

the pulse counter and to the second input of the first OR element, and the third outputs of the input block through the converter code - the code to the second information inputs of the memory block.

The invention relates to automation and computing and can be used in high-speed control systems of experimental installations in the study of fast processes.

The aim of the invention is to increase the speed and expansion of the functionality of the device by providing simultaneous switching of the actuating elements within one clock cycle.

FIG. 1 shows a functional diagram of the device; in fig. 2 structural scheme of the control unit.

The device comprises an input unit 1, a memory unit 2, a comparison unit 3, a switch 4, a first 5 and a second 6 pulse generator, a code-to-code converter 7, an output unit 8 and a control unit 9, which consists of a start unit 10, a clock frequency generator 11 , counter 12 addresses, register 13 addresses, block 14 matches the first 15, second 16 and third 17 elements OR, third 18, first 19, second 20 and fourth 21 elements I.

The device works as follows.

Initially, an executive control program is written, which is a set of control commands recorded in memory block 2 by means of input block 1 and code-code converter 7 in order corresponding to their execution order in time. Each control command is recorded in memory block 2 at the same address and consists of two parts — execution time code 1 command and channel status code, and the time code is recorded directly from input block 1 in

binary form, and the channel status code is initially converted by the converter 7 to a positional view, when each control

channel has one bit of code.

The unit record in any code bit corresponds to the enabled one, and the zero record to the disabled state of the corresponding control channel,

The program is recorded as follows.

Using the keyboard included in input block 1 (Fig. 1), the time code and the channel status code of the next command are dialed. Then, from the first output of the input unit 1, a signal is supplied to the control inputs of the memory unit 2 and the control unit 9. In block 9 control

(Fig. 2) the signal is fed to the control input of the address register 13 and through the second element OR 16 to the counting input of the address counter 12. The leading edge of this signal

The code of the next command is written to the memory block 2 at the address supplied to the address inputs of block 2 from the outputs of counter 12. In addition, the address code of the command being written is stored in register 13, the information inputs of which are associated with the address memory blocks of the memory block. I.

The trailing edge of the signal produces the formation in the counter 12 of the address of the next command. The next address is provided to memory block 2 and prepares it for recording the next command. Thus, the recording of all the control commands of the program is performed in turn. Lastly, a service command is recorded in memory block 2, in which instead of the command execution time code

the cycle number code is recorded; program repetition. In the register

13 records the address of the last service command.

Before starting work from the output of the start-up unit 10, the initial setup signal is applied to the outputs of zeroing the counter of 6 pulses and output unit 8 through the element 15 OR to the zeroing input of the address 12 counter and through the element 17 OR to the zeroing input of the counter 5 pulses. This signal is used to reset the device.

The start signal, coming from the output of the starting block 10, turns on the software device. The start signal enters the generator input 11 clock frequencies. At its outputs, two antiphase frequencies F, and Fj appear. The pulses of frequency P are fed to the counting input of the first 5 pulse counter, in which the current time is counted. The current time code is from the first 5 counter through the commutator 4 to the second inputs of the comparison unit 3, the first inputs of which are supplied with the time code for executing the first command from the second outputs of the memory 2.

When the current time codes and the command execution time from the output of the comparison unit 3 match, a signal is sent to the control input of the output unit 8 and sets the code at the outputs of this unit in accordance with the channel status code supplied to its information inputs from the first outputs of the memory unit 2 . In addition, the signal from the output of the comparison unit 3 is fed to the control unit 9 and opens the element AND 19. The clock frequency signal F through the element 19 And the element 16 OR switches the address counter 12, and the address code of the next command is generated in the address buses. At the outputs of memory block 2, the code of the following command appears, which is executed similarly when the codes of the current time and the time code for the execution of this command coincide.

In this way, all the control commands of the program are executed in turn. When the output of the counter 12 of the address of the last service command appears, the codes of the current address and the address of the last command at the inputs of the match 14 block coincide. In this case, the signal from the output of the coincidence unit 14 opens the elements AND 18, 20, 21. The clock frequency signal F, through the element 21, enters the control input of the switch 4 and connects to the second inputs of the comparison unit 3 outputs

Q pulse counter 6, in which the count of the number of spent program repetition cycles is performed. If the codes do not coincide at the inputs of the comparison unit 3, then

5 signal from the output of the block 14 coincidence through the element 17 OR the reset of the counter of 5 pulses and through the element 20 AND and the element 15 OR by a signal

Q clock frequency T ' is reset to the initial state of the address counter 12. The rising edge of the signal from the coincidence unit 14 in the counter 6 pulses is increased by one.

5 codes of the number of spent program cycles.

Thus, when the output of memory block 2 of the tracking command appears, the device is reset to its original state, and then a new program development cycle is repeated. When the specified number of program repetition cycles has been worked out, at the moment when the output of memory 2 of the service command appears, the codes at the inputs of comparison section 3 will match and the signal from its output through open 18 I will reset the starting block 10 and stop feeding Signal start to the generator input 11 clock frequencies. Further development of the program will be blocked. To restart the device, it is necessary from the start-up unit 10 to give a signal of the initial installation, and then a Start signal.

The device allows to achieve high speed for. an account of the change in the composition and structure of the control unit that implements a perfect operation algorithm, in which the sequence of command execution is given by the order in which they are written to the unit

memory, in each clock cycle of the current time, only one sequential control command is analyzed. The speed of the proposed device can be estimated by the value of the minimum clock cycle of the current time, which can be calculated by the formula

H ta.

Win

t., - command read time

where from memory block ty,

tq team analysis time. The calculation of the current time clock indicates that the speed of the proposed device is limited only by the time of reading and analyzing the control command and does not depend on the number of commands in the program.

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management The number of commands in a complex physical installation management program varies from five to ten to hundred.

Thus, the proposed device yields an advantage in speed by two orders of magnitude compared with the prototype.

The proposed device provides simultaneous switching of several actuators in any combination due to positional coding of the states of the output channels carried out by the channel state code generation unit.

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Claims (1)

A DEVICE FOR SOFTWARE, CONTROL, containing an input unit connected by the first and second outputs respectively to the first information input and input Record, a memory unit connected by the first output to the information input of the output unit, and the second output to the first inputs of the comparison unit connected by the second inputs to the output of the switch connected by the first and second information inputs to the bit outputs of the first and second pulse counters, respectively, a control unit containing the first, second, third and fourth AND elements, a clock generator connected to the first inputs of the first and second AND elements by the first output, an address register and an address counter, with the aim of increasing the speed and expanding the device’s functionality by ensuring simultaneous switching of actuating elements within one time step, a code-to-code converter is introduced into it, and a coincidence unit, the first, second, and third OR elements and a start-up unit connected by the output are inserted into the control unit the first inputs of the first and second OR elements and to the zeroing inputs of the second pulse counter and output unit, the input to the output of the third AND element, and the Start output to the input of the clock generator connected by the second output to the counting input of the first pulse counter and to the first input of the fourth AND element connected by an output to the control input of the switch, and by the second input to the output of the coincidence unit, to the second input of the second OR element, to the second input of the second AND element, to the counting input of the second pulse counter and to the first the input of the third AND element, connected by the second input to the output of the comparison unit, with the control input of the output unit and with the second input of the first AND element, connected by the output to the first input of the third OR element connected to the second input, with the control input of the address register and with the second output of the block input, and output - with the counting input of the address counter connected to the zeroing input to the output of the first OR element, and bit outputs - to the address inputs of the memory block, to the information inputs of the address register and to the first inputs of the block Ia, second inputs connected to the output of the address register, wherein the outputs of the second OR gate and the second AND gate are respectively connected to the reset input of the first 1179273 A pulse counter to the second input of the first OR element, and the third outputs of the input unit through the code-to-code converter to the second information inputs of the memory unit.