SU1619233A1 - Device for presetting cycles in n/c systems - Google Patents

Description

one

(21) 4671624/24

(22) 02.27.89

(46) 07.01.91. Bran. B 1

(72) E.T. Gorbenko, V.L.Koshkin,

A.I. Lapandin, A.D. Katynsky

and R.G.Ivantsov

(53) 621.503.55 (088.8)

(56) USSR author's certificate

W 246157, class G, 05 B 19/18, 1967.

USSR Author's Certificate No. 1280575, cl. G 05 B 19/18, 1986.

(54) DEVICE FOR SETTING CYCLES IN NUMERIC PROGRAM CONTROL SYSTEMS

(57) The invention relates to automation and computing, namely to positional numerical control systems, for example, for controlling machine tools for drilling printed wiring boards or cyclic-type handlers. The purpose of the invention is to simplify the device. Presumed

WITH&

(""

with to

with so

A link to achieve the goal is the possibility of failure in relation to positional systems from memorizing the addresses of the cycle entry and returning to the program and realizing the search for the desired memory addresses by writing special service characters tags followed by automatic regeneration of information. The device contains a controlled generator 1 pulse. relates to automation and computing, namely to positional systems of numerical program control, for example, to control machines for drilling pl t PCB manipulation tori or cyclic type.

The aim of the invention is to simplify the device.

FIG. 1 shows a functional diagram of the device; Fig. 2 is a circuit of a controlled ISO code symbol generator; Fig 3 is a diagram of the symbols decoder of the ISO code; in fig. 4 is a diagram of a deducting decimal two-bit counter; FIG. 5 shows timing charts of the device,

The device (Fig. 1) consists of a dual-band controlled generator of 1 pulses, memory elements 2, an address counter 3, an output key 4, an ISO code 5 decoder, a shift register 6, a subtracting decimal two-digit counter 7, a decoder 8 zero state of the counter controlled by the generator 9 symbols of the ISO code, the first 10 and second 11 RS-flip-flops, delay element 12, the first through eighth AND 13-20 elements, and three OR 21-23 elements.

Managed generator 9 codes (Fig. 2) consists of four inverters WITH OPEN COLLECTOR OUTPUT

24-27.

The decoder 5 (FIG. 3) contains a group of eight input inverters 28, a group 29 of five And elements, And 30 element, And 31 element for two inputs and output inverters 32-35.

The decimal counter 7 (fig. 4) consists of two one-bit counters 36 and 37.

owls, memory element 2, counter 3 addresses of the block of 4 output keys, decoder 5 characters of the ISO code, shift

register 6, subtracting two-digit counter 7, decoder 8 zero state of the counter, generator 9 characters of the ISO code, two RS flip-flops 10, 11, Delay element 12, AND 1320 elements, OR 21-23 elements. 1 hp f-ly, S il.

In positional systems, it is possible to refuse to memorize the addresses of the entrance to the cycle and the places of returning to the program and realizing the search for the necessary memory addresses by writing special service characters-labels followed by automatic regeneration of information.

The device (Fig. 1) works as follows.

In the information recording cycle, the operation of the device has no peculiarities: the part processing program in the ISO code goes through the ISO input bus to the information inputs of memory 2, accompanied by a signal. Recording DM, which through OR 22 enters the memory recording input of memory 2. Before recording, the counter 3 of the address is set to the initial zero state by the signal of the initial setup of the HU through the element OR 21. The change of the address of the counter 3 is carried out by applying the Start and Stop signals to the control inputs of the pulse generator 1, the output of which is connected to the counting input of the counter 3 addresses. After writing to elements 2 of memory, the processing program may have the form:

L1 ... EL2 ... E ... Lij ... E% N1 ... ... LFN2L1JLF ... M02.

In this representation, between the L and E symbols there is information about cycles (subprograms), the program itself begins with the% symbol, the cycle call command in the main program is programmed in frame N2 and has the form N2L1JLF, where Lij is the number of the called cycle.

Before transmitting information from memory elements 2 to the output bus, the ISO output device is given in

the initial state by sending a signal to the NC, which sets the triggers 10 and 11 to one state, and also through the OR 21 element to the zero state the counter 3 addresses. The signal from the inverted output of the trigger 11 is fed to the control input of the block 4 output keys and locks it. The same signal, arriving at the selection control input of generator 1, prepares it for operation in the higher range, which provides reading of information from memory elements 2 at the maximum possible speed. When a signal is received, the Start-up to the input of the controlled oscillator 1 begins to generate a series of high-frequency pulses (for example, 1 MHz). Since the trigger 10 is in the state S, the pulses from the output of the generator 1 through the elements AND 13 and OR 23 arrive at the C2-input shift control information of the register 6. Since the serial input of receiving information A. The register 6 is connected to the source-zero potential , then when the first four pulses are received from generator 1, O is recorded in all four bits of register 6, and during subsequent pulses of generator 1, the zero state of the register is confirmed. The pulses from the output of the generator 1 are also fed to the counting input of the address counter 3. Since the recording control input of the 2 elements of the memory from the output of the OR element 22 signals are not received, the elements of the 2 memory work in read mode

The information sequentially read from the memory cells of elements 2, starting with a zero address, goes to the inputs of the decoder 5. The signals on the outputs of the decoder 5 do not change the mode of operation of the device, because due to the fact that the input 11 of the trigger 20 signal and register 6 is in the zero state. The process continues until the decoder 5 generates a signal of the% symbol, which from the output of the decoder 5 enters the R-inputs of the trigger 10 and 11, and the signal from the output of the element 13 stops. out yes trigger 11 prepares keys 4 and element I 20 for operation, and also switches generator 1 to work in the lower range, in which the speed

reading information into the output bus The ISO output corresponds to the speed of an external receiver (for example, 10 kHz). Thus, after reading the% symbol, the information begins to arrive at the output of the device. The process continues until decryption.

the L symbol, whose signal from the output of the decoder 5 is fed to the S input of the control of the operation mode of the register 6 and prepares it for parallel reception of information.

5 Pulsed by the generator 1 pulse, the LC signal from the output of the decoder 5 is fed to the SZ-input of the parallel recording control register 6 m since the input of the first bit of the L register

0 6 is connected to the source of a single potential, and the remaining inputs are connected to a source of zero potency. then a register 1000 is written to register 6 (FIG. 5). Signal L, arriving at the input

5 of counter 7 does not change the mode of operation of the device. In accordance with the above representation of the cycle call command, the L digit code from the memory elements 2 receives the code of the digit of the higher bit of the number of the called cycle, and the signal Sign of the digit gated with the generator 1 pulse (Fig. 5) is fed to the inputs of the AND elements 15 and 16. Since register 6 is in the state 1000, the signal is produced at the output of element 15, as a result of which the high digit of counter 7 records the code of the digit of the higher bit of the QQ number of the cycle, the signal from the output of the element 15 through the element OR 23 enters also on C2 - the input of the shift control register 6 and on the falling edge of the pulse signal, the register 6 assumes the state 0100 (Fig. 5). The next digit is recorded by the signal from the output of the AND 16 element to the lower bit of the counter 7. Following the digit of the lower bit of the cycle number, when reading the cycle call command, the end code sign code of the LF information, whose signal from the output of the decoder 5 enters the input of the AND element 17. From the output of the element And 17 signal

e through the element OR 22 enters the recording control input of the elements 2 of the memory. Since the generator 9 codes, thanks to the signal from the FЈ-output of the register 6, generates a service code

five

the character H, then this character is written into that memory cell of the elements 2 in which the LF code is written. The symbol H represents the label of returning to the main program after completion of the called cycle.

The signal from the output of the element And 17 through the element 12 of the delay and the element OR 21 sets the address 3 to the zero state, and through the element OR 23 again shifts the information in the register 6, and it receives the state 0010 on the trailing edge of this signal . five). The signal from the output of the delay element 12 is also fed to the S input of the trigger 11, as a result of which the keys 4 are locked and the generator 1 switches to the higher range. The characters L are fed to the input. Subtracting the counter 7 and when the counter 7 reaches the zero state, the number of characters L corresponding to the number of the called cycle is read. The zero state of the counter 7 is decrypted by the decoder 8 and the signal from its output again brings the trigger 11 into the state R, while the information is read into the bus The ISO output at a speed corresponding to the lower range of the generator 1.

The process continues until the decoder 5 generates the E symbol, which is a sign of the end of the cycle (subroutine). This signal enters through element 18 on the S input of the trigger 11, the key block 4 is locked, the generator 1 switches to work in the higher range, at a higher speed it searches for a place to return to the program. The process continues until the decoder 5 generates a signal of the service symbol H, which is fed to the input of the AND 19 element, and from its output through the OR 22 element - to the input of the recording control of the 2 memory elements. Since, thanks to the signal from the Fa-output of the register 6, the 9-code generator generates the F code in the ISO input bus, it replaces the H symbol with the LF code and the information is restored. The signal 1 from the output AND 19 through the OR element 23 shifts the information in the register 6 and it assumes the state 001, as a result of which the next pulse from the output of the generator 1 through the element 14 translates the trigger 11 into the state R, the key block 4 opens and the information is read

into the line. At the same time, the signal from element AND 14 through the element OR 23 shifts the information in register 6 and it assumes the initial state 0000. When a new command is issued to call a loop with an arbitrary number, the process is repeated.

Generator 9 codes (Fig. 2) works as follows.

If zero potential is present at the outputs F and F3 of register 6, then open-collector inverters 24-27 are closed and the ISO symbol code to the bus (Input GCI) is not generated. If there is a single potential at the F4-output, then the outputs of the inverters 25 and 27 present a zero potential signal, which is transmitted in the third and seventh bits of the eight-bit bus. ISO input, which corresponds to the service symbol code I. At the single potential at the F3 output of the register 6, the inverters 24 and 26 provide for the generation of an input to the bus of the Input ISO through the circuits of the second and fourth bits of the input Input ISO, which corresponds to the character code LF.

The decoder 5 (Fig. 3) works as follows.

A group of five elements AND 29 provides for the decoding of the symbols of the ISO code: L; LF; E; H; % The direct and inverse signals to the AND 29 element come from the outputs of the memory elements 2 directly or through inverters 28. A sign of a digit in the ISO code is the presence of signals in the fifth and sixth bits. Element 30 is used to decipher the digit feature while simultaneously building the signal from the output of generator 1. Inverter 32 serves to match the signal C4C with the input circuits of the device elements. With the aid of element 31, the signal is transmitted by the generator 1 of the signal L, the gated signal of the positive polarity LC is transmitted to the C2 recording control input of the register 6.

Counter 7 (Fig. 4) works as follows.

The information on the figure comes in the chains of the first four bits of the bus Output ISO (matching inverters not shown). The rest of the work counter has no features.

The device allows you to search for the desired memory addresses by writing special service characters - tags, followed by automatic regeneration of information, which allows you to simplify the device,

Claims (1)

Invention Formula A device for setting cycles in numerical control systems, consisting of memory elements, an address counter, a dual-band controlled pulse generator, an output key block, a subtracting two-digit decimal shift register register, two RS trigger, eight elements And, three elements com or, the address inputs of the element-20, by non-recognition of the H code of the controlled memory, are connected to the outputs of the address counter, the control input for the recording of memory elements is connected to the output of the first element OR, the installation input in O of the address counter is connected to the output of the second element OR, the first the input of which is connected to the bus of the initial installation of NU, the Start and Stop control inputs are external channels of the device, which, for the sake of simplicity, the device contains a controlled code character generator, a decoder characters the code, the zero state decoder of the counter and the delay element, the information inputs of the memory elements are connected to the input bus ISO input, the information outputs of the memory elements are connected to the inputs of the decoder characters of the ISO code and the information inputs of the output key block whose outputs are connected to the output bus of the device The ISO output, to which the information inputs of the subtracting two-digit decimal counter are also connected, the outputs of which are connected to the inputs of the zero state decoder of this counter, at the same time, the counting input of the address counter is connected to the clock input of the code decoder of the ISO code, the output of the dual-band controlled pulse generator and with the first inputs of the first and second elements AND, the S input of the first trigger is connected to the first input of the first element OR for two inputs , the first S-input of the second trigger and with the initial installation bus 0 WELL, R-input of the first trigger is connected to the output 7 of the ISO code character decoder and the first R-input of the second trigger, the direct output of the first trigger is connected to the first input of the first element AND, the output of the first element AND is connected to the first input of the third element OR, the second input which is connected to the output of the second element AND and the second R-input of the second trigger, the output of the third element OR is connected to the input of the shift shift control register, the output of the first bit of which is connected to the first input of the third element AND, the output of the second bit with one with the first inputs of the fourth and fifth AND gates, and also to the control input ge- five 0 five 0 five 0 five the code symbol generator, the output of the third bit of the shift register is connected to the first inputs of the sixth and seventh And elements and to the control input of generating the code LF of the code character generator; the output of the fourth bit of the shift register is connected to the second input of the second element And parallel control input the register record is connected to the output of the eighth element I, the first input of which is connected to the control input of the selection of the range of the dual-band controlled pulse generator, the control input of the output key block and the inverse output of the second trigger, the second input of the eighth element I is connected to the gated LS output of the code symbol decoder, the ungated L output of which is connected to the control input of the shift register and the counting input of the subtracting two-digit counter of the counting input the most significant bit of which is connected to the output of the third element AND and the third input of the third element OR, the record control input to the lower bit of the deducting ten-bit two-digit counter is connected to the output ohm fourth AND gate, a second input coupled to a second input of the third AND gate and a gated output of decoder characteristic numbers of code symbols, LF symbol whose output is connected to the second input of the fifth AND gate, whose output is connected to the input of the delay element and the first input the first OR element, the second input of which is connected to the output of the seventh AND element and the fourth input of the third OR element, the fifth input of which is connected to the output of the delay element, the second S-input of the trigger and the second input of the second OR element, the output of the sixth AND element is connected to the third S -the input of the second trigger, and the second input of the seventh element I is connected to the E-output of the code symbol decoder, the N-output of which is connected to the second the input of the seventh element is And, the third lR input of the second trigger is connected to the output of the zero state decoder of the counter, the third input of the first element OR is connected to the external circuit. Record yes, the first discharge input A ,, of the shift register is connected to the source of a single potential, and the inputs of the others bits and serial input AO receive information shift register connected to the source of zero potential. srig.5