SU1681298A1 - Path program control system - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in computer numerical control systems for process equipment, for example, in automatic machines for arranging wires into harnesses. The aim of the invention is to improve the reliability of the system in cases where its work program contains a large number of repeated cycles. The system contains a program input device 1, a switch 2, a control program development block 4, a drive control block 11, a cycle counter 5, a zero indication element 6, an inverter 9, two keys 8 and 10, a program memory block 3 and an OR element 7. Introduction the memory unit and the OR component into the system and changing the circuits connecting them to the switch has reduced the length of the control program and expands the technological capabilities of the system: work from one control program when its length allows to fit on the reels of the tape deck input, divide the control program into two programs, main and additional, with preliminary input of the additional program into the memory block with a large program length, or enter the control program into the memory block if the memory size is sufficient to accommodate the program, and work from the memory block. 2 hp ff, 4 ill. cl

Description

The invention relates to automatic control and is intended for use in computer numerical control systems for equipment, for example, an automat for wiring harness.

The aim of the invention is to increase the reliability of the system.

Figure 1 shows the structural circuitry of a contour software control system; Fig. 2 shows an embodiment of an electrical circuit of a commutator; on fig.Z - pulse distributor; 4 is a memory block.

The contractual software control system (FIG. 1) contains a program input device 1, a switch 2, a memory block 3.

programs, unit 4 for testing the control program, counter 5 cycles, display element 6, zero, element OR 7, first key 8, inverter 9, second key 10, and drive control unit 11. The outputs (the first data bus and the first sync signal) of the program input device 1 are connected to the first group of information inputs of the switch 2 and to the group of information inputs of the program memory block 3, the first input Stop is connected to the first input of memory block 3 and the third output of block 4, the second the input of which is connected to the output of the first key 8, the first group of information outputs (the first output data bus and the clock signal) of the switch 2 are connected to the inputs of block 4, the second

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the stroke (Subtraction) and the second group of information outputs (Repeat number) are connected respectively to the subtractive input and information inputs (number setting) of the counter for 5 cycles, the first output (Input-output) is connected to the second input of the memory block 3 and the first input of the element OR 7 , the address output group (address bus) is connected to the address input group of the memory block 3, the control input (About counter) of switch 2 is connected to the output of the zero-display element 6 and to the Disable input of the Counter 5 cycles. The second group of information inputs (second data bus and clock signal) is connected to the group of outputs of memory block 3. The third input of the start of the memory block 3 is connected to the output of the element OR 7, the second input of which is connected to the output of the second key 10, whose information input connected to the information input of the first key 8 is connected to the second output of the start of the block 4. The control input of the first key 8 , connected via an inverter 9 with a control input of the second key 10, is connected to the output of the display element 6 zero. The first outputs of block 4 are connected to the inputs of block 11 for controlling the drive.

In the practical implementation of a contour program control system, a photoelectric puncture device can be used as a program input device 1, which is controlled by Start and Stop signals from block 4 and has an output data bus (eight signals D1.1-D1.8 from puncture tape code tracks) with CD1 sync signal connected to switch 2 and memory block 3.

The switch 2 is made according to the scheme shown in figure 2, which contains the first distributor 12 pulses, multiplexer 13, decoders 14-16, the second distributor 17 pulses, block 18 registers, element 19 of the signal delay, the first and second elements OR 20,21 and RS trigger 22.

The control input (O of the counter) of the multiplexer 13 is the control input of the switch 2. The first and second information inputs of the multiplexer 13 are respectively the first group of inputs (the first data bus) and the second group of inputs (the second data bus) switch 2. The outputs of the multiplexer 13 are the first group of outputs (the first data output bus) of switch 2, are connected to the inputs of the decoders 14-16. Digital bits D1-D4 data buses connected to the data inputs of block 18

registers, form the second output bus (number of repetitions) together with the output signal 1T. The strobe of the second distributor 17 pulses and are

the second group of outputs of switch 2,

Sync path CD is connected to the counting T-input of the first 12 and second 17 pulse distributors. The R input of the first distributor 12 pulses is connected to

the fourth output I / O of switch 2 and to the output of the RS flip-flop 22, the R-input of which is connected to the output of the second element OR 21, and the S-input to the fourth clock output of the first distributor 12

pulses connected to the second input of the first element OR 20, the output of the gate of which is connected to the address bus, which is the fifth output of switch 2 and connected to the outputs of the register block 18, strobe inputs of which are connected to the corresponding clock outputs of the first distributor 12 pulses, S input which is connected to the output of the first decoder 14. The output of the second decoder 15 is connected to the input of the signal delay element 19, the output of which is connected to the first inputs of the first 20 and second 21 OR elements and is the third output ohm Subtracting the switch 2. The output of the decoder 16 is connected to the second input of the second element OR 21 and the S input of the second pulse distributor 17, the R input of which is connected to its output 1T.

Switch 2 decrypts the signals of the program in order to form from them: address signals for memory block 3, signals Number of repetitions and subtraction signal for a counter of 5 cycles, signals

for switching the operation of the system in different modes, in the mode of data transfer from the device 1 to enter the program in block 4, in the mode of simultaneous data transfer from the device 1 to enter the program in block 4 and

their recording in memory block 3, or the mode of data transfer from memory block 3 to block 4. Each of the distributors 12.17 pulses can be performed according to the scheme shown in Fig. 3, which contains

signal delay element 23, trigger 24, four AND 25.1-25.4 elements, and a pulse counter 26 with a built-in decimal decoder. Input T, connected to the first inputs of elements And 25.2-25.4 and through

element 25.1 - with the counting input of the pulse counter 26, is the counting input of the pulse distributor 12 (17), the input R of which, connected via the signal delay element 23 to the R inputs of the trigger 24 and the pulse counter 26, is input

Resetting prohibiting work on input T,

The input D of the trigger 24, together with the input C and the input S, are the installation inputs and permit operation at the input T. The output of the trigger 24 is connected to the second input of the AND element 25.1. The first, second and third outputs of the counter 26 pulses are connected respectively with the second outputs of the elements And 25.2-25.4. The outputs of the elements 25.2-25.4 and the fourth output of the pulse counter 26 are respectively the clock outputs 1T, 2T, 3T, 3T of the distributor 12 (17) pulses.

The multiplexer 13, made according to the standard scheme, provides data transmission to the output data bus, depending on the potential, the signal at its control input.

Decoders 14-16 can be performed on the elements NOT, I.

The decoder 14 defines in the output data line the program line with the address N of the repetitive region. The decoder 15 - the end of the repeating section. Decoder 16 - the number of repetitions.

Block 18 of registers stores the number of a repeating program section before changing it with a new number received from the program, and can be executed on three ICs of the 1551M5 type, each of which contains four D-flip-flops.

The signal delay element 19 serves as a signal time delay. The end of the repeating program section from the output of the decoder 15 to the input of the OR element 20 is necessary for recording the end of the repeating section into memory block 3 and switching it from input mode to output mode.

The trigger 22 determines the operation mode of the memory block 3 (Input or Output). The memory unit 3 can be made according to the structural scheme shown in FIG. 4, which contains an OR element 27, a pulse generator 28, an AND element 29, a HE element 30, a pulse distributor 31, an address counter 32, a memory drive 33 and a driver 34 impulses sync path (CD2).

The data set inputs with the address input of the counter 32 addresses are a group of address inputs (an address bus with a gate) of memory block 3, the first input of which Stop is connected through the OR element 27 to the first input of the element AND 29, the fifth Start input is connected to the second the input element AND 29. The first group of inputs (the first data bus with the CD1 clock signal) is connected to the data bus of the memory drive 33, with the CD1 clock signal, to the C input of the pulse distributor 31, with the first data bus. The third input I / O is connected to the input Write-read of the memory drive 33 of the memory, to the input D of the distributor 31 pulses and through the element NOT 30 to its S-input. The data outputs of memory drive 33 and v: drive pulse generator 34 (CD2) is a group of outputs (second data bus CD2) of memory block 3. The output of the generator 28 pulses connected to the third input element And 29, the output of which is connected to the first counting input of the distributor 31 pulses, the input R of which is connected to its output ST, the output 2T connected to the counting input of the counter 32 of the address, the outputs of which are connected to the address inputs of the drive 33 the memory, the input sample of the microcircuit GE of which and the input of the imager 34 pulses are connected to the output 1T of the distributor 31 pulses. The CD2 shaper (pulse width shortener) can be executed on an AND element with an integrating chain. As a block 4, a numerical control device such as a DSS can be used.

As a counter of 5 cycles, a reversible counter with a Barring element (series-connected elements NOT and AND) at the subtractive input can be used.

As element 6 of the indication of the zero element OR NOT.

As the first and second keys 8 and 10, the element I. As the drive control unit 11 can be used

commercially available thyristor control unit BTU3601, which is designed to control DC motors.

The konturny software control system works as follows.

The program of the system, recorded on punched tape, usually contains non-repeating sections and repeatedly repeating sections of the program. In this system, multiple repeating sections are assigned numbers at the beginning of the section, and at the end of the section there is the symbol End of the repeating section and the number of repetitions of this section of the program,

which is recorded on a punched tape once together with non-repeating sections of the main program. You can also create a separate program from multiple repetitive program sections and

pre-enter it into the memory block. In this case, in the main program, the numbers of repeating sections and the number of their repetitions are indicated in the necessary sequence.

The program is entered into block 4 frame by frame, at the end of each frame from block 4, a stop signal is sent to device 1 and program block 3 of memory, stopping the next frame to be entered until the end of the system’s execution by the executive bodies of the previous frame information system. At the end of the test, the Start signal is selected, which includes the input of the next program frame.

Before operation, the system is reset by a reset signal to the initial state, at which the switch 2 is in the mode of data transfer from the program input device 1 to the block 4, the first key 8 is open, and the second key 10 is in the closed state. On the Start signal, the program input device 1 is started via the first public key 8 and information from the punched tape enters the switch 2, where it is transmitted to block 4 through multiplexer 13 and processed by the drive control unit 11. This continues until the address line appears in the program. The number of the repeated program section, according to which in switch 2 on decoder 14, signal 1 is output to input S of pulse distributor 12, where the trigger sets (fig. 3) 24 into one state, permitting the operation of the distributor 12 then to the counting T-input. The signal CD arriving at this time at the input T through the element I 25.1 to the counting input of the pulse counter 26 switches it to the first state only after the termination of the signal CD (according to its cut). In this case, from the first output of the pulse counter 26, the enabling signal arrives at the second input of the And 25.2 element. The next CD sync signal of the first digital line of the repeating section number, which arrives at the first input of the And 25.2 element, generates the first 1T clock signal. The 1T signal is fed to register block 18 and gates recording from the output data bus of multiplexer 13 to the higher bits of block 18 of the registers of the first digital line of the repeating segment number. At the end of the 1T signal, the pulse distributor 12 switches to the second state. The next (second) digital line at signal 2 is written into the next bits of register block 18, and so on. After the recording of the numerical value of the number of the repeating program section in the register 18 block in the pulse distributor 12, a 4T signal is generated, which is fed to the trigger 22 and the OR 20 element. The signal from the OR 20 element gates the recording of information from the 18 register block on the address bus to the 3 block

a memory, where the address counter 32 and the memory drive 33 connected to it are set to the corresponding address information. Signal from trigger 22, incoming

5 to the input S of the distributor 12 pulses, sets it to the initial state, and the input to the output of the switch 2 through the I / O circuit to the memory block 3, sets it to the input mode and through the element

0 OR 7 as a start signal enables the operation of block 3 of the memory in input mode. Information from the program input device 1 at the same time as being transferred to block 4 is then recorded in memory block 3 as follows (see Fig. 4). The input mode sets the enabling potential at the input D of the pulse distributor 31 and switches the memory 33 of the memory to the write mode. With the arrival of a line of information on

0, by the first data bus on the CD1 sync signal, the pulse distributor 31 is set to the state permitting its operation at the counting input to which the pulses are received from the generator 28

5 through element I 29 and at resolving potentials at its first and second inputs (there is a Start and no Stop). The first pulse slice translates the pulse distributor 31 into the first state. On the second pulse, a 1 T signal is generated, which is fed to the input of the Selection of the CE chip of the memory drive 33, according to which information from the first data bus is written into the memory. Next 2T signal with

5, the pulse distributor 31 enters the counting input of the address counter 32 and switches it to the next state. The outputs of the counter 32 addresses connected to the address inputs of the memory drive 33 change its address. At the ST signal, the pulse distributor 31 returns to the initial state and is ready to receive information from the next program line. This process of recording information in memory block 3

5 will continue until the program displays a line with the address. The end of the repeating section, which is also recorded in the memory and according to which in switch 2 on the decoder 15 is allocated

0 signal arriving through the element 19 of the signal delay on the elements OR 20,21.

The signal from the OR element 21 switches the trigger 22, which along the I / O circuit puts the memory block 3 into the output mode and

5 through the element OR 7 stops the operation of the memory block 3. The signal from the OR element 20 re-gates the recording of stored information in register block 18 via the address bus to memory block 3, setting it to the starting address of the recorded program section. Next, from the program, switch 2 receives the line with the address Number of repetitions, by which the decoder 16 extracts a signal, which arrives at the input of the pulse distributor 17 and allows it to work at the input T, to which the CD sync track signal arrives at this time, after which the distributor 17 pulses are set to the first state.

Next, the program receives the next digital line with the number of repetitions. The sync track signal accompanying the program line in the distributor 17 generates a signal 1Т, which over the bus the number of repetitions builds its record in the cycle counter and resets the distributor 17 pulses to the initial state on the input. The number recorded in the counter 5 cycles changes the state of the zero indication element 6, the signal from which, coming to the control input of the multiplexer 13, switches it to the data transfer mode from the memory block 3 to the block 4, simultaneously the signal from the zero indication element 6, acting on the first key 8, closes it, and through the inverter 9 opens the second key 10. The first key 8 stops the program input device 1, and the second key 10 switches the memory unit 3 into operation, which was previously set to output mode . Information is output from memory block 3 as follows (see FIG. 4). In the output mode, the memory drive 33 is set to read mode, and through the NOT 30 element, a potential is applied to the S input of the pulse distributor 31, setting it in the state permitting operation via the T input. According to the Start signal (in the absence of a Stop signal), the pulses from the generator 28 through the element 29 are fed to the T input of the pulse distributor 31, the output of which produces a sequence of 1T, 2T, 3T clock pulses. In the 1T cycle, data is selected in the memory drive 33 by the source address and the shortened CD2 pulse is generated by the pulse shaper 34, which are transmitted to Switch 2 on the second data bus to multiplexer 13 and then to block 4. By the 2T clock, the address counter 32 switches the drive 33 memory to the next address. In an ST stroke, the pulse distributor 31 returns to its original state. Next, starting at 1T, the process repeats. Information output from memory block 3 will continue until information appears on the second data bus. The end of the repeating section, along which in switch 2

Decoder 15 extracts a signal that, through element 19, the delay of the signal per element OR 20 again gates recording the stored information in register register 18 via the address bus to memory block 3, setting it again to the starting address of the previously recorded program section. At the same time, the signal from the decoder 15 through the element 19 of the signal delay arrives at

0 subtracting the input of the counter 5 cycles and reduces the number of repetitions set in it by one. Repeated output of information from memory block 3 is performed as many times as recorded in the counter.

5 5 cycles. When zeroing the counter of 5 cycles, the signal from the zero indication element 6 sets the system to its initial state for transmitting information from the program input device 1 to block 4. The next signal

0 The start-up includes a program input device 1 to continue operation from punched tape.

If according to the nature of the system's operation of repeatedly repeated program sections, we are always different from each other, it is possible to simplify the circuit of switch 2 by eliminating the distributor 12 pulses and register block 18, and the output of the decoder 14 is connected to the second input of the element OR 20,

0 whose output is connected to the setup input to zero (not shown in the diagram) of the address counter 32, i.e. In this case, all the repeated program sections will be entered into the memory block 3, always starting with the same

5 (zero) addresses while erasing the previous entry. In the program, the command Number of the repeated section will be called the Start of the repeated section and contain only one

0 string punched tape. In this case, it is also possible to exclude the decoder 15 and the OR 21 element from the circuit, while the output of the decoder 16 is connected to the input of the delay element 19 of the signal, the output of which is connected to the R input of the trigger 22. In this case, the End Section command is excluded from the program. the function will be performed by the address line Number of repetitions, which will be recorded in memory block 3.

0 In the 5-cycle counter, the Inhibit input is entered to exclude its operation in the subtraction mode in its zero state. A counter of 5 cycles is used in a one-decade version to simplify the description.

Claims (3)

The use of this contour software control system as compared to the prototype will improve the reliability of the system operation by eliminating the second program input device from it, which is the most unreliable in the system due to the presence of punched tape and electromechanical components, which often go out of order and require periodic adjustments. Claims 1. A software control system comprising a program input device, a switch, a control program test block, a cycle counter, a display element zero, first and second keys, an inverter, a drive control unit, the data output device group of the program input device connected to the first group the information inputs of the switch and is the first data bus containing the sync signal bit; the first information group of the switch outputs is connected to the group of inputs of the program The control codes are the first data output bus containing the sync signal bit, the first, second and third outputs of the control program development block are connected to the first input of the program input device, the second input of which is connected to the control input of the drive control unit, information inputs of the first and second keys to the output of the first key, the control input of which is connected to the output of the display element and the input of the inverter, the output of which is connected to the control input of the second key, the second group of information the switch outputs are connected to an information input of a cycle counter, the output of which is connected to a zero indication element, characterized in that, in order to increase reliability, a program memory block and an OR element are inserted into it, and the program memory block is connected by a first input to the first input the program input devices, the group of information inputs of the program memory block is connected to the output group of the program input device, the group of outputs of the program memory block is connected to the second group of information inputs of the switch and is With a second data bus containing a sync bit, the address group of the program memory is connected to the switch output address group and is an address bus containing the strobe bit, the second input of the program memory is connected to the first output of the switch and is connected to the first the input of the OR element, the second input of which is connected to the output of the second key, and its output to the third input of the program memory, the second output and the control input of the switch are connected respectively to the subtraction input of the cycle counter and to the output display element zero, which is connected to the input of the Loop counter inhibitor. 2. The system of claim 1, wherein the switch comprises a multiplexer, three decoders, a block of registers, the first and second elements OR, the RS flip-flop. the delay element, the first and second pulse distributors, the first and second groups of information inputs The switch 0 is connected respectively to the first and second multiplexer inputs, the control input of which is the control input of the switch, the first group of information outputs of which 5 is connected to the inputs of three decoders, the first four bits of the data of the first output bus connected to the data inputs of the register block with the output signal of the second distributor 0 pulses are the second data output bus and are connected to the second group of information outputs of the switch, the sync signal of the first output data bus is connected to the counting input 5 of the first and second pulse distributors, the R-input of the first of which is connected to the fourth output I / O of the switch and to the output of the RS flip-flop, the R-input of which is connected to the output of the second element 0 OR, and the S-input with the fourth clock output of the first pulse distributor connected to the second input of the first OR element, the output of which is connected to the group of address outputs 5 of the switch connected to the outputs of the register block, the gate inputs of which are connected to the first, second and third clock outputs of the first pulse distributor, whose S input is connected to the output of the first decoder, the output of the second decoder is connected to the input of the delay element of the signal whose output is connected to the first inputs of the first and second OR elements and is the second output 5 of the switch, the output of the third decoder is connected to the second input of the second OR element and the S input of the second distributor, the R input of which is connected to its output of the Strobe. 0 3. The system according to claims 1 and 2, characterized in that each of the pulse distributors consists of a signal delay element, a trigger, four AND elements, a pulse counter with a built-in ten decoder, a T-input of the pulse distributor connected to the first the inputs of the four elements And through the first element And with the counting input of the pulse counter, is the counting input of the pulse distributor, whose R input, connected through the delay element of the signal with the R inputs of the trigger and pulse counter, is the Reset Distributor input, the setup inputs D, C, S of which are the corresponding trigger inputs, the output of which is connected to the second input of the first element, And the first, second, third the outputs of the pulse counter are connected to the second inputs of the second, third, and fourth elements, respectively, whose outputs and the fourth output of the pulse counter are respectively the clock outputs of the pulse distributor. ami om2 fig.Z $