SU798731A1 - Multichannel apparatus for step motor control - Google Patents

Description

one

The invention relates to automation and computer technology and is intended for use in automated control systems based on digital computers (DVM),

A device for controlling stepper motors is known, comprising a digital computer, registers, counters, triggers, phase switching circuits of stepper motors, elements I, and a clock generator 1.

The closest in technical essence to the present invention is a digital device for controlling stepper motors, containing a clock pulse generator, an address block connected to a digital computer, an register-counter counter, triggers and elements connected to them AND, random access memory, differential read amplifiers, read amplifiers, reversible switching circuits, power amplifiers in the phases of 2J stepper motors

These devices have significant disadvantages t

a) time of processing the value of each step motor in the group Vavk

but the time to work out the maximum. the values for one of the stepper motors, which prevents the use of this device in real-time control systems;

b) the devices do not provide continuous input of values, i.e. no can work in continuous mode

o tracking;

c) the presence of a separate reverse phase switching circuit for each stepper motor and an additional random access memory with the circuits necessary for its operation complicates the device and increases its dimensions, d) the lack of control over the operation of the device does not provide improved accuracy of the output of values to the stepper motors.

The purpose of the invention is to enhance the functionality and simplify the device.

five

Expansion of functionality consists in providing the possibility of continuous input to stepper motors, i.e. continuous tracking mode, which allows to name it in control systems operating i real-time. Simplification of the device consists in the abandonment of the buffer storage device with complex control schemes, in the abandonment of the reversible switches for each stepper motor, and in the construction of the device using the elementary computer nodes of the type AND, OR, T, providing the simplest linear connections. The goal is achieved by the fact that in multi-channel devices. for controlling stepper motors, containing a register, pulse counter, calculator, the first output of which is connected to the first input of the first trigger, the second output to the input of the address block, and the third output to the inputs of the second trigger, connected to the first inputs of the corresponding first And elements, the second inputs of which are connected to the output of the second element And connected by the first input to the output of the first trigger, and the second input to the output of the clock generator, and in each control channel the power amplifier unit, with Single outputs with stepper motor inputs, the first comparison block, the first and second OR elements, the third OR block, the commutator connected in series, the second comparison block and the fourth OR block, and into each control channel are entered. and series-connected delay elements, a block of third AND elements, a block of memory elements and a block of fourth AND elements, the output of which is connected to the second inputs of the second comparison unit and through the block of the third OR elements to the inputs of the first OR element, and watts These inputs are connected to the input of the delay element and to the outputs of the address block, the output of the first comparison block is connected to the first input of the calculator and the second input of the first trigger, the first inputs of the second register to the fourth output of the calculator, and the second inputs through the counter-pulses - from the output of the second OR element and with the first output of the calculator connected by the second input to the output of the first OR element, the second inputs of the block of the fourth OR elements are connected to the outputs of the second AND elements, and the outputs to the switch inputs, and each channel is controlled and the outputs of the power amplifier unit are connected to the corresponding input of the second element OR through the fifth element OR of this cocoa, and the second inputs of the block of the third AND elements to the switch outputs. The drawing shows the functional diagram of the device. The device contains a calculator 1, a generator of 2 clock pulses, the first trigger 3, the second trigger 4 and 5, the first element OR b, the second element and 7, the first elements AND 8 and 9, the address block 10, the register 11, the counter 12 pulses, the switch 13, the first 14 and second 15 comparison blocks, block 16 of the fourth element OR 16i, .. 16j. block 17 of the third element OR 17. . 17fy ,, delay element 18, block 19 of the third elements AND 19 ... 19 ,, block 20 of the element 20 ... 20 memory, block 21 of the fourth elements AND 21 ... 21, block 22 of the amplifiers 22 / i ... 22 yy, power, stepper motor 23, fifth element OR 24, and second element OR 25. Functional units containing generator 2, trigger 3, element 7, triggers 4 and 5, elements 8 and 9, register 11, counter 12 and comparison block 14 are used to form a stack of units of unitary value codes and to end the device operation cycle. The functional units containing the switch 13, blocks 16, 19, 20, 22, and 10 are intended to distribute units of units of unitary codes of magnitudes across the phases of the stepper motors 23. The functional blocks 15, 21, and 17 are used to set the switch 13 to a state corresponding to the phase selected for entering the motor size 23. Functional units containing the element OR b, the element OR 24, the comparison unit 14, the inputs of which are connected to the outputs of the register 11 and the counter 12, and the element OR 25 are used in the device for generating control signals Ota. The device works as follows. When the supply voltage is applied to the device, the calculator 1 sets up groups of elements 20 ... 20 of the block 20 belonging to the corresponding motors 23 in the state that coincides with the output states of the switch 13. For this, the calculator 1 produces a sequential output of the address codes of the motors 23 to block 10. Each signal from block 10 is resolving for elements AND 19 ... 19 1 of block 19 of the selected motor 23. When this signal is received by elements AND 19 ... 19, block 19, the output states of switch 13 are transmitted to the elements 20... . 20y), block 20 and from the outputs of these elements to amplifiers 22 ... 22 (engine block 22, after the initial installation, the device operates in the input mode for the motors 23 before removing power from the device blocks. The input to the motors 23 proeevolts cycles, the frequency of which is equal to the frequency of operation of the engines 23, and in ka cycle, a unitary code unit (pulse), for each motor 23, units (pulses) of the unitary code are fed to the inputs of the switch 13 to change its state. The changed state of the switch 13 is transmitted to the elements 20,. . 20 of the block 20 for controlling the amplifiers ... 22 c, the block 22 and further with the phase 1 of the engine 23 chosen by the calculator 1 at the address. When issuing a unitary code unit for one engine 23, numerator 1 produces a sign of this value from the output via the transfer line of the sign to triggers 4 and G, the sign of the code of the address of the engine 23 selected to enter this value, from the output of the calculator 1 s 10 is the code for the number of motors 23 selected for inputting the values in the cycle to register 11. The signal from the output of block 10 is resolving for the elements of AND 21. . .21 of block 21 belonging to the selected motor 23. When this signal appears at block 15, a comparison of the output states of the switch 13 and the states of elements 20 ... 20j of block 20, which arrive at the input of block 15 by means of elements 21, occurs. . .. 21 wt block 21 and. elements OR 17 ... 17u, block 17. If the states of the indicated functional units do not match, block 15 generates a signal that the output states of the switch 13 correspond to the states of the elements 20. .. 20 block 20, related to the selected engine 23, i.e. the states of its phases. Next, the calculator 1 issues a control signal from the output to begin forming a pack of units (pulses) of unitary codes of the values selected by the calculator 1 for the device operation cycle. This signal is transmitted via the control bus to a single input of trigger 3, the signal from the output of which allows passage of the generator 2 through the element 7 to the elements 8 and 9. The signal from the output 1) from the triggers 4 or 5 characters at the input of one of AND 8 or 9 elements allow the clock pulse to pass through the corresponding OR element of block 16 to the summing or subtracting input of switch 13. This changes the state of switch 13. By means of the signal from block 10, through element 18, this new state of switch 13 is transmitted by elements And 19. .. block 19 into elements 20 .. .iOrn of block 20 and through amplifiers 22 ... 22 of block 22 to the phases of the selected motor 23. At the time of appearance at the outputs of the OR elements 17x1 .. .17 of the block 17, the states of the elements 20-. .. 20w of the block 20 (phases) of the selected engine 23, the element OR 6 generates a signal that is fed to the input of the calculator 1. This completes the issuance of a unitary code unit for the phases of one engine 23, and the calculator 1 prepares for issuing the address of the next engine 23. The composition of operations when issuing a unitary code unit of the value to the next motor 23 is maintained. The difference lies in the use according to the address of the engine of 23 other groups of elements AND 19. ... 19 wi of block 19 and 21x1 ... 21u, 1 of block 21, elements 20 ... 20 of block 20 and amplifiers 22 ... 22u of block 22. At the same time, the appearance of a new address from block 10, a comparison of the states of switch 13 and elements 20. .. 20 (block 20 occurs before the next clock pulse appears. Thus, in the operation cycle of the device, a pulse burst is formed from the clock pulses of the generator 2, each of which is a unitary code of one of the values selected for output to the motors 23 in this cycle. In each cycle, the operation of the device is controlled with the help of a number of signals: element OR b generates a control signal for the unit (pulse) unitary code per unit 20 ... 20 4 of block 20, i.e. a control signal for the high-speed part of the device; each of the elements OR 24 forms the signal when the phases of the corresponding engine 23 are switched and controls the passage of a unit (impulse) unitary code value to the phases of the engine 23, i.e. it controls the operation of the slowly acting part of the device - amplifiers 22 engines 23; counter 12 counts the number of signals from the OR element 25, which is received at its inputs from the elements of OR 24; block 14 generates a signal of the health of a group of engines 23 when it coincides at its inputs. codes from the counter 12 and from the register 11. On this signal, the trigger 3 prohibits the passage of clock pulses through the element 7 to the elements 8 and 9, and the calculator 1 receives information about the end of the device operation cycle. The absence of a signal from block 14 at the time allocated for the calculator 1 in the device, indicates a malfunction of one of the amplifiers 22 ... 22 of block 22 or some phase 23 of the engine 23. The search for a faulty engine 23. and faulty power amplifiers produces calculator 1 by issuing in each cycle the addresses of only one engine 23 in block 10 and 1 in register 11.

During normal operation of the device and healthy stepping motors, the limiting cycle is the period of frequency of operation of the stepping motors. The same frequency is used to generate bursts of pulses (units) of unigar stakes of quantities. The total number of cycles is limited by the total operating time of the device in the mode of outputting values that the calculator’s storage unit generates and stores.

The frequency of pulses (units) of unitary codes in a bundle is determined by the frequency of switching addresses of engines 23, and the frequency of switching addresses depends on the speed of the radio element components of the device and the time of resolution in the calculator of the problem of forming the address of engine 23.

The frequency of the clock pulses of the generator 2 is selected in accordance with the frequency of formation of the addresses of the motors 23, taking into account the speed of the block 15.

The proposed device is used to control stepper motors in the continuous input mode, while ensuring autonomy of each value, which is especially important for control systems operating in real time.

The proposed device simplifies the known, since it allows you to refuse a buffer storage device with complex control schemes, reverse switches for each stepper motor and build a device of similar purpose using elementary computing nodes of type AND, OR, t, while using the simplest linear connection.

The proposed device, when used for controlling 50-hectare stepper motors, is 2 times smaller than the available one, which makes it possible, while maintaining the dimensions of the known device, to increase its reliability by full redundancy. The presence of control signal generation units of the high-speed part of the device and its low-speed part allows using these signals to programmatically enter quantities to stepper motors, to improve the accuracy of quantity input, since the control signals can fix the address of the faulty stepper motor and the group of control nodes of any stepper motor in each the device operation cycle, while the accuracy of control of the input of the value is a unit of the unitary code, and the accuracy of determining the faults of the phases is stepwise of the engine - one specific stepper motor, and improve the performance of the device, hence reducing the occupancy calculator issuance quantities per group SD to 10% instead of 25% occurring at present.

Claims (1)

1. USSR author's certificate №419850, cl. G 05 B 19/40, 1972. 2 o USSR author's certificate No. 411436, cl. G 05 19/40, 1972 (prototype), TUI