SU1591014A1

SU1591014A1 - Microprogram control device

Info

Publication number: SU1591014A1
Application number: SU874345364A
Authority: SU
Inventors: Grigorij N Timonkin; Vyacheslav S Kharchenko; Valentin P Ulitenko; Andrej G Zolotarev; Sergej N Tkachenko; Boris O Speranskij
Original assignee: Grigorij N Timonkin; Vyacheslav S Kharchenko; Valentin P Ulitenko; Andrej G Zolotarev; Sergej N Tkachenko; Boris O Speranskij
Priority date: 1987-11-16
Filing date: 1987-11-16
Publication date: 1990-09-07

Description

The invention relates to automation and computing and can be used to build programmable controllers. The purpose of the invention to improve the performance of the device. The device contains the micro-command address counter, the first and second demultiplexers, ϋ-trigger, LK-trigger, start trigger, group of comparison circuits, one-shot, seven elements I. element OR, memory of micro-instructions, register, group of trigger, clock pulse generator. The essence of the invention is to increase the speed of the firmware control device based on the introduction of a new discipline of functioning, based on the method of coding micro-instructions at the level of conjunctions. The goal is achieved through the introduction of a group of triggers, O-t'rigger, ϋΚ-trigger. groups of comparison circuits, the first and second demultiplexers. 1 il.

The invention relates to automation and computing and can be used to build programmable controllers, in particular, implementing the time Boolean functions.

The aim of the invention is to increase the speed of the device.

The invention consists in increasing the speed of the firmware control device based on the introduction of a new functioning discipline based on the method of coding micro-instructions at the conjunction level.

The drawing shows a functional diagram of the device.

The firmware control device contains block 1 of microinstructions memory, counter 2 addresses of microinstructions, register 3 numbers of logic functions, group 4 triggers (register of values of logic functions), second 5 and first 6 demultiplexers, O-trigger 7 (calculated value of conjunctions), κ-trigger 8 (controls), trigger 9 start, generator 10 clock pulses, group of comparison schemes 11, first 12, second 13, third 14, fourth 15, fifth 16, seventh 17 and sixth 18 elements AND, element OR 19, one-shot 20, input 21 operation codes, start input 22, stop 23 input, input s 24 logical conditions, information output 25 function values, the output end 26 sync computing device functions.

Memory block 1 is used to store and

issuing microinstructions with a computed conjunction included in a logic function.

Counter 2 addresses microinstructions serves to

the formation of the address of the microcommand block

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3

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four

1 memory. Register 3 of the logical function number is intended for receiving, storing and issuing information about the number of the calculated Boolean function.

The group of triggers 4 (the register of the value of a logical function) is intended for receiving, storing and issuing information about the computational value of a logical function.

The first b and second 5 demultiplexers are designed to convert the positional code arriving at their inputs into a unitary code. Therefore, at one of the outputs of the first 6 and second 5 demultiplexers, a signal of the computational value of a logic function and a signal permitting the writing of this value to the corresponding information input of the register 3 of the values of the logic function appear.

The trigger 7 is used for receiving, storing and issuing the calculated value of the conjunction included in the logic function on the control input of the second demultiplexer 5 and the input of the one-shot 20.

The trigger 8 is designed to control the operation of the firmware control device, to enable or disable, at the corresponding times of the passage of signals through the fourth 15 and fifth 16 elements I.

The trigger 9 start device firmware control is designed to start and stop the device. The generator 10 is used to synchronize the operation of the firmware control device.

The group of comparison circuits 11 is intended for issuing single signals in case of coincidence of the values of signals received from a group of inputs 24 of the logical conditions of the device and from the corresponding bits of the microcommand of memory 1, as well as if the variable is not part of the conjunction.

The comparison circuit generates a single signal, if the variable is not included in the conjunction or is included in its real value, it converts the conjunction into unity (for single values of other variables or their negations included in this conjunction).

The first element And 12 is designed to calculate the conjunction included in the logic function.

The second 13, third 14, fourth 15, fifth 16, sixth 18 and seventh 17 elements AND, elements OR 19, one-shot 20 are designed to control the operation of the firmware control device,

The firmware control device operates as follows.

When the power is turned on, all the memory elements are reset to "0" and the start trigger 9 is set to "1" (the initial state setting circuits are not shown conventionally).

On the falling edge of the first clock pulse coming in from the first output

10.1 of the generator, through the open second element I 13, the addresses of the first micro-command are written into the counter 2 of the micro-command addresses.

The first clock pulse in the second output 10.2 of the generator switches the control trigger 8 to one state and through the second input of the fifth element I 16 synchronizes register 3 on the falling edge, as well as resetting the trigger 7 to the zero state. On the falling edge of the synchronization signal, the number of the logical function is written to the register 3 from the memory 1 of the first microcommand.

The second clock pulse from the first output 10.1 of the generator 10 passes through the third element I 14, which is open at the inverse input connected to the inverse output of the trigger 8, and increases the contents of the counter 2 by one.

Selected at the second address of the counter 2 micro-command of the values of the logical variables included in the conjunction, goes to the corresponding inputs of the group of the comparison circuit 11. Comparison of each category of logical variables is performed in the event that the signal controlling the comparison is zero, i.e. if the corresponding logical variable is part of the conjunction.

If the comparison of the logical variables included in the conjunction is allowed, and the values of these variables are equal to each other, then the outputs of the group of the comparison circuit 11 receive signals of the logical "1" and arrive at the corresponding input of the first element And 12. In this case, the conjunction included in the logical the function is equal to one, and there is no point in finding the values of the other conjunctions.

A single signal from the output of the first element And 12 is fed to the information input of the trigger 7 and the trailing edge of the sync signal from the output of the fourth element And 15, translates it into a single state.

The signal from the output of the trigger 7 is fed to the control input of the second demultiplexer 5, thereby allowing the passage of information through it from the outputs of the first register 3.

On the leading edge of this signal, the one-shot 20 operates and through the element

five

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OR 19 allows the control input of the first demultiplexer 6 to pass information from the output of register 3, and therefore write the calculated value of the logic function to register 4. In addition, the signal from the output of the element OR 19 is output to output 26 and switches trigger 8 to the zero state and prepares the passage of the sync pulse from the first generator output, and depending on the signal at the device input 23, the trigger 9 is set to “0” and the device stops.

When the device restarts to calculate the next function or when the signal at input 23 is zero, the next clock pulse from the first generator output 10.1 through the second input of the second element And 13 synchronizes the counter 2 to receive the address of the next microcommand, which is determined by the number of the calculated logic function.

If the corresponding logical variables are not included in the conjunction, then at the output of the group of comparison schemes 11 corresponding to these logical variables, the logical "ической" signals appear and arrive at the corresponding inputs of the first element 12 and are perceived as unit values of the variables included in the conjunction.

Thus, a cyclical analysis of conjunctions included in a logical function is performed.

If the logic variables supplied to the inputs 24 of the firmware control device do not coincide with the required values of the variables in the conjunctions, the cyclic analysis reaches the last microcommand for calculating the logic function, and the command end signal appears in the low-order microcommand of memory 1, the first input of the sixth element And 18 prepares it for the passage of signals.

The next sync pulse from the second output 10.2 of the generator passes through element 18 and element 19 and switches the trigger 8 to the zero state, opening element 13 for passing the clock pulses.

The next sync pulse from the first output 10.1 of the generator through the element And 13 synchronizes the recording of the address in the counter 2.

Thus, the operation of the firmware control device can be repeated provided that the corresponding code of the following logic function is fed to the device inputs 21.

If during the operation of the firmware control device there is a need to finish the work, then you can use the device stop input 13. In this case, when a single signal appears at the output of the OR 19 element, the trigger 9 for the start switches to the zero state, the generator 10 stops operation and the device stops.

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Claims

Claim

A firmware control device containing a counter, register, start trigger, microinstructions memory block, first to seventh And elements, one-shot, clock generator, OR element, with the device start input connected to the installation input of the start trigger "1", the output of which is connected with the start input of the clock pulse generator, the first output of which is connected to the first inputs of the second and third elements I, the outputs of which are connected respectively to the synchronization and addition inputs of the counter unit, information the output of which is connected to the address input of the memory block, the output of the microcommand field of which is connected to the information input of the register, the output of the "End of command" feature of the memory block of microcommands is connected to the first input of the sixth And element and to the inverse inputs of the fourth and fifth And elements, the second output of the clock generator is connected with the first direct inputs of the fourth and fifth elements And with the second input of the sixth element And, the input of the operation code of the device is connected to the information input of the counter, characterized in that performance, it additionally contains an O-trigger, LC-trigger, the first and second demultiplexers, a group of triggers, a group of comparison circuits, and the stop input of the device is connected to the first input of the seventh element And, the output of which is connected to the installation input in ”0” trigger start, the second output of the clock pulse generator is connected to the L- and C-inputs of the LC-trigger, the direct output of which is connected to the second direct input of the fourth element I, the output of which is connected to the synchronization input of the O-flip-flop, the output of which is connected to iruyuschim input of the first demultiplexer and the input of monostable multivibrator, whose output is connected to the first input of the OR gate, whose output is the output of the synchronization device and is connected to the reset input of latch LC, a second input of the seventh AND gates and gating

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the input of the second demultiplexer, the outputs of which are connected to the synchronization inputs of the trigger group, the outputs of which are information outputs of the device, the inverse output of the EC-trigger is connected to the second 5 input of the second element And, the inverse of the third element And the second direct input of the fifth element And whose output is connected with the installation input in the "0" O-trigger and the synchronization input register, the output of which is connected to the information inputs of the second and first demultiplexers, outputs

ten

the first demultiplexer is connected to the information inputs of the group triggers, the inputs of the logic conditions of the device are connected to the first inputs of the group comparison circuits, the outputs of which are connected to the inputs of the first I element, the output of which is connected to the information input of the trigger, the high and low bits of the microcommand field of the micro-memory command are with a gate input and the second inputs of the group comparison circuits.