SU1386986A1 - Data input device - Google Patents

Abstract

The invention relates to automation and computing and can be used to enter information from analog sensors into a computer. The purpose of the invention is to expand the field of application of the device by organizing a multiple cyclic polling mode and providing direct access to computer memory. The device comprises a switch 2, an analog-digital converter 3, a first counter 4, a first register 5, a second register 6, a comparison block 7, a second counter 9, a third counter 10, a control block 12. Before the start of measurements, the boundary numbers of channels are recorded in registers 5 and 6, the total number of measurements is loaded into counter 9, and the starting address of direct memory access is loaded into counter 10. At the start signal of the counter 10, the operation of the analog-to-digital converter 3 begins. At the time of the end of the measurement, an exchange request is sent to the computer via one channel. At the end of the recording of information in the computer memory, it generates a signal for the end of the recording. When counter 9 overflows, the end of exchange signal is generated. The combination of the numbers loaded into registers 5, 6 and into counter 9 can interrogate either all channels, or a selected group of channels, or only one channel with the maximum frequency. 1 hp f-ly, 2 ill. Q 9 (/ С

Description

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The invention relates to automation and computing and can be used to enter information from analog sensors into a computer.

The purpose of the invention is to expand the scope of application of the device by organizing a multiple cyclic polling mode and providing direct access to computer memory.

FIG. 1 shows the structural scheme of the device; in fig. 2 is a structural diagram of the control unit of the device. i Device for inputting information contains | analog channels 1, switch 2, analog-to-digital converter (ADC)

The formation also arrives at the input 19 of the control unit 12, where it sets the trigger 25. As a result of this, at the output 15 of the device, a request is sent to the computer for direct memory access. At the same time, the end of conversion signal, using elements 27 and 30, triggers the analog-to-digital conversion on the next input.

The computer, upon receiving a request for data input in the direct access mode, reads from the device at outputs 11 from counter 10 the address of the memory cell and writes into it the result of analog-to-digital conversion, which from ADC 3 is output to

ten

3, first counter 4, first register 5, second outputs 13. After writing the result to register 6, comparison block 7, information inputs 8 of the device, second 9 and third 10 counters, address outputs 11: devices, control block 12 , information-: device outputs 13, input 14; device start-up, device 15 request for device IcTBa output, device exchange end output 16, device write end input 17, third 18, second 19 and first 20 inputs of the control unit, first 21, the fourth 22 and fifth 23 | outputs of the control unit. The control unit 12 contains the first; 24 and second 25 triggers, the AND element 26, the first 27 and second 28 OR elements, the single vibrator 29 and the delay element 30.

The device works as follows.

From the computer, the signal of the end of the recording is sent to the device input 17, which in block 12 resets the trigger 25 and thereby removes the request for direct access, and also with the help of the single-oscillator 29 generates the increment pulse of the second 9 and

third 10 counters, preparing the address

next cell in the computer memory array.

The operation is repeated until overflow.

counter 9, the signal of which is fed to

.J, .. input 18 of block 12 and resets trigger 24. As a result of resetting trigger 24, output of the device appears at the output 16 of the device.

Three modes are possible in the device: address, scanning at given edges. At the beginning, the counter is loaded 10 by-JQ, and multiple cyclic polling. The outputs 8 from the computer are the starting address of the memory array, where the measurement results are transmitted in the direct access mode. Then the computer loads; the counter 9 by the inputs 8 by the number in the mode complement is determined by the ratio between the codes loaded into registers 5 and 6 and into the second counter 9.

In the address mode, one analog-to-digital conversion is performed on the input.

There is a special code that determines the total code that is addressed by register 5, the contents of which are the number of measurements. Next, the computer issues to; device 8 inputs the code of the initial analog input, which is written to register 5, and the code of the final analog input, which is written to register 6, while the device is ready for operation.

The computer starts the measurement with a start signal, which, through the device input 14, sets the first trigger 24 of the control unit 12

at the beginning of the conversion, is rewritten into counter 4. In this mode, counter 9 is loaded with all units to specify only one conversion. Loading of channel 6 register is not necessary in this mode.

In the second mode (scanning within the specified limits) the number of transformations loaded into counter 9 corresponds to the difference of the numbers in registers 6 and 5. In this

Nor, through the element OR 28, causes recording g, - the mode performs a single scan over the selected group of analog inputs. When counter 4 reaches the upper limit set by register 6, the operation is completed, as at the same time counter 9 overflows. When loading into the register 5 the code "O, into register 6 the addresses of the last analog input and in counter 9 - A number equal to the total number of inputs scanned on all inputs. In the third mode, the local one, a single command from the computer performs multiple scans in the specified address boundaries. This mode at the beginning of the operation is performed similarly to the second mode before polling the input corresponding to the register-containing register 5 to the first counter 4. In addition, the start signal using the delay element 30 generates a conversion start signal, which is fed to the ADC 3. The delay value is determined The time required for switching the analog channel whose address is specified by the first counter 4. A digital-to-digital conversion is performed. Upon completion, its A / D converter 3 generates a conversion end signal arriving at the clock input of counter 4, increases its content by one, and thus switch 2 selects the next analog channel 1. In addition, the conversion end signal also enters input 19 control unit 12, where it sets the trigger 25. As a result of this, at the output 15 of the device, a request is sent to the computer for direct access to the memory. At the same time, the end of conversion signal, using elements 27 and 30, triggers the analog-to-digital conversion on the next input.

The computer, upon receiving a request for data input in the direct access mode, reads from the device at outputs 11 from counter 10 the address of the memory cell and writes into it the result of analog-to-digital conversion, which from ADC 3 is output to

outputs 13. After writing the result to the outputs 13. After writing the result to the memory from the computer, a signal is received at the end of the recording to the input 17 of the device, which in block 12 resets the trigger 25 and thereby removes the request for direct access, and also with the help of the one-shot 29 increment impulse second 9 and

third 10 counters, preparing the address

next cell in the computer memory array.

The operation is repeated until overflow.

counter 9, the signal of which is fed to

the input 18 of the block 12 and resets the trigger 24. As a result of resetting the trigger 24 at the output 16 of the device, the end of exchange signal appears.

Three modes are possible in the device: address, scan at specified limits, multiple cyclic polling. Mode selection is determined by the ratio between the codes loaded into registers 5 and 6 and into the second counter 9.

In the address mode, one analog-to-digital conversion is performed on the input.

addressable by register 5, the contents of which

at the beginning of the conversion, is rewritten into counter 4. In this mode, counter 9 is loaded with all units to specify only one conversion. Loading of channel 6 register is not necessary in this mode.

In the second mode (scanning within the specified limits) the number of transformations loaded into counter 9 corresponds to the difference of the numbers in registers 6 and 5. In this

6. At this point, the comparison unit 7 generates a match signal of counter 4 with register 6. After the conversion is completed on this channel, two signals are present at the inputs of AND 26, the conversion end and the match signal. Element AND 26, through element OR 28, reloads the first counter 4 with the starting address of the selected area from register 5. Thus, in this mode, the signals from the input defined by register 5 are repeatedly measured to the input specified by register 6, and then from the selected starting address, etc. until counter 9 is full. When counter 9 is loaded with a number that is a multiple of the difference between the boundary addresses, the device performs the total number of polling cycles within the specified limits.

A special case of this mode will be the mode when the same address is loaded into registers 5 and 6. In this case, the conversions are continuously carried out on the same input with the maximum speed of the A / D converter 3. This allows using this mode if it is necessary to poll any input 1 with the maximum speed.

Thus, the proposed device provides operation in several modes and uses direct data input to the computer operating memory, which allows changing the polling modes of channels on the basis of the analysis of the entered information.

In addition, it has a structure that allows you to use the maximum speed of the ADC. When using multiple cyclic polling on a computer, it is not necessary to form control commands before each polling cycle, as a result of which the overall system speed increases.

Claims (2)

1. Device for input. information containing a switch, an analog-to-digital converter and first, second and third counters, the outputs of the first counter are connected to the address inputs of the switch, the output of which is connected to the information input of the analog-digital converter, the outputs of which are information outputs of the device, the information inputs of the switch are information inputs of the first group of devices, characterized in that, in order to expand the scope of application by op0 management of the multiple cyclic polling mode and provision of direct access to the computer memory, a control unit, a comparison unit, the first and second The 5 registers, the outputs of the first register are connected to the installation inputs of the first counter, the outputs of which are connected to the inputs of the first group of the comparison unit, the output of which is connected to the first control input, the first output of which is connected to the start input of the analog-digital converter, the output of the conversion end of which is connected to the clock input of the first counter and the second input of the control unit, the second and third outputs of which are, respectively, the outputs of the exchange end and the device request, the fourth output of the control unit laziness coupled to clock inputs of the second and third counters, the second counter output is connected to -tert input control unit, a fifth output is connected to stro- biruyuschim input of the first counter, setting the second and third inputs of the counters combined with the register inputs and data inputs are second The 5 groups of the device, the outputs of the second register are connected to the inputs of the second group of the comparison unit, the outputs of the third counter are the address outputs of the device, the fourth and fifth inputs of the control unit are respectively the start inputs 0 and end recording device. 2. The device according to claim 1, wherein the control unit comprises two triggers, two OR elements, an AND element, a single vibrator and a delay element whose output is the first output of the block, the first input of the AND element is the first input of the block The second input of the AND element is combined with the S input of the second trigger, the first input of the first OR element, and is the second input of the block, the R input of the first,. The first trigger is the third input of the block, the S input of the first trigger is combined with the second input of the first OR element, the first input of the second OR element is the fourth input of the block, the R input of the second trigger is combined with the input of one or five vibrators and is the first input of the block, the inverse output of the first trigger, the direct output of the second trigger and the output of the single vibrator are respectively the second, third and fourth outputs of the block, the output of the first element OR is connected to the input of the delay element, the output of the element AND is connected to the second inputtorogo OR gate, whose output is the output of the fifth. 7U Z1 21 thirty 1b nineteen 2U 17 25 CDl / lZ w. 22 gz