SU1564649A1 - Multichannel device for registering analog and digital signals - Google Patents

Abstract

The invention relates to computing and information-measuring technology and can be used in automated systems for registering high-speed processes. The aim of the invention is to enhance the functionality, increase the speed when registering analog signals and reduce the dynamic error when registering analog and digital signals by introducing additional modes of operation and intermediate data buffering. Introduction of a buffer memory unit 14, a digital-to-analogue converter 23, comparators 25 and 26, and amplifiers 28 and 29 to the device, as well as an extension of the setting of the program operating modes of the control units 31 and 32, provide ample start-up capabilities, various sampling rates, and flexibility for expansion multichannel, conveyor mode of operation of the sampling-storage units, storing not only the measurement results, but also the results of processing them in a computer. 2 Il.

Description

The invention relates to computing and information-measuring technology and can be used in automated systems for registering high-speed processes.

The purpose of the invention is to expand the functional possibilities, increase the speed when registering analog signals and reduce the dynamic error when registering analog and digital signals by introducing additional modes of operation and intermediate data buffering.

 FIG. 1 shows a block diagram of the proposed device; Fig. 2 is a functional block diagram of the control unit.

The multichannel device has two groups of 1, 2 analog inputs, a group of 3 digital inputs, and contains (Fig. 1) the first 4 and second 5 blocks of sampling and storage, the first 6 and second 7 switches, analog-to-digital converter 8, inputs-outputs 9 data, the first 10 and second 11 transceivers, the first 12 and second 13 storage blocks, the buffer memory block 14, the digital multiplexer 15, the first 16 address counter, the element AND NOT 17, the delay element 18, the first element 19, the clock generator 20 , first 21 and second 22 triggers, digital-to-analog converter 23, register 24 sp Startup, first 25 and second comparators 26, reference voltage source 27, non-inverting amplifier 28, inverting amplifier 29, first element OR 30, first 31 and second 32 control units, first decoder 33, and also has an external clock signal input 34, output 35 interrupt signals5

0

five

0

five

0

five

0

five

nor, the output 36 of the control signal, the output 37 of the address, the input 38 of the control.

The control blocks 31 and 32 each contain (FIG. 2) register 39 programs, the first 40, the second 41 and the third 42 programmable counters, the group 43 of address keys, the second decoder 44, the first 45, the second 46, the third 47 and the quarter 48 multiplexers, the channel number counter 49, the response driver 50, the element 51, the second 52, the third 53, the fourth 54, the fifth 55, the sixth 56 and the seventh 57 elements AND, the first 58 and the second 59 groups of AND-OR elements, the second counter 60 addresses, control trigger 61, measurement trigger 62, registration trigger 63, account trigger 64, second 65 and third 66 OR elements, first 67, the second 68, the third 69, the fourth 70, the fifth 71, the sixth 72, the seventh 73 and the eighth 74 formers.

The multi-channel recording device operates as follows.

To register analog signals, the principle of automatic digital registration is used, including: process discretization in time with given sampling parameters and simultaneous fixation of the instantaneous values of electrical signals; measurement of recorded instantaneous values of signals and obtaining measurement results in binary code; memorization of measurement results in storage units.

Thus, as a result of the registration in the storage unit, an image of the process under investigation is found in the form of an array of instantaneous values of input signals captured at predetermined sampling intervals.

software registers from the computer the registration modes in each control block 31, 32. The first decoder 33, under the influence of the control signals of the machine input or output line arriving at control input 38, decrypts the address from the computer address input 37, and generates selection signals for the first or second control blocks 31, 32. The selection signal permits the operation of the second decoder 44, which, under the influence of input or output control signals, generates control signals for individual functional units depending on the values of the bits of the input 37 of the computer addresses. The response shaper 50 in the presence of a message from the computer, i.e. when the output signal of the second decoder 44 or the readiness signal of the block 12 or 13 arrives at it, it gives a response signal of the exchange with the computer at the control output 36 with a delay relative to the input or output reversal signals.

The control units 31, 32 provide two switching modes for the input measurement channels: address, when the input data of one channel with a programmable number of samples are measured; cyclic with a programmable number of channels in the Diclion and the number of discretizations of each channel, as well as three registration modes: normal, when registration is performed after the arrival of pre-start and start signals at one or two registration sections with a programmable number and sampling interval; delayed, when, after the arrival of the pre-start and start signals, the start of registration is delayed, the value of which is programmed, and then the input signal is recorded at the registration section with a programmable number and sampling interval; prelaunch, when registration starts at the moment of arrival of the pre-start signal and consists of two registration sections: prestarting and post-starting with a programmable sampling interval for two sections and the number of discretizations on the post-launching section of registration, the number of discretizations on the starting section can be any, including

five

0

measurements that can be stored in a memory bale. In this case, the oldest measurements are erased and replaced with new ones.

The type of registration mode and its parameters are stored in the program register 39 and the three programmable counters 40, 41 and 42. Information from the mode input is recorded in them. Transceivers 10 or 11 provide communication between the input-output 9 of the data from the computer to the mode input. Register write signals and programmable counters are generated by a second decoder 44

Register 39 of programs determines the following registration parameters of the sensor polling mode (address, providing measurement on a single channel, and cyclic, providing measurement on a group of channels); type of sampling of analog input signals (normal, or pipeline); the code of the channel number in the address mode or the number of channels in the cycle; registration mode, t start-up; registration mode delayed; block record in the storage unit; type of clocking (vttg Ekny or external) about

The programmable counter 40 serves to programmatically set the sampling rate and operates in a frequency divider mode.

The programmable counter 41 serves to programmatically set the delay of the start-up pulses of the analog-digital converter relative to the start signal.

The programmable counter 42 is used to programmatically set the number of sampling on one channel in the address mode to the number of sampling on each channel in cyclic mode.

After programming, the device performs the process of measuring and recording the input data.

To start work, pre-start and start signals are required to ensure synchronization of the registration process with the process under investigation. The device provides the formation not only of a start signal, performed manually by the operator or by a program from the processor, but also by an external analog signal, which is used as

five

0

five

0

five

one of the input measured signals. An external analog signal is triggered when the software-set trigger level crosses the analog signal at a positive and / or negative slope of the input signal.

A digital-to-analog converter receiving information from data input 9, using a recording signal produced by the first decoder 33, outputs an analog signal to the input of comparators 25, 26, the value of which is programmed from the maximum positive to the maximum negative value depending on the input code. The input code is determined by the desired trigger level and trigger method. The first comparator 25 is fed through the input signal through a non-inverting amplifier 28, and to the second 26 through an inverting amplifier 29.

In case of equality of the input analog signal and the programmed start level from the output of converter 23, one of the comparators 25, 26 generates an output signal arriving at the input of the first OR 30 circuit, which also receives a digital start signal programmed in the start method register 24. The comparators 25, 26 are controlled by two signals determining the method for triggering the registration on the analog signal. The triggering method is programmed in the triggering mode register 24, into which information is recorded from the data input 9 via a computer according to the recording signal of the first decoder 33.

The formation of the start signal from the analog signal is performed at the time of the analog signal crossing the trigger level in the direction of increase, when the signal slope is positive, or falls, when the signal slope is negative.

The imaging unit 73 receives the signal from the output of the register 24 of the triggering method, and the imaging unit 71 receives the signal from the output of the first circuit 30 OR in the presence of a prestress signal. The counting trigger 64 generates a counting signal upon the arrival of the first clock pulse of the 20 clock pulse generator in the presence of a start signal from the output of the driver 71. Upon the arrival of the next clock pulse after the trigger 64 has been set, the generation of the pre-start and start signals is terminated.

Consider the different modes of per gistration.

In the delayed registration mode, the register output 39 of the program is set: single sign signal Delayed mode and zero sign signal Pre-start mode, which is fed to the inputs of the eighth driver 74. In the delayed counting signal from the trigger output

5 64 counts pass immediately through shaper 74 to shaper 68 input, which generates by it the enable signal of the first channel of programmable counter 40. Then, the ID1 sampling rate is programmed from the mode input and it operates in the frequency divider mode.

The clock input receives clock pulses from the output of the second group of elements AND-OR 59. It passes either internal clock pulses from the generator of 20 clock pulses or external clock pulses through

0 to the external clocking input 34 depending on the clocking type programmed in the register of 39 programs. External clocking is used to link the sampling times of analog signals or store digital signals to an external reference signal. At the output of the programmable frequency counter 40, sampling pulses are received.

d ID1, following with a frequency equal to the frequency of the clock pulses divided by the programmed division factor.

5 In the delayed registration mode, the shaper 69 allows the passage of ID1 sampling pulses to the output of the first group of AND-OR 58 elements and to the input of the programmable counter 41 as clock pulses. In the programmable counter 41 from the mode input, the start delay of measurements of the converter 8 in the first control block 31 and the counting of the counter of the intermediate memory address 16 in the second control block 32 with respect to the start signal. The work signal enable signal of this programmable counter is supplied

five

0

five

from the output of the former 72, after triggering the trigger 64 of the account upon the arrival of the next clock pulse of the generator 20 clock pulses.

After the number of sampling pulses, which determine the programmed delay interval, arrives at the input of the programmable counter 41, a pulse of the end of the delay occurs at the output of the programmable counter 41 and passes through the driver 74 to the input of the registration trigger 63, setting it to one. the signal at the output of the imaging unit 69 and resetting the trigger 64 of the count, which removes the enable signal of the programmable counter 41.

In addition, the output signal of the driver 69 is fed to the input of the programmable counter 42, allowing it to work. As clock pulses, the output sampling pulses of ID1 of a programmable frequency counter 40 are used. After the programmed number of sampling has been completed, a program end signal appears at the output of the programmable counter 42, which enters the registration trigger 63, completes the formation of the registration signal, and the programmable counter work enable signal 42 is removed. When a program end signal appears, the driver 68 stops the programmable operation the estimator 40 and the output of the ID1 sampling pulses is stopped. The sampling pulses ID1 pass through the first group of elements 58 AND-OR and then the second element 65 OR, forming the trigger signals of the converter 8 for the first control block 31 or the counter 16 of the buffer memory block address for the second control block 32

one

In delayed registration mode

after the passage of the start and release signals, the start of the registration is delayed, and after it is completed, the registration with the programmed number of samplings and the sampling frequency is performed. The sampling pulses generated in the delay interval do not cause sampling of the input signal, but are used to form a certain length of the delay section. Subsequent pulses

sampling cause the input signal to decrease.

In the normal registration mode, it is possible to work with different sampling rates on two sampling sites. In that case, in programmed counter 41, the number of discretizations is Qy with the first speed, in programmed counter 42, the total number of discretizations, the sampling interval of ID1 in the first channel of the programmable counter 40, and the sampling interval of ID2 in the second channel. The difference in the operation in this mode from the previous (delayed) one is as follows.

The registration trigger 63 in this Q case is set by uo; r.e setting the trigger 64 of the account upon the arrival of the next clock pulse of the generator 20 clock pulses. When the signal from the output of the trigger 5 64 is detected, the operation of the first channel of the programmable frequency counter 40 is enabled, from the output of which the sampling pulses appear. After completed for: the programmed number of measurements with the ID speed, the output signal of the programmable counter 41 through shaper 74 and 69 resets the trigger 64 of the account and through the shaper 74 and 68 blocks the operation of the first channel of the programmable counter 40, and through the shaper 69 permits operation of the second channel. At the output, discretization pulses ID2 appear, i.e. Q is the switching of the sampling rate.

When programming the first and second channels of the programmable counter 40, the sampling pulses during the entire sampling period, determined by the single state of the registration trigger 63, will proceed uniformly with the same speed.

Q In the pre-registration mode, the programmable counter 41 is not used. The installation of the registration trigger 63 occurs on a pre-start signal, which, if there is a sign, the pre-start mode from the output of the program register 39 passes through the driver 74 to the installation input. In a programmable counter 42, the number of discretes is programmed.

post-launch operations. The enable of this programmable counter is set by the output signal of the trigger 64 of the account, the resolution of the first channel of the programmable counter 40, where the sampling interval is programmed before the start, is performed by the pre-start signal. If the sampling frequency needs to be changed after start-up, the second channel of the programmable counter 40 is used to program it. The operation of this channel is enabled by the output signal of the account trigger 64 passing through the drivers 74 and 68.

Consider two switching modes of input measuring signals: cyclic and address. Under the influence of sampling pulses passing through the first input of the second element OR 65, the converter 8 is started, which, after the end of the conversion, gives a ready signal. This signal is fed to the first input of the imager 70, at the output of which a recording signal is generated in block 12, triggered by the readiness response signal of block 12. The output signal of this imager is fed to the recording input of the measurement trigger 62. The input of the installation of this trigger receives an ID1 discretization pulse and sets it to a single state. The information input of this trigger is received by the signal of the feature Cyclic mode from the output of the register of 39 programs. In the address mode, this signal is zero and the write signal to block 12, with its falling edge, returns the measurement trigger 62 to the initial zero state. To start the converter 8, the second input of the OR circuit 65 also passes the write pulses to the block 12. From the output of the former 70, they pass to the input of the former 67, where they are delayed and gated by the output signal of the measurement trigger 62. In the address mode, the signal of the Cyclic mode is equal to zero, and the recording signal in block 12, which enters the recording input of this trigger. returns it to the zero state. Therefore, the delayed recording signals in block 12 do not pass to the output of the driver 67 and in the address mode

five

0 5 0 5 0 5 Q

five

Converter 8 is triggered only by sampling pulses on the first input of the second circuit OR 65.

When operating in the address mode, for each sampling pulse, one start pulse of converter 8 is formed, according to which the measurement is performed. The formation of the following start-up pulses in an amount equal to a given number of discretizations is performed with the period programmed in the programmable counter 40.

The output signal of the trigger 62 of measurement is supplied in the first control block 31 to the read input of the converter 8, so that its output information can be recorded in the first block 12.

The channel number in the address mode is programmed in the program register 39 by four bits. These signals are sent to the information inputs of the counter 48 channel numbers. Sampling pulses are sent to one input of element 54, and the second input is a sign of the addressing mode, which is the inversion of the signal from the output of element 51. In the addressing mode, sampling pulses go to output of the element 54 and the record entry of the channel number 48 and the channel number is written into it by parallel writing. From the outputs of the channel number 48 counter, the channel number in the form of a code is fed to the inputs of the switches 6 and 7 for the first control block 31 or the address inputs of the buffer memory block 14 of the second control block 32.

In cyclic mode, the channel digits of the register register 39 are used to program the number of channels in a loop. The passage of the sampling signal to the input of the recording of the channel number 48 counter is blocked by the And 54 element, and parallel recording is not performed. According to the sampling signal, the initial installation of the counter 48 of the channel number is made by the reset input by the output signal of the circuit 53. Then, in cyclic mode, the recording signals from the output of the element And 52 arrive at the counting input of the counter 48 of the channel number, increasing its address by one. From the outputs of this counter, the address code is fed to the inputs of multiplexer 46, which is allowed to operate only in cyclic mode. Depending on the programmed number of channels in the loop at the output of multiplexer 46, the signal is hung after the signal of the last channel number in the loop appears.

The output signal of this multiplexer resets the measurement trigger 62. Unlike the address mode, the information input of this trigger is a single signal, so after setting the trigger on the setup input by the sampling signal to the single state, the recording signal arriving at the recording input leaves it in this state ; the trigger is reset only by the reset input; A single output signal of the trigger 62 of measurement passes to start up the converter 8 through the shaper 67 all the signals from the shaper 70 output.

When operating in a cyclic mode, switching for each sampling pulse generates a measurement pulse Mk, where NK is the number of channels in the cycle, with a period equal to the measurement duration. In the process of registration in cyclic mode, the number of sampling set in the programmable counter 42 will be performed for each channel.

To increase the speed when registering analog input signals, it is possible to use conveyor sampling of blocks 4, 5.

All analog inputs are divided into two groups.

The first and second groups 1 and 2 of the analog inputs contain eight channels each. The fixation of the instantaneous values is performed by the sampling-storage units installed at the input of each channel. The two multi-channel blocks 4 and 5 are multi-channel devices, each of which consists of eight sampling-storage schemes, and are controlled by separate storage enable signals; when blocks of these signals are input to the input, the instantaneous value of the measured signal is stored by the corresponding blocks 4, 5. Two switches 6 and 7 with combined outputs connect the analog signals recorded in blocks 4, 5 to the input of the converter 8, switching channels in both switches a three-digit channel number code generated by the channel number counter 48, and the resolution of each switch is made by the corresponding control signals. When operating with a sample of 16, the measured input signals are connected to the input of each of the eight channels of blocks 4 and 5. The control signals of the switches are generated by the control trigger 61, and the storage resolutions by the multiplexer 47.

The control inputs of the multiplexer 45 receive the cyclic mode and the sampling of the conveyor from the outputs of register 39 of the programs to the information inputs-outputs of the channel number of the register 39 of programs and signals from the power buses in such a way that, if the cyclic mode is programmed and the sampling is normal, the first output of the multiplexer 45 a zero signal is set, and on the second, a single signal, but only if the number of channels in the cycle does not exceed eight. The output signals of the implexer 45 are fed to the inputs K and I of control trigger 61, on the outputs of which, when a record of sampling pulses arrives at the record, a single signal is set at the first output and zero at the second, i.e. First switch 6 is selected.

If the number of channels in cycle 16, then the first switch 6 operates from the zero to the eighth channel, when switching to the eighth channel, the control trigger 61 is reset to its original state, i.e. The second switch 7 is selected. Multiplexer 47 is controlled by a signal from the second output of register 39, and if the sample is normal, both measurements 4 trigger 61 pass to both outputs of multiplexer 47 and, under the influence of equal storage signals, both units 4, 5 operate synchronously. After transferring both blocks 4, 5 to the storage mode, the input signals are measured in series across all channels switched by switches 6, 7 during 16 conversion cycles. After performing measurements on all channels, both blocks 4, 5 are switched to the sampling mode by sending both storage signals equal to a logical O.

With a conveyor sample, two groups of analog inputs 1, 2 are combined, each sensor is connected to the inputs of two blocks 4, 5, and the number of input measuring channels is reduced by two times to eight. . On both outputs of the multiplexer 45, single signals are set and the control trigger 61 starts to operate in the counting mode, the signals on its outputs are in opposition, i.e. switches 6, 7 are alternately selected. On both outputs of the multiplexer 47, the output signals of the control trigger 61 and the storage signals change according to: the trigger and 61 signals are located; TC also in antiphase. In the mode: wound is one of the blocks

or 5, included at the input of the selected switch, the other is in the sampling mode.

At the moment of fixing the values of the input signals, one of the sample-storage blocks goes into the storage mode, and the other into the sampling mode. The outputs of the unit in storage mode are sequentially polled by the appropriate switch and measured by the converter 8 to a temperature of eight conversion cycles. After the measurements are completed, the following values of the input signals can be fixed via the same channels, i.e. the sampling time of the storage-storage blocks is excluded from the time interval for measuring the input signal.

If the working mode is programmed to address and the sample is normal, a zero signal is set at iiepBOM output of multiplexer 45 and a single signal at mercury. If the number of the selected channel is less than eight, the first switch 6 works, if the no-Ner channel is greater than eight, the second switch 7 works, Multiplexer 47, as in the cyclic mode with normal sampling, passes measurement signals 62 to the Codes, Both blocks 4 and 5 work synchronously. If the addressing mode and sampling of the conveyor are programmed, then the operation is similar to the cyclic mode with conveyor sampling.

The system provides enhanced use of storage blocks.

The recording signals to the recording input of blocks 12 or 13 are passed from the output

five

0

five

0

five

0

five

0

five

OR 66, enabling the storage unit not only of the measurement results of the converter 8 in the first control block 31 or data of the buffer memory block 14 in the second control block 32, but also the ability to read and write data stored in the computer memory, for example of measurement processing results. In this case, the recording signal from the computer arrives at the second input of the element OR 66. At the same time, the corresponding control signals are output to the transceivers 10 or 11 from the output of the second decoder 44 and the inverse output - trigger 62 measurements In the absence of a measurement process, the system allows data transmission from the input 9 of computer data to the input of blocks 12 or 13. Accordingly, it is possible to output the address of blocks 12 or 13 either from the address counter 60 or directly from the input 37 of the computer addresses using multiplexer 48.

When recording the measurement results, the signal from the output of the imaging unit 70 is supplied to the counting input of the counter 60 of the address. In the initial zero state, the address counter 60 is set by a pre-start signal from the output of the And 57 element, where it is gated with a block record signal from the output of the program register 39, which prohibits a reset. The output code of the address counter 60 is fed to the inputs of the multiplexer 48, and from its output to the address inputs of blocks 12 or 13. The other inputs receive the address directly from the input 37 of the computer addresses. The transmission direction of the multiplexer 48 is controlled by the output control signal of the second decoder 44.

The number of measurements in the address or cyclic modes is programmed and may be less than the total volume of the storage unit. It is envisaged that the remaining free part of the memory can be used to store the results of the next measurement series or, as indicated, computer data, such as processing results. To do this, the Block Record mode is recorded in the program register 39, which prohibits the reset of the counter 60 of the address on the pre-start signal of the next measurement series, and they are recorded

in the remaining free part of the memory. If data of the computer is recorded, the address from the output of the counter 60 of the address can be read by the computer and recorded from the initial address of the free memory zone. The address from the output of the counter 60 of the address is fed to the input of the group of valve 43 of the address and is removed from their output if there is a control signal from the output of the second decoder 44 passing through the element 55, where it is gated by the signal of no measurements from the inverse output of the measurement 62.

After recording the measured input analog or digital information, it is read in a program exchange with a computer. In addition, it provides for work in the interrupt mode - at the initiative of the device itself with the issuance of a signal to the computer at the output of 35 interrupts.

There are three types of interrupts: interrupt at the end of each measurement (the interrupt signal is the readiness of the converter 8 in the first control block 31 or the counter 16 of the buffer memory block in the second control block 32, used in address and cyclic modes); interrupt at the end of the switching cycle on the selected group of channels (the interrupt signal is the output of the measurement trigger 62, used in a cyclic mode); interrupt at the end of the programmed sampling number (the interrupt signal is the end of program signal, used in address and cyclic modes).

The read signal of the storage unit is a control signal from the output of the second decoder 44, passing through the element 56, where it is gated with a signal of no measurements from the inverse output of the measurement trigger 62. From the output of the element And 56, this signal is fed to the read input of block 12 or 13.

The device provides registration in the storage blocks of both analog and digital input signals from the same control blocks 31, 32. A control block 32 is used to register input digital signals, similar to block 31 (FIG. 2).

0

five

The third group of inputs of the device 3 is designed to register digital input signals. The device provides a reduction in the dynamic error during the transmission of digital input signals by using an intermediate memory.

When the trigger signal is received from the control unit 32, a single voltage level is established at the output of the recording of the second flip-flop 22. On the leading edge of the pulse from the output of the generator 20 clock pulses, whose frequency exceeds the measurement frequency, a single voltage level is set at the output of the first trigger 21, thereby allowing the reset pulse to pass through the first element 19 to the counter 16 of the buffer memory block. At the same time, the second trigger 22 is reset.

On the leading edge of each subsequent clock pulse, the first trigger 21 is reset, and the clock pulses through the AND-NE 17 circuit affect the counting input of the counter 16

0 addresses of the buffer memory block and through the delay element 18 to the input of the record of the buffer memory block 14. At the same time, the output of the counter 16 of the address of the block of the buffer memory is set to the cell address of the block 14 of the buffer memory and controlled by the digital multiplexer 15. Thus, in a time equal to

NK (tMn - tinn),

0 where N is the number of channels;

t is the delay time in the multiplexer; V C n is the write time to the intermediate memory,

5, a digital signal is recorded at the clock frequency in the intermediate memory of the block 14. At the end of the recording, a readiness signal is output, which is sensed by the control block 0 32.

On the readiness signal, control unit 32 transmits the contents of buffer storage unit 14 Ј unit 13 and outputs the next trigger signal 5.

Dynamic uncertainty is the dating error associated with insufficient time.

Melena binding of the beginning of the registration of several digital input signals to a single point in time.

The dating error when retrieving digital signals is determined by the formula

where tjn is the write time in nan.

A reduction in the error of dating is achieved by reducing the time, since the buffer memory can be built on high-speed memory integrated circuits that have a significantly higher speed than a conventional storage unit, the main requirement of which is a large amount of memory. Therefore, t, nn "t, n.

Claims (1)

Claim 1 A multichannel device for registering analog and digital signals, which contains two sampling-storage units, two switches, an analog-digital converter, two storage units, a clock generator, an orbital element OR, a first decrypt-frop, a first address counter, the first element I, two control units, each of which contains a program register, a second decoder, a channel's Yomer counter, a second address counter, the second and third AND elements, a second and third OR elements, and an NO element, the first analog input of the device connected the information input of the first sampling-storage unit Yi, the second analog input of the device is connected to the information input of the second sampling storage unit, the output of the first sampling storage unit is connected to the information input of the first switch, the output of the second sampling storage unit is connected to the information input of the second switch whose output is connected to the output of the first switch and to the information input of the analog-digital converter, the inputs of the address of the first and second switches are connected to the first address output ohm the first control unit, the address input of the device is connected to the address inputs of the first and second control blocks and the address input of the first decoder, the control input of the device is connected to the same inputs of the first and second control units and the first decoder, the external clock signal of the device is connected to the first clock the inputs of the first and second control units; the output of the interrupt signals of the device is connected to the same outputs of the first and second control units, with each control unit and the address input in the control unit is connected to the address input of the second decoder, the control input of which is connected to the control input of the corresponding control unit, the enable input of the second decoder of the first control unit is connected to the first output of the first decoder, the second output of which is connected to the resolution input of the second decoder of the second control unit , the first output of the program register is connected to the information input of the counter channel number, the output of which is connected to the first address output of the corresponding A control unit, characterized in that, in order to expand the functionality, increase the speed when registering analog signals and reduce the dynamic error when registering analog and digital signals by introducing additional operating modes and intermediate data buffering, two transceivers, a digital multiplexer, are introduced into it, first and second triggers, buffer memory block, inverting amplifier, reference voltage source, digital-to-analog converter, mode register trigger, the first and second comparators, the NAND element delay element, and in each of the control blocks entered THREE programmable counters, four multiplexers, control trigger, measurement trigger, registration trigger, count trigger, fourth, Fifth, sixth and seventh elements , two groups of AND-OR elements, a response driver, a group of address keys and eight drivers, the first group of inputs-outputs of the first transceiver connected to information inputs-outputs of the first storage unit and information output E analog-to-digital converter, a first group of inputs of the second outputs transceiver is connected to the information inputs-outputs of the second storage block and the outputs of the buffer memory block, the information inputs of which are connected to the outputs of the digital multiplexer, the control inputs of which are connected to the address inputs of the buffer memory block and the data outputs of the first address counter, the overflow output of which connected to the first input of the NAND element and the first input of the signs of the second control unit, the second inputs-outputs of the first and second transceivers are connected to the information the digital address converter, the start method register and the device data input / output data paths, the first address output of the second control unit is connected to the address input of the buffer memory block, the device’s digital information input is connected to the information input of the digital multiplexer, the second address outputs of the first and second control units are connected to the corresponding address inputs of the first and second storage units, the first and second control outputs of the first control unit are connected to the control inputs neither the first and the second sampling-storage unit, respectively, the third and fourth control outputs of the first control unit are connected to the control inputs of the first and second switches, respectively, the fifth control output of the first control unit is connected to the start input of the analog-digital converter, the fifth control the output of the second control unit is connected to the write input of the first trigger, the sixth control output of the first control unit is connected to the read input of the analog-digital converter, the sixth control The second output of the control unit is connected to the readout input of the buffer memory unit, the seventh and eighth control outputs of the first and second control blocks are connected to the control inputs of the first and second transceivers, respectively, the ninth and tenth control outputs of the first and second blocks controls are connected to the write and read inputs of the first and second memory blocks, respectively; the eleventh control outputs of the first 15 20 five Jq and the second control units are connected via INSTALLING OR and connected to the control output of the device, the first input of the first control unit is connected to the ready output of the analog-digital converter, the second inputs of the first and second control units are connected to the ready output of the first and second storage units, respectively , the inputs of the modes of the first and second control units are connected to the first groups of inputs and outputs of the first and second transceivers, respectively, the output of cycles generator is connected to the second clock inputs of the first and second control units, the second input of the NAND element, the first input of the first element I and the recording input of the second trigger, whose information input is connected to the direct output of the first trigger, the reset input of which is connected to the inverse output of the second trigger, the direct output of which is connected to the second input of the first element I, the output of which is connected to the reset input of the first address counter, the counting input of which is connected to the output of the NAND element and the input of the delay element and whose output is connected to the write input of the buffer memory block, the third and fourth outputs of the first decoder are connected to the write inputs of the digital-to-analog converter and the starting method register, respectively, the first output of which is connected to the first input of the first comparator, the output of which is connected to the first input of the first OR element , the second input of which is connected to the output of the second comparator, the first input of which is connected to the second output of the starting register, the third output of which is connected to the third input of the first the OR element, the output of which is connected to the third inputs of the first and second Q blocks of the control, the fourth inputs of the attributes of which are connected to the fourth output of the starting method register, the second inputs of the first and second comparators are connected to the output of the reference voltage source and the input of the reference level of the digital-analog converter, analog the output of which is connected to the third inputs of the first and second comparators, four five 0 five five The first input of the first comparator is connected to the input of the inverting amplifier and one of the channels of the first analog input of the device, the fourth $ of the second comparator is connected by the output of the inverting amplifier, in the control unit each mode input is connected to the information input of the program register, the information inputs of three programmable counters and outputs group of address keys, the first output of the program register is connected to the first control inputs of the first and second multiplexers, the information input of the second multiplex The second output of the program register is connected to the second control input of the first switch and the first control input of the third switch, the second and third inputs of which are connected to the direct and inverse outputs of the control trigger and the third and fourth control outputs of the unit. control, respectively, the first and second control outputs of the control unit are connected to the first and second outputs of the third duplexer, the fourth input of which is connected to the direct output of the measurement trigger, the first inputs of the first and second drivers, the control output and the first IJI3 outputs of the interferences signal of the etching unit; the second of the outputs of the interferences of the control unit are connected to the output of the third programmable counter, the second input of the third generator, and the information input of the trigger trigger , The third output of the program register is connected to the third control input of the first multiplexer, the second control input of the second multiplexer, the first input of the second element and M, the input element is NOT, the information input of the measurement trigger and the first input of the third element I, the second input of which is connected to the input of the measurement trigger installation, the input of the recording control trigger, the first inputs of the fourth element AND and the second element OR, and the first output of the First group of elements AND- OR, the second input of the second element OR is connected to the output of the first driver, the second input of which is connected to five 0 five output of the fourth driver, the second output of which is connected to the first input of the third element OR, the second input of the second element AND, the recording entry of the measurement trigger and the counting input of the second address counter, the output of which is connected to the first information input of the group address keys, input control of which is connected to the output of the fifth element I, the first input of which is connected to the inverse output of the measurement trigger, the recording entry of the registration trigger, the first input of the sixth ele And the eighth control output of the control unit, the ninth control output of which is connected to the output of the third OR element, the second input of which is connected to the second output of the second decoder, the third, fourth and fifth outputs of which are connected to the recording inputs of the first, second and third programmable counters, respectively, the sixth and seventh outputs of the second decoder are connected to the second inputs of the fifth and sixth elements And, respectively, the eighth output of the second decoder is connected to the control input of the fourth mule of a typelexer whose output is connected to the second address output of the control unit, the seventh control output of which is connected to the ninth output of the second decoder, whose address input is connected to the second information input of the fourth multiplexer, the second output of the second decoder is connected to the first input of the response shaper whose output is the eleventh control output of the control unit, the first feature input of which is connected to the first input of the fourth driver and is the third of the outputs of the signals n breaking the control unit, the second sign input of which is connected to the second inputs of the response shaper and the fourth shaper, the output of the first shaper is connected to the second input of the second OR element, the output of which is connected to the fifth control output of the control block, the third sign input of which is connected to the first input p the former, the second input of which is connected to the first inputs of the sixth, 0 five five 0 five the seventh and eighth drivers and the output of the account trigger, the recording input of which is connected to the third input of the fifth driver, the first inputs of the AND-OR elements of the second group, the second input of the seventh driver and the second clock input of the control unit, the ten control output of which is connected to the output of the sixth element I, the fourth sign input in each control unit is connected to the third input of the seventh shaper, the first input of the seventh And element, and the second input of the eighth shaper, the third input of which is connected to the fourth output of the program register, the fifth output of which is connected to the fourth input of the eighth shaper, the fifth input of which is connected to the output of the second programmable counter, the control input of which is connected to the sixth input of the eighth shaper, and the second input of which is connected to the first and second synchronous inputs the first programmable counter and the output of the I-IL elements of the second group, the second inputs of which are connected to the first clock input of the control unit, and the third inputs - to the sixth output of the re istra programs, a seventh output is connected to the second input of the seventh AND gate, whose output is connected to the input for setting the second address counter, the first output of the first programmable counter is coupled to first inputs of AND-OR of the first group, 0 five 0 five 0 five the installation input of which is connected to the first output of the eighth shaper, the second output of which is connected to the third input of the second shaper, the output of which is connected to the first control input of the first programmable counter, the second output of which is connected to the third inputs of the AND-OR elements of the first group, the second output of which is connected to synchronous inputs of the second and third programmable counters, the control input of the third programmable counter is connected to the first output of the third generator, the second output of which is connected with the reset input of the account trigger, the information input of which is connected to the output of the fifth shaper, the fourth input of which is connected to the output of the seventh shaper, the third output of the third shaper is connected to the fourth input of the AND-OR elements of the first group and the second control input of the first programmable counter, the third input The third driver is connected to the third output of the eighth driver, the output of the second multiplexer is connected to the reset input of the measurement trigger, the output of the element is NOT connected to the second input m of the fourth element I, the output of which is connected to the input of the record of the channel number counter, the counting input of which is connected to the output of the second element I, and the reset input - with the output of the third element, And, the first and second outputs of the first multiplexer are connected to the input the second inputs of which are connected to the second blocks K and I, respectively, by the trigger input of the third driver and control, the forward output of the registration trigger,