SU1168973A1 - Device for presenting delaying functions - Google Patents

Abstract

DEVICE FOR REPRODUCING retarded function comprising follower analog-to-digital converter, an information input of which is an input device, and a clock input connected to the output of the clock, the output of a digital to analog converter and a first flip-flop coupled to the first and second mounting inputs to the first and second buses setting the device operation modes respectively, and the output with the zeroing inputs of the first and second counters and the first installation input of the second trigger a connected by an output to the first input of an element I connected by an output to a counting input of a second counter connected by a code output to a first information input of a multiplexer connected by a second information input to a code output of the first counter and to the first input of a code comparison unit, and an output to the address input of a block RAM connected to the write enable input to the pulse driver output, the second input of the code comparison unit connected to the bus for setting the delay time code device Twa, characterized in that, in order GPRS ustroyst spinning. by reducing the information capacity of the RAM block, the device contains a demultiplexer, a NOT element and a third counter connected by an output to the input of the output digital-to-analog converter, a setting input to the output of a parallel conversion result code of the following analog-digital converter, control input (L setting the code to the output of the first trigger, and summing and subtracting inputs to the first and second outputs of the demultiplexer, respectively, connected by an information input to the output of the element I, and the control input with the output of the operative memory unit OD connected by the information input 00 to the output of the sign of the unit increment of the next analog-digital Nj converter, the output of the clock generator connected to the input of the pulse driver, the synchronizing input of the first the trigger, the counting input of the first counter, the control of the multiplexer and the input of the element NOT, the output of which is connected to the second input of the AND element, and the output of the code comparison block is connected to the second second input of the second trigger.

Description

The invention relates to automation and computing and can be used, in particular, in hybrid computing devices and systems when playing back functions with adjustable latency times. The purpose of the invention is to simplify the device by reducing the information capacity of the RAM unit. The drawing shows a block diagram of an apparatus for reproducing late functions. The device contains an analog-to-digital converter 1 (of the counting type), the first 2 and second 3 triggers, the shaper 4 pulses, the RAM block 5, the multiplexer 6, element 7, the generator 8, clock pulses, the code comparison block 9, the output - digital analog converter 10, input 11 of the device, first 12 and second 13 buses of the task of operating modes, bus 14 specifying the delay time code, first 15 and second 16 counters, demultiplexer 17, element. HE 18 and the third counter 19 .. The shaper of 4 pulses is performed on the delay element and the element AND whose output is connected to the output of the shaper, the first input is connected to the output of the delay element, and the second input is connected to the input of the shaper and the input of the delay element. The demultiplexer 1 7 contains the element NOT and two AND elements connected by the first inputs to the information input of the demultiplex, and the outputs respectively to the first and second outputs of the demultiplexer, and the second input of the first element I is connected through the element NOT to the control input of the demultiplexer and the second input of the second element I. The device operates in two modes: Preparation (trigger 2 is reset with a pulse. Stop from the device bus 13) and Playback (trigger 2 is set to one, pulse Start from the device bus 1 ). In addition, switching of the trigger 2 to the corresponding state occurs through a cut of the output pulse of the generator 8 arriving at the synchronizing input of the trigger 2, In the Prepare mode, the zero signal, the zero zero trigger output 2 enters the trigger 3 and counters 15 and 16, and also to the control input of the installation of the counter code 19, allowing the output parallel output code of the conversion of the analog-digital converter 1 to the counter 19 to be written. The output code of the counter 19 is converted by the converter 10 into an analog signal received conductive to the output device. In this case, the signal at the output of the device with an accuracy of one of the lowest bit of the transducers 1 and 10 is equal to the analog signal at the input 11 of the device. In playback mode, the signal. bus 12 sets trigger 2 to one state. A single signal from the output of trigger 2 prohibits the writing mode of the code of the analog-digital converter 1 to the counter 19. Thus, the last code from the sequence of parallel codes recorded in the counter 19 is the initial condition code that comes from the output of the counter 19 to the input of the converter 10 which forms the voltage of the initial condition. On the front of each output pulse of the generator 8, an increment sign signal is formed at the corresponding output of the analog-digital converter 1 (in the case of a positive increment of the driver, a single signal and in the case of a negative increment a zero signal). The counter 15 on the front of the pulse generator 8 sets the next address of the recording cell, which arrives at the address input of the RAM 6 through the multiplexer 6. When a delayed single signal arrives from the output of the imaging unit 4, a write cycle occurs in the cell of the RAM 5. This recording cycle is repeated periodically with the arrival of subsequent clock pulses. The reading of information from block 5 also takes place sequentially, starting with the first memory location, but with a delay of the number of ticks, determined by the digital code arriving on the bus 1 4 of the device. When the codes on the inputs of the comparison unit 9 are equal, a comparison pulse is generated at its output.

over the slice of which the trigger 3 is set to one. The output signal of the trigger 3 unlocks the AND 7 element, allowing the inverted clock pulses to pass to the counting input of counter 16. With the simultaneous arrival of the counter code 16 to the address input of memory block 5 and the zero signal from the output of driver 4 to the write enable input of block 5 (zero signal corresponds to read mode) a read cycle occurs. The read data from the output of block 5 is fed to the control input of the demultiplexer 17, in which the formation of an increment pulse occurs. The zero signal from the output of block 5 corresponds to the difference in the passage of the output pulse of the element And 7 to the subtracting input of counter 19, respectively, the unit output signal of block 5 allows the pulse to enter the summing input of counter 19.

Thus, with a delay of the corresponding number of clocks at the output of the counter 19, the reproduction begins.

the sequence of codes for the results of analog-digital conversion of the input signal of the device

 , 4-2 P,

1 1 where NMIJ is the initial condition code;

P - the increment of the function P with -1, +

1 - time point.

Claims (1)

DEVICE FOR PLAYING BACK LATER FUNCTIONS, containing a tracking analog-to-digital converter, the information input of which is the input of the device, and the synchronizing input is connected to the output of the clock generator, the output digital-to-analog converter and the first trigger connected by the first and second installation inputs to the first and second bus settings the operation of the device, respectively, and the output with the inputs of zeroing the first and second counters and the first installation input of the second trigger, connect output to the first input of the AND element, connected by the output to the counting input of the second counter, connected by a code output to the first information input of the multiplexer, connected by the second information input to the code output of the first counter and to the first input of the code comparison unit, and by the output with the address input of the RAM block connected by the recording permission input to the output of the pulse shaper, the second input of the code comparison unit being connected to the bus for setting the device delay code, the fact that, in order to simplify the device by reducing the information capacity of the RAM block, the device contains a demultiplexer, a NOT element and a third counter connected by an output to the input of the output digital-to-analog converter, and a setting input to the output of the parallel code of the result of the conversion of the tracking analog a digital converter, the code setting control input - to the output of the first trigger, and summing and subtracting inputs - to the first and second outputs of the demultiplexer, respectively, the information input with the output of the AND element, and the control input with the output of the RAM block connected by the information input to the output of the unit increment sign of the tracking analog-to-digital converter, the output of the clock generator connected to the input of the pulse shaper synchronizing the input of the first trigger, the counting input the first counter, which controls the input of the multiplexer and the input of the element NOT, the output of which is connected to the second input of the AND element, and the output of the code comparison unit is connected to torym adjusting input of the second flip-flop.