RU2218596C2 - Data acquisition device - Google Patents

Abstract

FIELD: data processing and measurement technology. SUBSTANCE: device that can be used as part of on-board analog and digital data conversion systems, computer-based control systems of flying vehicles, and also as part of ground-based computerized monitoring systems has data input unit, double-entry random-access memory, buffer, addressing unit, control unit, address register, code comparison unit, and record shaping unit. EFFECT: reduced time for software servicing of device. 4 cl, 4 dwg

Description

 The invention relates to information-measuring equipment and can find application in on-board systems for converting analog and discrete information, automated control systems for aircraft, as well as in ground-based automated control systems.

 A very important parameter of the data acquisition device is speed, especially with a large number of controlled objects. The required speed can obviously be achieved by using devices with a higher conversion speed. Given the increased requirements to reduce energy consumption and cost, it is more preferable to search for improved work algorithms. Along with this task, there is another, when a high-speed device for inputting analog information overloads the central processor. In this case, the analog input device is advisable to supplement the RAM, as is done in the data acquisition device [1].

 The specified device contains an analog information input and conversion unit (BVPAI), including N conversion paths, a storage device (memory), a control computer (HC), a synchronization unit, consisting of an external synchronization signal switcher, long and short pulse shapers, a reference source frequency, counter, two AND elements, OR element, control unit containing a frequency divider, four triggers, timer, OR element, element I. Analog signals are sent to N groups of information inputs block BVPAI. The cycle of measuring analog signals begins with setting to zero N conversion paths of the specified block. For this, the control unit generates a strobe, which is fed to the reset input of the BVPAI unit. At the end of the reset gate of the N conversion paths, n signals are simultaneously accumulated over a time equal to or a multiple of an integer number of voltage periods of the wiring network. For this, the control unit generates an accumulation strobe, which is fed to the input of the permission of the BVPAI block. At the end of the accumulation gate, N conversion paths go into the storage mode of analog signals for n conversions of the accumulated information into a digital code. Digital codes of analog signals are recorded in the memory unit of the BVPAI. After that, the interrupt trigger of the control unit generates an interrupt request signal (ZPR), which arrives at the specified block. The latter generates an interrupt grant signal (PNR) to the signal ZPR. This signal removes the interrupt request, and the control unit generates the next reset strobe. From this moment, information is exchanged between the memory and the hydrocarbon, and for the conversion paths, the next measurement cycle. The described data acquisition device has a limited speed, because interrupt data entry has a limited data transfer rate even provided that only data transfer is performed without checking conditions or converting the data format. Performing any such operation can significantly reduce this speed. The use of two-input RAM in analog input devices allows you to reduce the processor machine time spent working with an analog input device to the lowest possible level, which should be considered the time required for the processor to work with the simplest static type RAM, which has a volume corresponding to the product of the number of ADC channels on demand frequency.

 A data acquisition device [2] is known, which contains an information input unit, which includes an analog signal and ADC multiplexer, two-input RAM, a buffer, an addressing unit, a control unit, an address register, and the analog inputs of the information input unit are device inputs and outputs are connected to the data inputs of two-input RAM, the outputs of which are connected via a buffer to the data bus of the central processor. The inputs of the addressing unit are connected to the address bus of the central processor, and the output is connected to the address inputs of the dual-input RAM record and to the address inputs of the multiplexer of the information input unit. The address inputs for reading two-input RAM are connected to the outputs of the address register, the information inputs of which are connected to the address bus, and the control input is connected to the control bus of the central processor. The first output of the control unit is connected to the control input of the addressing unit, and the second output is connected to the synchronization input of two-input RAM.

 The central processor implements a program for polling signal sources and converting information. The program for interrogating signal sources is a time alternation of a sequence of address codes of a multiplexer that performs switching of signal sources under the control of an addressing unit. The signals from the output of the multiplexer are fed to the input of the ADC, which converts these signals into digital codes. The latter from the ADC output go to the data inputs of two-input RAM. In accordance with the address code coming from the addressing unit to the address inputs of the dual-input RAM record, the converted information is written to the corresponding cell. The central processor implements an information reading program, which is an alternation in time of a sequence of codes recorded in the address register. The address register addresses two-input RAM when reading information from it through a buffer into the data bus. The control unit generates write pulses for two-input RAM and synchronizes the operation of the addressing unit. The use of two-input RAM in this device implies a significant investment of time in software for analog-to-digital conversion. Reducing these time costs can be achieved by transferring the information input unit to offline mode. In this case, the central processor is freed from the program of polling signal sources, and the time spent on write cycles in the addressing unit is excluded.

 The present invention solves the problem of increasing the speed of the device. The technical result is to reduce the time spent on software maintenance of the data acquisition device by translating the information input unit into offline mode while ensuring the accuracy of the information in case of simultaneous access to RAM for reading and writing.

 Into a device containing an information input unit, two-input RAM, a buffer, an address block, an address register, a control unit, a code comparison unit, a write pulse generator are input, and the inputs of the information input unit are information inputs of the device, and the information outputs are connected to data inputs of a two-input RAM . The data outputs of the latter through a buffer are connected to the output of the device. The address inputs of the information input unit, the address inputs of the two-input RAM recording and the first group of inputs of the code comparison unit are connected to the outputs of the addressing unit, and the outputs of the address register are connected to the read address inputs of the two-input RAM and to the second group of inputs of the code comparison unit, the output of which is connected to the blocking input pulse shaper recording. The output of the specified driver is connected to the synchronization input of a two-input RAM. The inputs of the address register are the address inputs of the device, the synchronization input of the specified register and the input of the control unit are the control inputs of the device. The first output of the control unit is connected to the clock input of the addressing unit, the second output is with the control input of the code comparison unit, the third output is with the input of the write pulse generator, and the fourth output is with the buffer control input.

 Figure 1 presents a structural diagram of a data acquisition device, where 1 is an information input unit, 2 is a two-input RAM, 3 is a buffer, 4 is an addressing unit, 5 is an address register, 6 is a control unit, 7 is a code comparison unit, 8 is recording pulse shaper.

 Figure 2 presents the timing diagrams of operation, where 1 is the pulse of the end of the conversion, 2 is the pulse of the change of address, 3 is the pulse of blocking, 4 is the pulse of writing, 5 is the pulse of writing to RAM, 6 is the pulse of reading data.

 Figure 3 presents the structural diagram of the block comparison codes.

 Figure 4 presents the structural diagram of the pulse shaper recording.

 As shown in figure 1, the inputs of the input unit information 1 are used to connect to signal sources. The purpose of block 1 is to interrogate signal sources connected to the information inputs of the device and convert the signals to a digital code. Block 1 includes a multiplexer and an ADC (not shown in FIG. 1). Two-input RAM 2 is intended for temporary storage of converted information and subsequent output through buffer 3 to the processor data bus. The addressing unit 4 may be made in the form of an address counter. The address counter is designed to address the multiplexer unit 1, two-input RAM 2 in the mode of conversion and data recording. The address register 5 addresses the two-input RAM 2 in the mode of reading data from it under the control of the central processor. The inputs of address register 5 are used to connect to the address bus, and the synchronization input is to the control bus of the central processor. The control unit 6 consists of a pulse shaper for changing the address of the address counter of block 4, a pulse shaper for reading data for a buffer 3 that enters data into the central processor, a pulse shaper for permission for the code comparison unit 7, a pulse shaper for the conversion end (not shown in Fig. 1) . The code comparison unit 7 is intended for comparing address codes and generating a blocking pulse for the shaper 8. The shaper 8 is intended for generating a data recording pulse from the information input unit 1 in RAM 2.

 As shown in FIG. 3, the code comparison unit 7 may include a code comparator 9 and an OR element 10, wherein the first group of inputs of the comparator 9 is the first group of inputs of the block 7, and the second group of inputs is the second group of inputs of the specified block. The output of the comparator 9 is connected to the first input of the OR element 10, and the second input of this element is the control input of the code comparison unit 7. The output of the OR element 10 is the output of the code comparison unit 7.

 As shown in figure 4, the recording pulse shaper 8 may include a single vibrator 11 based on the front-triggered trigger and the element And 12, and the input blocking the operation of the one-shot 11 and the first input of the element And 12 are combined and are the blocking input of the shaper 8, the second input of the element And 12 is the input of the specified shaper. The output of the one-shot 11 is the output of the shaper 8, and the synchronization input is connected to the output of the element And 12.

The device operates as follows. The multiplexer of block 1 under the control of the counter of the address of block 4 polls the signal sources. The polling period T ₆ is determined by the frequency of the clock pulses from the output of block 6, which are received at the counting input of the specified counter (figure 2, diagram 2). The signals from the output of the multiplexer are fed to the input of the ADC, which converts these signals into digital codes. Each digital signal code is recorded in the corresponding cell of the two-input RAM 2, addressed using the counter of block 4. Moreover, the address code of the corresponding cell is fed to the entries of the write address of the specified RAM. Data recording from the ADC output takes place according to the positive difference of the recording pulse received from the output of the shaper 8. The central processor implements an information reading program, which is an alternation in time of a sequence of codes written to the address register 5. Address register 5 addresses two-input RAM 2, moreover, the address code of the corresponding cell goes to the inputs of the address of reading RAM 2. Data is read when the address code is set on the address inputs of RAM 2. Yes The data are sent to the data bus of the central processor by a data read signal. This signal comes from the control bus to block 6, which forms a data read pulse from it with the necessary delay (Fig. 2, diagram 6). A data read pulse arrives at the control input of the buffer and allows the data to pass through to the CPU bus. In case of mismatch of the codes of the read and write addresses, the output of the code comparison unit 7 is logical “1”, driver 8 is unlocked. The pulse of the conversion end t ₆ (Fig. 2, diagram 1) from the output of block 6 goes to the input of the shaper 8. According to the positive difference of the specified pulse, the shaper 8 generates a write pulse in RAM 2, which goes to the synchronization input of the RAM 2. If the address codes match read and write block comparison codes 7 generates a blocking pulse (figure 2, chart 3). For normal operation of the device, it is necessary that the duration of this pulse is t ₇ <t ₆ . There are three options for the operation of the device if the address codes match. In the first case, the data read impulse arrives before the end-of-conversion impulse, in the second - the data read impulse comes later, in the third - the data read impulse arrives during the action of the end-of-conversion impulse. In all three cases of the device’s operation, the code comparator 9 generates a permission signal, which is fed to the input of the OR element 10. A pulse to read data from the output of block 6 is received at the other input of this element. A blocking pulse appears at the output of the OR element 10 (Fig. 2, diagram 3 ), which is fed to the information input of the one-shot 11 and the input of the element And 12. The pulse of the end of the conversion is received at the other input of this element. Element And 12 generates a pulse (Fig. 2, diagram 4), arriving at the clock input of a single-shot 11. Based on the positive difference of this pulse at the output of a single-shot 11, a write pulse is generated in RAM 2. Thus, in the first case of operation of the device, data is read first, and then write data to the next RAM cell 2. As mentioned above, the data read pulse (Fig. 2, diagram 6) is generated by block 6 with a delay t ' ₆ ≥t' ₂ + t ' ₅ + t' ₇ , necessary to establish data at the input of buffer 3, where t ' ₂ is the response time of RAM 2, t' ₅ is the time response register address 5, t ' ₇ is the response time of block 7. As shown in figure 2, in the second case of the device, the data is first written to the next RAM cell 2, and then the data is read. In the third case of the operation of the device, two write pulses are generated in RAM 2, respectively, before reading data and after. Moreover, in order for the data to be reliably recorded at the set address, it is necessary that the pulse of the change of address be delayed relative to the pulse of the end of the conversion for a time t'≥t ' ₂ .

 As can be seen from the description and the graphic materials, the proposed device by providing an autonomous process of polling and data conversion allows you to unload the central processor, eliminate the time spent on machine maintenance and thereby improve the performance of the data acquisition device compared to the prototype. An additional advantage of the proposed device is the small hardware costs of implementation compared, for example, with devices using direct access to the memory of the central processor. The proposed device is more efficient and reliable when used in conversion systems of analog and discrete information serving a large number of controlled objects. The data acquisition device can be implemented using an inexpensive element base of domestic or imported. For example, a frequency signal receiving module using the proposed technical solution is implemented on 564, 140, 588 series microcircuits.

Sources of information
1. Description to the copyright certificate of the USSR 1642883.

 2. Chernov V. G. Devices of input-output of analog information for digital systems of data collection and processing. - M.: Mechanical Engineering, 1988, p. 144.

Claims (4)

1. A data acquisition device comprising an information input unit, a two-input random access memory (RAM), a buffer, an addressing unit, a control unit, an address register, wherein the inputs of the information input unit are information inputs of the device, and the information outputs are connected to data inputs of a two-input RAM, the data outputs of which are connected to the inputs of the buffer, the outputs of which are the output of the device, the address inputs of the information input unit, the address inputs of the two-input RAM record are connected to the outputs of the addressing unit, and in the address register moves are connected to the address inputs of reading the two-input RAM, the address register inputs are the address inputs of the device, and the synchronization input is the first control input of the device, the first output of the control unit is connected to the input of the addressing unit, characterized in that a code comparison unit and a shaper are introduced into it a write pulse, the input of the control unit being the second control input of the device, the second output connected to the control input of the code comparison unit, the third output to the input of the driver recording pulse, the output of which is connected to the synchronization input of two-input RAM, and the fourth output is to the buffer control input, the write pulse generator blocking input is connected to the output of the code comparison unit, the first group of inputs of which is connected to the outputs of the addressing unit, and the second group of inputs - to the outputs address register. 2. The data collection device according to claim 1, characterized in that the code comparison unit contains a code comparator and an OR element, the first group of inputs of the code comparator being the first group of inputs of the code comparison unit, and the second group of inputs of the code comparator is the second group of inputs of the last, the output of the code comparator is connected to the first input of the OR element, the second input of which is the control input of the code comparison unit, and the output is the output of the specified block. 3. The data acquisition device according to claim 1, characterized in that the recording pulse shaper comprises a single vibrator and an I element, the first input of the I element and the information input of the single vibrator being interconnected and are a blocking input of the recording pulse shaper, the second input of the And element is an input of the specified of the shaper, the clock input of the one-shot is connected to the output of the And element, and the output of the one-shot is the output of the shaper of the recording pulse. 4. The data acquisition device according to claim 1, characterized in that the addressing unit is designed as an address counter, the counting input of the latter being the input of the addressing unit, and the outputs being the outputs of the specified unit.

Images