SU1612290A2 - Multichannel data input device - Google Patents

Abstract

The invention can be used in input devices in a computer. The purpose of the invention is to expand the field of application of the device by providing the possibility of sampling and storing software-defined codes from the arrays of input information with the subsequent storage of selected matched codes. The device contains in each channel triggers 1, 2, elements OR 6, 16, counters 7, 12, 20, 22, blocks 9, 14, 18 comparisons, trigger 19, driver of a single pulse 21, block 24 of registers, decoder 27, block 28 indications. Using the programmable code, the device inputs 29 check the operation of each channel of the device, the comparison takes place at comparison unit 18, the comparison results are recorded in register register 24, the first channel of which records information at the addresses generated by the counter 20, and the second channel reading the information on the addresses of the counter 22 via the counting pulse input 23, through the code decoder 27, the contents of the RAM are displayed on the display unit 28.

Description

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specified codes from the input data arrays with subsequent storage of the selected matched codes. The device contains in each channel triggers 1,2, elements OR 6, 16, counters 7, 12, 20, 22, blocks 9, 14, 18 comparison, trigger 19, driver of a single pulse 21, register block 24, decoder 27, block 28 i-diction. Using the programmable code, the device inputs 29 check the operation of each device channel. Comparison occurs at comparison unit 18, the comparison results are recorded in register register 24, the first channel of which records information at the addresses generated by the counter 20, and the second channel - reading the information on the addresses of the counter 22 via the counting pulse input 23, through the code decoder 27, the contents of the RAM are displayed on the display unit 28. 1 il.

The invention relates to automation and computing, can be used to enter information into a computer with indication of the contents of the RAM for viewing control codes and is an improvement of the invention according to the author. St. No. 1525696.

The purpose of the invention is to expand the area of application of the device due to the possibility of sampling and storing software-defined codes.

Figure 1 shows the structure of a multichannel input device.

The device contains in each channel the first trigger 1 and the second trigger 2, information input 3, output 4 of the first group and output 5 of the second group, as well as the first element OR 6 first counter 7, device sync input 8, first comparison block 9, set-up inputs 10 code, element 2I-NOT II, second counter 12, first element 2I 13, second comparison block 14, inputs 15 specifying a code, second SH 18 element, second element 2И 17 third comparison block 18, third trigger 19, third counter 20, driver 21 single-pulse, four-quarter counter 22, counting pulse input 23, block 2 4 registers, positive bus 25 and device negative potential bus 26, decoder 27, display unit 28, code setting inputs 29.

The device works as follows.

When the power is turned on, the device inputs 3 have low voltage levels, corresponding to the absence of input signals. At the direct outputs of the triggers 1 - low levels of voltage, on inverse - high. Triggers 2 are in the initial state, i.e. At their outputs, low voltage levels are set and inverse voltages are high. The high voltage levels of the corresponding inverse outputs of the flip-flops 1 and 2 keep the counters 7 and 12 in the zero state through the OR 6 and 16 elements. Low voltages from blocks 14, 18 and 9 prohibit the passage of clock pulses from the synchronization input 8 to the outputs of the elements 13 , 11 and 17. When the power is turned on, the single pulse shaper 21 zeroes the counters 20 and 22 with a single negative polarity pulse. The low voltage level from the output of the comparator unit 18 keeps the 1K-trigger 19 in the initial state. To the recording input of the first channel of the block 24 dual-address registers (for example, type KR1802IP1) receives a high voltage level from the inverse output of the trigger 19. High voltage level tires Power supply 25 of the device is fed to the input of the first channel and to the recording input of the second channel of the register block 24, i.e. reading mode on the first channel and recording mode on the second channel are prohibited. The low voltage level from the bus 26 turns on (chip selection) both channels of the register block 24 and enables the reading mode on the second channel. The zero address from the output of counter 22 is read in the order of the second channel addresses, therefore, the information of the first register of the register block at the zero address is decrypted by the desigger 27 and displayed on the display unit 28. The device is in its original state.

When the input signals are received, the triggers 1 are cocked on the leading edge of the input signal. High levels of signals from the outputs of the first triggers 1 are fed to the J-inputs; at the same time, low levels of voltage from the inverse outputs of the triggers 1 are fed through the OR 16 element to the R-count of the counter 12 and allow it to work. The counter 12 starts counting the clock pulses coming from the input 8 of the device synchronization. On the leading edge of the hg pulse of the clock frequency at the output of the counter 12, a code is established that coincides with the code on the input 15 of the code for the appearance of the leading edge of the output pulses of the device.

Indeed, a high voltage level is established at the output of the comparator unit 14, which permits the passage of the t-th pulse through the element 2I 13 to the C inputs of the triggers 2. The information from the J inputs of the triggers 2 is copied to the outputs 4 and 5 of the first and second groups of the device, respectively. . Low voltage levels from the inverse outputs of the second triggers 2 through the element OR 6 arrive at the R input of the counter 7 and permit its operation. Counter 7 starts counting the clock pulses from the input 3 synchro. At the same time, low voltage levels from the inverted outputs of the flip-flops 2 arrive at the K-in power of flip-flops 1 and bring these triggers back to their original states. Through the RSHI element 16, the counter 12 is zeroed, and low voltage levels are set at the J-inputs of the flip-flops 2. On the leading edge of the nth pulse from the input 8 at the output of the counter 7, it sets a code that coincides with the code on the inputs 10 of the code controlling the duration of the output pulses. At the output of the comparator unit 9, a high voltage level is established which permits the passage of the nth pulse of the clock frequency through the element 2I-NO 1 1 to the P inputs of the flip-flops 2, since the pulse has an inverse form, the flip-flops 2 are reset. The formation of the duration of the output pulses of the device | C; tva, i.e. at the direct outputs, 4 triggers 2 set-low voltage levels, and on the inverse outputs high. High levels for example

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Neither from the inverted outputs of the flip-flops 2 are reset through the OR 6 element at the R input of the counter 7, the outputs of blocks 14 and 9 compare low voltage levels, the counters 12 and 7 reset the triggers 1 and 2 in the initial state, t. e. With the arrival of the following 3 input pulses at the inputs, the device continues its operation first.

This operation continues until the information code of all channels from the outputs of the trigger 2 does not coincide with the code at the inputs 29 of the sample control. At the output of the comparator unit 18, a high voltage level appears, which permits the passage of the k-ro pulse to the output of element 2 and 7 and enables the JK flip-flop 19 to work through the inputs J, K, R. On the leading edge of the k-ro pulse, a counter 20 is set. from the outputs of which the address is fed to the address buses of the first channel of block 24 of registers. On the falling edge of the k-ro pulse, trigger 19 is cocked, from an inverse output of which a low voltage level arrives at the recording input of the first channel and records information that stands at the outputs of the trigger 2 to the initial address. With the arrival of the next code from the device output to the group of block inputs

18, which does not coincide with the code at the inputs 29 of the device, a low voltage level is established at the output of block 18.

This level resets the trigger.

19in the initial state and prohibits the passage of pulses of the clock frequency to the C input of the counter 20. A high voltage level appears at the recording output of the first channel of the block 24. As block 24 of registers on the second channel is always in read mode, then by setting 29 on a code that obviously doesn’t compare with the output code of the device, you can use a counting pulse on input 23 of counter 22, which goes through the addresses of the operational memory of the block 24 registers, read information about the health of channels of a multi-channel input device. This information is displayed on the display unit 28. If the operator sets the address on the counter 22, the same address of the counter 20 after comparing the codes on the block

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ke 18, then the result of the performance of each channel can be seen on the display unit 28 each time after the coincidence of the input device code with the code on the inputs 29.

Claims (1)

Invention Formula Multichannel device for; water information on the author. Ev, No. 152569 | o; tl and ch yu e with the fact that with | the purpose of expanding the scope of application | and the device due to the possibility of sampling and storing software-defined Ne1x codes entered into it, the third b | by comparison, the third and fourth counters, a single pulse shaper, a block of registers, a decoder bpok display, the third the trigger, the second element 2I, the first input of which is connected to the synchronization input of the device, the second input is connected to the output comparison unit and to the E | J, K, R third trigger moves, and the E | IS input is connected to the three-way clock input and the third counter, entrance. reset cat This is connected to the output of a single pulse and with the input c, q 0 five resetting the fourth counter, the sync input of which is the device’s pulse count, the outputs of the third counter are connected to the first group of address inputs of the register block, the second group of address inputs of which are connected to the outputs of the fourth counter, the first input of the register block is connected to the inverse output of the third trigger , the first reading input of the register block is combined with its second write input and connected to the positive potential bus, the first input of switching on the block of registers is combined with its second reading inputs and switching on and connected to the zero potential bus, the second group and the information outputs of the register block are connected to the inputs of the decoder, the outputs of which are connected to the input of the display unit, the first group of information outputs of the register block, are connected to the inputs of the first group of the third comparison unit and the direct outputs of the corresponding second the triggers, the inputs of the second group of the third comparison unit are an additional group of inputs for the output of the device.