SU1070532A1 - Device for forming time intervals - Google Patents

Abstract

1. DEVICE FOR FORMING TEMPORARY INTERVALS, containing a pulse counter, connected by a reset to the zeroing bus, information (HW tires, fixed frequency bus, characterized in that, in order to improve the noise immunity of the device, a memory register, sync bus, first and the second write resolution bus, the overflow bus, the comparator connected by the first inputs to the outputs of each bit of the pulse counter, the fault input to the overflow bus, and the second inputs to the corresponding output the memory register associated with the installation inputs with the corresponding information buses connected to the information inputs of the corresponding bits of the Impulses counter connected by the synchronization input, the counting input, the control input, respectively, the synchronization bus, the fixed frequency bus and the first write resolution bus, wherein the control input of the memory register is connected to the second bus resolution (O or a record, and the output of the last bit is connected to the overflow bus.

Description

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2. The device according to claim 1, characterized in that each bit of the pulse counter contains a w-flip-flop, the first and second elements are NOT, the AND-NOT element, the first, second and third AND elements, the OR-NOT element, connected to the output by D - input of D-flip-flop connected by C-input with synchronization input, direct output - with the first input of the first element AND connected by the second input to the first input of the NAND element and to the output of the first element NOT connected to the input with the control input of the pulse counter and with the first input of the second element AND, the connection is referred to as Computational techniques and can be used in various devices to form time intervals of a given duration. A device for forming time intervals is known, which contains a clock counter, control triggers, the outputs of which are outputs of the device, a decoder, the first input group of which is connected to the outputs of the counter of clock pulses, the second group of inputs to the information inputs of the device, and AND, OR elements 1. However, this device is characterized by insufficient noise immunity under the conditions of exposure to destabilizing factors (for example, an increased level of electrical / noise interference, including high frequency). Closest to the present invention is a device for forming time intervals, comprising a counter, connected to a decoder whose outputs are connected to control 155 -triggers and has a t-input connected to fixed-frequency t-sources, which are connected to the corresponding main elements the outputs of which are connected to the inputs of the first OR element, the output of the latter is connected to the counter input of the counter, and the outputs of the control 5 & triggers are connected to the inputs of the second OR element, and the inverse output actuating RS-flip-flops are connected to the inputs of R-dopolnitolnyh OF -triggerov and straight outputs to inputs of the first additional element and a second input connected to the output of first OR

by the second input to the waste input of the pulse counter, and the third input to the inverse output of the first L-trigger and to the second input of the NAND element connected by the output to the first input of the second element AND the subsequent discharge and to the input of the second element NOT connected to the output to the second input of the first element And the subsequent discharge, with the first and second inputs of the third element And connected respectively to the installation and control inputs of the pulse counter, and the outputs of the first, second and third elements and to the input element OR NO. The outputs of the additional elements AND are connected to the S-inputs of additional RS-flip-flops 2. The drawback of the device lies in the absence of a common pass-through synchronization, which leads to hard-to-detect and even more difficult to remove faults, the purpose of the invention is to improve the noise immunity devices. The goal is achieved by the fact that the device for forming time intervals, containing a pulse counter, connected by a fault input to the zeroing bus, information buses, a fixed frequency bus, is entered into a memory register, a sync bus, the first and second write resolution buses, an overflow bus, a comparator connected by the first inputs to the outputs of each bit of the pulse counter, the fault input to the overflow bus, and the second inputs to the corresponding outputs of the memory register connected by the setting inputs Data with the corresponding data busses / connected to the information inputs of the corresponding bits, the pulse counter connected by the synchronization input, the counting input, the control input, respectively, of the synchronous synchronization, the fixed frequency bus and the first recording resolution bus, and the control input of the memory register connected to the second write resolution bus, and the last bit output is k overflow bus. Each bit of the pulse counter contains a D-trigger, the first and second elements are NOT, the AND-NOT element, the first, second and third elements are AND, the OR-NOT element, connected to the D-input of a D-trigger connected to the C-input with synchronization input, direct output - with the first input of the first AND element connected by the second input to the first input of the NAND element and to the output of the first element NOT connected by the input with the control input of the pulse counter and with the first input of the second AND element connected the second input to the reset input of the pulse counter, and re, dark input - to the inverse output of the first D-flip-flop and to the second input of the NAND element connected by the output to the first input of the second element And the next digit and to the input of the second element NOT connected by the output to the second input of the first element AND the subsequent discharge, the first and second inputs of the third element I are connected respectively to the installation and to the control inputs of the pulse counter, and the outputs of the first, second and third elements AND to the input of the element OR NOT. FIG. 1 shows a functional diagram of the device; Figure 2 is a circuit diagram of one bit of a counter and one bit of a register; in fig. 3 - time diagram. The device contains a counter 1, consisting of 1-1 ... 1-n bits, register 2 memory, also consisting of 2-1 ... 2-n bits and a comparator, each digit of the counter 1 contains the element OR -NOT 4, D-flip-flop 5, first element NOT B, element YNE 7, all the element NOT 8, lane. the second, second, and third elements of M 9, 10, and 11, additionally in FIG. one bit of register (memory) 12 and elements of the second bit of the counter are shown, the fourth elements are AND 13, the element OR is NOT 14 counters. FIG. 1-2 p {buttons are the following designations of tires and signals: Q and O are the forward and inverse outputs of the trigger, C is the synchronization bus, FROM the first recording resolution (e counter), FROM 2 .- the second recording resolution bus ( register) - obiuleni bus, I - fixed frequency bus, p - counter overflow (carry) signal. The device works as follows. After zeroing (by the signal Obn.), Counter 1 receives the first time / EXT code for information f buses, which is recorded at the signal FROM 1, then the second time counter code is written to register 2 for the same information buses, signal FROM 2 Moreover, the code of the first time delay is received and recorded in the reverse code, and the code of the second time support in the forward code. With the arrival of the If signal, which consists of a command to start counting time intervals and pulses of a fixed frequency, the counting of the pulses by the counter of the first counter begins. After filling in counter 1 (all triggers have a logical unit at the inverse output), an overflow signal (p) is output, which signals the end of the first time limit and simultaneously enables the (digital) comparator 3. After the signal P has been received, the counter continues to count further until until its state is comparable to the code (state) recorded in memory register 2. The equality of codes is fixed by Comparator 3, after which a signal is issued Equality of codes, which removes the signal H (fixed frequency) and is the end of the second time delay of the Formation of the signals Obn., H and their removal is not shown conventionally. Such a construction of the functional circuit of the device allows one to obtain two time intervals with optimal hardware costs. With the need to obtain a large number of time slots, it is necessary to supply several additional digital comparators (according to the number of required time slots). The following provisions are taken as the basis for constructing the principle cxeNfij device: the presence of a common synchronizing pulse sequence for the system and the whole, the reception, processing and output of all signals without exception synchronously with the pulse sequence, i.e. the duration of any pulsed signal must be equal to the frequency synchronization period or a multiple of it. It is convenient to consider the operation of a single bit of a counter in a schematic diagram (Fig. 2) and in a time diagram (Fig. 3) in the recording and counting mode. In the recording mode information is as follows. With the arrival of the information bus (inf.) The recording pulse input, which needs to be recorded (time t), and with the arrival of the write enable pulse AND 31, the element 10 is ready for operation. Therefore, the output of the element 4 (at the input of the D flip-flop 5) is is O, which prepares, and the strobe-pulse (time t) pebrasyvaet trigger 5c on (output 0). This condition can be poured for a long time. Let us consider the return of the discharge to the initial state (time to or tj). Signal Ref.

comes during ctj (or at another time), changing the output state of element 4c O by 1 and, which, in turn, by a strobe pulse causes the flip-flop of a trigger, which is equivalent to its transition to its original state.

In the counting mode, operation proceeds as follows. With the arrival of the first pulse of the counting sequence (time tt4) at the inputs of the element, AND (input H) is removed, therefore, at the output of element 4 (at the input of D-flip-flop 5) it appears. The trigger is prepared for reversal and, via a strobe pulse (time t), changes its state (overturns), after which element 4 is not yet ready for operation, since at time tj. (end of the first pulse) there is no change at its inputs. Thus, at the input of the D-flip-flop 5, the state does not change until the second counting pulse H arrives (time t,). With the arrival of this imn exit

pulse arises

element b, which, folding

from the output Oh, changes the state

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I. L-r element 4 (input D-flip-flop 5), pod-, preparing a trigger for the flip. With the arrival of the strobe pulse (time tj), the trigger is transferred. Then the cycle repeats, starting at time ts.

Simultaneously with the arrival of the second counting pulse, the inverse and forward jib pulses (time i tJ, and t) are generated on elements 7 and 8 of frp-j, which also affect the second-bit element 13 and OR-HE 14 of the second bit.

The proposed device for forming time intervals can be used in various control and test settings, in which the time delays are programmed, in a personal way, and the construction of a functional and schematic circuit allows

optimize hardware costs with high accuracy of forming time intervals of various durations, as well as increased noise immunity, which is especially important

when the equipment is operated in industrial premises with a high level of electrical noise.

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Claims (2)

1. DEVICE FOR FORMING TIME INTERVALS, comprising a pulse counter, an input reset connected to the zeroing bus, information buses, a fixed frequency bus, characterized in that, in order to increase the noise immunity of the device, a memory register, a synchronization bus, the first and second buses are introduced into it write enable buses, overflow bus, 'comparator connected by the first inputs to the outputs of each discharge of the pulse counter, the dump input to the overflow bus, and the second inputs to the corresponding outputs of the reg tra memory associated with respective locating inputs data lines connected to data inputs of respective bits of the pulse counter, an input connected to the synchronization counting input, a control input respectively to the synchronization bus with a fixed frequency bus and the first bus write enable, _with than control pri- the input of the memory register S8 ty is connected to the second write resolution bus *, and the output of the last row tj of the row is connected to the overflow bus. - FIL, / V 2. The device according to π. 1, the fact that each category of the pulse counter contains a trigger, the first and second elements NOT, the AND element, the first, second and third AND elements, the OR-NOT element connected by the output to the D input of D- a trigger connected by a C-input to the synchronization input, a direct output - with the first input of the first AND element, connected by the second input to the first input of the AND-NOT element and to the output of the first NOT element, connected by the input to the control input of the pulse counter and with the first input of the second element And, connected by the second input to the dump I input a pulse counter, and the third input to the inverse output of the first b-trigger and to the second input of the AND element NOT connected by the output to the first input of the second AND element of the subsequent discharge and to the input of the second element NOT connected by the output to the second input of the first AND element of the subsequent discharge moreover, the first and second inputs of the third AND element are connected respectively to the installation and control inputs of the pulse counter, and the outputs of the first, second and third AND elements are connected to the input of the OR-NOT element.