JPH05227133A - Parity check circuit - Google Patents

Abstract

PURPOSE:To provide a parity check circuit for multiplex data whose configuration can be simplified by reducing an E-OR and by which the merits of capacity and cost can be obtained. CONSTITUTION:This circuit is comprised in such a way that a data inversion means 40 in common to each of data groups DA...DD which inverts odd pieces of data in the data groups DA...DD in one frame corresponding to a polarity setting signal S4 is provided at the front stage of parity counters 100:100A...100D in the parity check circuit provided with the parity counters 100:100A...100D and data latches 200:200A...200D which hold count results by the counters 100:100A...100D in accordance with the data groups DA...DD for multiplexed input data S3 in which plural data groups DA...DD are multiplexed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check circuit, and more particularly to a parity check circuit for multiplexed input data.

[0002]

2. Description of the Related Art Parity check circuits include a circuit for detecting odd parity and a circuit for detecting even parity.

If one parity check circuit can detect both odd parity and even parity, the operation of the parity error detection function and the error rate function can be verified at system startup and system test. Very useful. Therefore, there is a case where a parity check circuit capable of detecting the odd parity or the even parity as described above is used so that the polarity can be set from the outside.

FIG. 7 shows a basic structure of a conventional parity check circuit used for such a purpose, and FIG. 8 is a timing chart thereof. This parity check circuit basically includes a parity counter 100 and the parity counter 1
The data latch 200 holds the count result of "00" and the polarity setting means 300.

In the parity counter 100, the input data S
₂₃ (FIG. 8 (c)) is an absolute OR circuit (hereinafter, E-OR circuit)
It is input to 111). On the other hand, the AND gate 112 outputs the frame timing signal S ₂₂ (FIG. 8B).
And the output S ₂₄ (FIG. 8D) of the flip-flop 113, which will be described later, are ANDed to obtain the above E-OR.
It is input to the circuit 111. Further, the output of the E-OR circuit 111 is input to the D terminal of the flip-flop 113.

The parity counter 10 having the above configuration
0, the frame timing signal S_{twenty two}Beginning period of
(Frame timing signal S_{twenty two}Is “1”),
The output of the AND gate 112 becomes "0", and E-OR times
The output of path 111 is the input data S _{twenty three}The "1" in (A-1)
And is input to the flip-flop 113.

Next, when the frame timing signal S ₂₂ becomes "0", the output of the flip-flop 113 receives the output of the E-OR circuit 111 and becomes "1", so that the output of the AND gate 112 becomes It becomes "1". At this time, since the input data S ₂₃ (A-2) is “0”, the output of the flip-flop 113 eventually becomes “1”. By repeating the above procedure, the output S24 of the parity counter 100 as shown in FIG. 8D is obtained.

The output S24 of the parity counter 100
Indicates whether the number of data input in one cycle of the frame timing signal S ₂₂ is even or odd (“1” or “0”) at the beginning of the next cycle of the frame timing signal S ₂₂ (FIG. 8). (B) and (d), especially the timings t ₂₁ , t _22, ...

Then, the selector 211 of the data latch 200 to which the output of the parity counter 100 is input is in the leading period of each cycle of the frame timing signal S ₂₂ (as described above, the frame timing signal S ₂₂ is "1"). , The output of the parity counter 100 is the flip-flop 2
12 is input to the flip-flop 212 when the frame timing signal S ₂₂ becomes “0”.
It is designed to input its own output. This data latch 200 when the parity in the previous frame as shown in FIG. 8 (e) of the odd number of "1", it outputs a "0" when the even number signal S _25.

The output of the data latch 200 is input to the E-OR circuit 301 as the polarity setting means 300.
This is the E-OR circuit 301 and the polarity setting signal S ₂₆ is input as shown in FIG. 8 (f), the polar set signal S ₂₆
Is "0", the output signal S of the data latch 200 is
₂₅ passes through the E-OR circuit 301 as it is, and when it is "1", as shown by the signal S ₂₇ in FIG.
The output of 00 is inverted (polarity is converted) and output.

FIG. 9 shows multiplexed input data S ₃₃ (DA ... D).
The parity check circuit for D) is shown, and FIG. 10 is a timing chart thereof. The parity check circuit shown in FIG. 9 uses each data group DA forming the multiplexed input data S _33.
... corresponding to DD, parity counter 100A ... 100
200D, and polarity setting means 300A ... 300D. In this case, the unit parity check circuit is provided with the same parity check circuit as shown in FIG.

The multiplexed input data S ₃₃ is the E-OR circuit 111A ... 1 of each parity counter 100A ... 100D.
11D provided in front of 11D 114A ... 11
Enable signal S ₃₅ A which is input to 4D and becomes "1" in response to the input timing of each data group DA ... DD.
... allocated to each data group DA ... DD by S ₃₅ D, is input to the corresponding parity counter 100A ... 100D. The operation thereafter is exactly the same as that shown in FIGS. 7 and 8 as shown in FIG. 10, and the outputs S ₃₆ A ... S ₃₆ D of the parity counters 100A ... 100D are input to the data latches 200A. Each data latch 2
The outputs S ₃₇ A ... S ₃₇ D of 00A ... 200D are output as they are or by being inverted from the respective E-OR circuits 301A ... 301D as the polarity setting means 300.

The frame timing signals S ₃₄ A ... S ₃₄ D in FIG. 10 are expressed as a length obtained by dividing the frame timing signal S ₃₂ of each parity check circuit by the number of data groups (4 in this case, A to D). ing. Since the other points are exactly the same as the time chart shown in FIG. 8, detailed description thereof will be omitted here.

[0014]

When the above conventional circuit is used, E-OR circuits 111A ... 111D used in parity counters 100A ... 100D and E-OR for polarity setting are used.
The OR circuits 301A ... 301D are required in the number corresponding to the multiplicity n, but the E-OR circuit has a relatively high cost, resulting in a cost demerit, a complicated circuit configuration, and a further volume demerit. Will occur.

The present invention has been proposed in view of the above-mentioned conventional circumstances, and the parity check for multiplexed data is advantageous in that the number of E-OR circuits is reduced, the configuration is simplified, and volume and cost advantages are obtained. The purpose is to provide a circuit.

[0016]

The present invention employs the following means in order to achieve the above object. That is, as shown in FIG. 1, parity counters 10: 10A ... 10D corresponding to each data group DA ... DD of multiplexed input data (S ₃ ) in which a plurality of data groups DA ... DD are multiplexed, In the parity check circuit provided with the data latches 20: 20A ... 20D for holding the count results by the counters 10: 10A ... 10D, the parity counter 1
Data inversion means 40 common to each data group DA ... DD that inverts an odd number of data in each data group DA ... DD of one frame according to the polarity setting signal S ₄ before 0: 10A ... 10D. Is provided.

[0017]

The input data A-1 to A as shown in FIG.
-5 (the total number of data is an odd number), or input data A-1 to A-6 (the total number of data is an even number) as shown in FIG. 2B.
Among them, when an odd number of data is inverted, the parity changes from odd to even or from even to odd (that is, the polarity of parity changes).

As a result, the conventional data latch 20 described above is provided.
It can be understood that the polarity can be indirectly converted only by inverting an odd number of input data without directly setting the polarity for the data output by 0.

In order to invert an odd number of data as described above, the data inversion means 40 common to a plurality of parity counters corresponding to each data group DA ... DD is used as shown in FIG. In the data inverting means 40, for example, only one data at the head of the data of each data group DA ... DD which forms the multiplexed input data S ₃ is set to the polarity setting signal S.
_{According to 4} , it is inverted by the E-OR circuit 41 and input to the parity counter.

[0020]

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIGS. 4 and 5 are timing charts thereof. Note that the enable signal S ₃₅ A ... S ₃₅ D appearing in FIG. 3, the frame timing signal S ₃₄ A ... S ₃₄ D Figure 9 are denoted by the same reference numerals as used in FIG. 10.

Data inversion means 40 common to each parity check circuit corresponding to each data group DA ... DD constituting the multiplexed input data S ₃ is provided. In this data inverting means 40, each data group DA ... DD is input to an absolute OR circuit (hereinafter referred to as an E-OR circuit) 41. On the other hand, the frame timing signal S ₂ is input to the AND gate 42, and the polarity setting signal S ₄ is further input to the AND gate 42. The output of the AND gate 42 is the other input of the E-OR circuit 41.

Here, when the polarity setting signal S ₄ is "0" as shown in FIG. 4D, the output of the AND gate 42 becomes "0" regardless of the state of the frame timing signal S _2. The multiplexed input data S ₃ passes through the E-OR circuit 41 as it is, as shown in FIG.
It becomes ₅ and is commonly input to each of the parity counters 10A ... 10D.

As described with reference to FIG. 9, the enable input signals S ₃₅ A ... S ₃₅ D divide the multiplexed input data S ₃ into data groups DA ... DD and input the corresponding parity counters 10A ... 10D. .. Detailed operation of the parity counter 10A ... 10D has omitted the same as the conventional example shown in FIGS. 7 to 10, each parity at the beginning period of the next frame (a period of "1" of the frame timing signal S ₄₎ Output of counter 10A ... 10D S ₆ A
~ S ₆ D represents whether the number of “1” in the previous frame is odd or even (“1” when odd, “0” when even), FIG. 4 (f) → (g), (H) → (i),
As indicated by arrows in (j) → (k) and (l) → (m),
The data latches 20A ... 20D in the next stage hold the state and output as the parity results S _{7 A to} S ₇ D.

As a result, the data latches 20A ... 20
The output of D represents the parity of each data group DA ... DD.
Will be. On the other hand, the polarity setting signal S_FourIs shown in FIG.
As shown in the figure, when it is "1", the output of the AND gate 42 is
Timing signal S₂Is "1" only when is "1"
At this time, the output of the E-OR circuit 41 is inverted. This
By this, multiplexed input data S ₃Is frame timing
Signal S₂Inverted only in the first period of (
The signal S is output from the E-OR circuit 41 by inverting several data.
₅₁(Fig. 5 (o)).

The signal S ₅₁ is the signal S ₅ (E not inverted).
-Output of OR circuit 41), each data group DA ... DD
The corresponding parity counters 10A ... 1
Is input to 0D, the output S ₆₁ A~S ₆₁ D is latched by the data latch 20A ... 20D, FIG. 5 (p) →
(Q), (n) → (s), (t) → (u), (v) →
As shown in (w), the parity results S _{71 A to} S ₇₁ D are output.

The above embodiment can be applied to the case where all the data of each data group DA ... DD is even or odd, but when all the data of each data group is odd, FIG. As shown in FIG. 7, only the E-OR circuit 45 which inputs the multiplexed input data S ₃ and the polarity setting signal S ₄ may be used to invert all the data of the polarity setting signal S ₄ .

[0027]

As described above, according to the present invention, the polarity setting stage 40 common to each data group is provided in front of the parity counter corresponding to each data group of multiplexed data. The number of circuits can be remarkably reduced, so that the structure is simplified, the circuit volume is reduced, and the cost can be kept low.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is a block diagram of an embodiment of the present invention.

FIG. 4 is a timing diagram of FIG.

5 is a timing diagram of FIG.

FIG. 6 is a circuit diagram of an embodiment of the present invention.

FIG. 7 is a basic configuration diagram of a conventional example.

FIG. 8 is a timing diagram of FIG. 7.

FIG. 9 is a configuration diagram of a conventional example for multiplexed data.

FIG. 10 is a timing diagram of FIG.

[Explanation of symbols]

 10A ... 10D Parity counter 20A ... 20D Data latch 40 Data inverting means DA ... DD data group S31 Multiplexed input data

Claims (1)

[Claims] 1. A plurality of data groups (DA ... DD) is in correspondence with the multiplexed input data multiplexed (S ₃₎ each data group (DA ... DD) parity counter (10: 10A ... 10D) and , The counter (1
In a parity check circuit equipped with a data latch (20: 20A ... 20D) that holds the count result by 0: 10A ... 10D), a polarity setting signal (S ₄ ) According to each data group of one frame (DA ... DD)
Each data group (DA…
A parity check circuit characterized in that a common data inverting means (40) is provided for DD).