JPS615628A - Data conversion processing circuit - Google Patents

Abstract

PURPOSE:To prevent a decrease in processing speed by adding a simple dedicated circuit and performing software data processing independently of a main frame. CONSTITUTION:The head address of a table 1 is read out of a register and supplied to the table 1 to read the center boundary value, which is compared by a comparing circuit 5 with a value to be converted which is read out of a register 2 for the value to be converted. When the value to be converted is discriminated as a result, the order of the value to be converted that indicates which area the value belongs to is known, so a selector 6 selects the frequency of comparison of a register 4 sequentially. Then, this is repeated until the value of the sequential comparison register 4 attains to ''0'', thereby knowing which area the value to be converted belongs to.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a circuit that performs data conversion (mainly data encoding) in digital signal processing, and particularly to a circuit that performs data conversion (mainly data encoding) in digital signal processing, and in particular, a circuit that performs data conversion (mainly data encoding) in digital signal processing, and in particular, a circuit that performs data conversion (mainly data encoding) in digital signal processing. The present invention relates to a data conversion processing circuit that performs conversion.

Prior Art and Problems Digital signal processing devices (DSPs) and the like often require complete data conversion processing such as encoding digital data. Conventionally, as a method for performing such data conversion, there is a table reference method in which a table of outputs corresponding to all input buttons is prepared and conversion is performed by referring to this table. In the case of a table reference method, for example, this can be easily done by preparing a table consisting of a read-on memory (ROM) or the like that can read the corresponding output data by using input data as an address. When the number of bits on the paternal side is large, the table size becomes extremely large, making it impractical.

On the other hand, there is a method in which data conversion is performed using software. This method can be used, for example, for conversion in which the output value becomes constant for each value range of input bits. Such conversion can be performed by software processing, but when the number of input bits is large, a large number of instruction steps are required, which reduces the overall processing speed of the signal processing in the main processing system of the signal processing device. Consider the issue of influence.

Purpose of the Invention The present invention attempts to solve the problems of the prior art, and its purpose is to add a simple dedicated circuit consisting of a hardware share to a device that performs data conversion processing. By separating the data conversion processing, which was conventionally processed by software using the main calculation system of the signal processing circuit, from the main body, the data conversion processing circuit can prevent a decrease in processing speed in the signal processing circuit. We are here to provide you with the following.

Structure of the Invention The data conversion processing circuit of the present invention sequentially includes a table that stores the boundary values of each conversion area, a table reference register that generates a reference address for this table, a start address register that stores the start address of the table, and a table that stores the boundary values of each conversion area. A successive approximation count register that stores a value corresponding to the number of times the comparison should be performed, a comparison circuit that compares the boundary value obtained from the table and the converted value to determine whether it is large or small, and a An address control circuit is provided that selects an address obtained by adding 1 to the current address of the table or an address obtained by adding the value of the successive approximation count register to the current address and writes it to the table reference register and updates the value of the successive approximation count register. , in which the area to which the converted value belongs is determined by successively comparing each boundary value and the converted value according to the address of the table reference register from the boundary value stored at the start address of the table. It is.

Embodiments of the Invention FIG. 1 shows nine principle examples of data conversion to which the present invention is directed. In the figure, the entire region of the vagina is divided into 16 regions from ■ to [phase], and boundary values 0 to 15 are determined corresponding to the boundary values of each region.

In this case, for example, first the long sword data is compared with the central boundary value 8 to determine whether it is larger or smaller than this.

If it is larger than the boundary value 8), it is within the input data expansion area ■~[phase], so next it is compared with the boundary value 12 at the center of this area. If the boundary value is smaller than 12, the large sword data is in the area ■
Since it is in ~@, next compare it with the boundary value 10 at the center of this area. By repeating this detailed procedure, encoding (data conversion) is performed in which the human data is converted into an output that indicates to which region the signal belongs. In this case, if it is possible to determine which area the long sword belongs to from the value of the long sword data using simple logic, it is possible to perform efficient conversion processing by combining commands. You can, but
In general, such a logical relationship cannot be expected, and the number of instruction steps increases. Therefore, it has been difficult to perform data conversion using a small-scale circuit without delaying the processing of the entire signal processing circuit.

In order to solve the above problem, the data conversion processing circuit of the present invention is a circuit system in which a dedicated hardware macro is provided to perform data conversion processing separately from processing in a signal processing device. # & is proposed. Hereinafter, the data conversion processing circuit of the present invention will be explained using an example in which human data as shown in FIG. 1 is converted into 16 areas.

FIG. 2 shows the configuration of an embodiment of the data conversion processing circuit of the present invention. In the figure, 1 is a table that stores boundary values, and 2 is a table that stores converted values. register, 6
4 is a register that stores the number of successive approximations, 5 is a comparison circuit, 6 is a selector, 7 is an adder, and 8/I'i address register.

Figure 3 shows the order in which the boundary values in Table 1 shown in Figure 2 are stored.In the data conversion processing circuit of the present invention, by storing the boundary values in this order, , making it possible to reduce the scale of macro hardware. In addition, microcontrollers and digital signal processing devices (DS)
P) usually has a constant table area, so a part of it can be used as such a table.

In Figure 2, the boundary values are stored in Table 1 as shown in Figure 3, and then the values corresponding to the converted value, the start address of the table, and the number of successive approximations are stored in registers 2 and 3.4, respectively. do. The @number of successive approximations is when dividing into 16 areas.

If 16=2', then 24'-1-a is sufficient.

Address register 8 initially contains table 1 from register 3.
The start address of is stored. By successively supplying these addresses to table 1, the first boundary value, that is, the value of boundary 8 shown in FIG. 3 from table 1 is successively obtained. This value and the converted value read from register 2 are added to comparison circuit 5, and their magnitudes are compared. As a result, it is determined whether the converted value is in the region ① to @ or in the region ① to ① depending on whether the converted value is larger or smaller than the first boundary value.

The area where the current value to be converted is larger than the first boundary value ■~@
, the selector 6 selects the successive approximation count of the register 4, that is, “8” and inputs it to the adder 7, and the adder 7 adds “8” to the address read from the address register 8. The added value is sent to the address register 8 and its value is updated.

At the same time, the number of successive approximations in register 4 is set to "4"'. This is done by shifting the value of register 4 one bit to the left when the comparison value is selected as described above. As a result, the address of the 9th boundary value is output from address register 8 and given to table 1,
The ninth boundary value, that is, the value of boundary 12, is read from table 1, and this value and the converted value are compared in the ratio V@path 5, and whether the converted value is greater than the ninth boundary value or not. It is determined whether the converted value is in the region @ to @ or in the region ■ to ■ depending on whether the value is small or small.

The area where the converted value is larger than the 9th boundary value [phase] ~ @
, the selector 6 selects the successive approximation count of the register 4, that is, "4" and inputs it to the adder 7, and the adder 7 adds "4" to the address read from the address register 8. and sends it to the address register 8 to update its value. At the same time, the number of successive approximations in register 4 is set to "2". This allows address register 8
The address of the 13th boundary value is output from Table 1 and given to table 11/c, the 15th 9th boundary value, that is, the value of boundary 14 is read out from table 1, and this value and the value to be converted are sent to the comparison circuit. 5, and the converted value is the 13th
Depending on whether the value is larger or smaller than the th boundary value, it is determined whether the value to be converted is in the region ① to [phase] or in the region @ to @.

Also, the area where the converted value is smaller than the 9th boundary value
When it is determined that the
It is selected and input to the adder 7, and the force a calculator 7 adds "1" to the address read from the address register 8, and sends it to the address register 8 to update the value of Teso. As a result, the address of the 10th boundary value is output from address register 8 and given to table 1, and the 1Qth boundary value, that is, the value of boundary 10, is read from table 1, and this value and the value to be converted are Comparison circuit 5 compares at φ,
Depending on whether the converted value is larger or smaller than the 10th boundary value, it is determined whether the converted value is in the region @~[phase] or the range @~@.

On the other hand, the area where the converted value is smaller than the first boundary value
When it is determined that
1 is added to the address successively generated from , and the result is sent to the address register 8 to update its value. As a result, the address of the 182nd boundary value is output from address register 8 and sent to table 1, and the second boundary value, that is, the value of boundary 4, is read from table 1, and this value and the value to be converted are It is compared in the comparator circuit 5, and depending on whether the converted value is larger or smaller than the second boundary value,
It is determined whether the value to be converted is in the area (2) to (2) VC or in the area (2) to (2).

When it is determined that the value to be converted is larger than the second boundary value and is in the range ■ to ■, the selector 6 selects the number of successive approximations in the register 4, that is, "4T", and inputs it to the adder 7.
Adder 7 adds address K"4# read from address register 8 and sends it to address register 8 to update its value. At the same time, the number of successive approximations in register 4 is set to "2". As a result, the address of the sixth boundary value is output from address register 8, and table 1
is given to f, the sixth boundary value, that is, the value of boundary 6, is read from table 1, this value and the converted value are compared in the comparison circuit 5, and the converted value is read out from table 1. Depending on whether the value is larger or smaller than the boundary value, it is determined whether the value to be converted is in the region (1) to (2) or (2) to (2).

Also, the area where the converted value is smaller than the second boundary value
, the selector 6 selects "1" and inputs it to the adder 7, and the adder 7 selects "1" and inputs it to the address register 8.
1# is added to the address read from address register 8 and the value is updated. As a result, the address of the third boundary value is output from address register 8 and given to table 1. The third boundary value, that is, the value of boundary 2, is successively output from table 1, and this value and the converted value are compared in the comparator circuit 5, and the converted value is larger than the third boundary value. Depending on whether the value to be converted is small, it is determined whether the value to be converted is in the region (■) to (2) or whether the value (force) is in the region (2) to (2).

Thereafter, the same procedure is repeated until the value of the successive approximation register 4 becomes "0" in line 9. In the above example, the area determination is completed by performing the process four times.

In this way, it is possible to know the order in which regions the values to be converted belong to. Depending on the application, it may be necessary to convert that value into a value, but that value can be, for example, the center value of each area, and this value is often found by simple processing from the boundary values of the area, etc. .

Note that in Example h, the case where identification is performed for 16 areas was explained, but the number of areas can be expanded.1.
It goes without saying that φ is limited to this, but in general 2N□
These areas can be identified by N times of size comparison. In this case, the table that supplies the boundary values of each conversion area i is the boundary value T2N-+ used in the first size comparison.
is stored at address a, then 211 boundary values T2N-1+2"-27(2) + -"+ 2t"- are used in the &(2&≦N)th magnitude comparison.
” r (4-1) -(1) Money, just store it at the next address.

a+2(N-1)δ(1) +2(N-2)δ(2)
+,,,+21N-(A-1))δ(&-1)...Reason...(2) However, 11. (In formula 21.

Furthermore, in the embodiment, the table start address register and the boundary value storage table are shown separately for clarity of explanation, but they are actually the same. 'KFi various information such as hardware configuration, table address assignment method, etc.
However, basically all methods that use the concept of the present invention are included within the scope of the present invention.

In addition, it is most convenient for the number of regions to be a power of 2 (generally, there are many applications like this), but if this is not the case, the number of regions is p larger than the number of regions, and the minimum number is a power of 2. As such, a dummy area may be provided in the table.

As described in detail, the data conversion processing circuit of the present invention performs data conversion processing for converting a converted value into data representing one of the 'II number areas each having a different value to which it belongs. In the circuit, there is no need to perform software processing using the main calculation system of the signal processing circuit, and therefore it is possible to prevent a decrease in processing speed in the signal processing circuit.

[Brief explanation of drawings]

Figure 1 is a diagram illustrating an example of the data conversion process targeted by the present invention, Figure 2 is a diagram showing the configuration of an embodiment of the data conversion processing circuit of the present invention, and Figure 5 is the order in which boundary values are stored in a table. FIG.

Claims (1)

[Claims] In a data conversion processing circuit that converts a converted value into data indicating one of a plurality of areas each having a different value to which the converted value belongs, a table for storing boundary values of each conversion area and a reference address for the table are generated. A table reference register, a start address register that stores the start address of the table, a successive approximation count register that stores a value corresponding to the number of times to perform successive approximation, and a boundary value and a converted value obtained from the table. A comparator circuit that determines the magnitude by comparing the values, and a comparison circuit that selects an address obtained by adding 1 to the current address of the table or an address obtained by adding the value of the successive approximation count register to the current address according to the result of the judgment, and refers to the table. An address control circuit is provided that writes to the register and updates the value of the successive approximation count register, and reads each boundary value and the converted value from the boundary value stored at the top address of the table according to the address of the table reference register. A data conversion processing circuit characterized in that a region to which a value to be converted belongs is determined by successive comparison.