JP3092527B2 - Butterfly operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a butterfly operation circuit, and more particularly to a butterfly operation circuit used in a radix-2 time-decimating fast Fourier transform.

[0002]

2. Description of the Related Art Conventionally, real part data and imaginary part data have been used.
To convert Ranaru N complex data from the time domain to the frequency domain, it is known to use a decimation-in-time high-speed Fourier transform of the radix-2. The radix-2 time thinning-out fast Fourier transform is realized by repeatedly performing a basic operation called a well-known butterfly operation. The butterfly operation will be described with reference to the schematic diagram of FIG. 2. It is known that complex data X and Y, which are operation results for arbitrary input complex data x and y, are obtained as follows.

[0003] X = (x + W a · y) (1) Y = (x-W a · y) (2) In addition, (1), (2) where, ^{W a} is a twiddle factor, ^{W a} = Cos (2π · a / N) −j · sin (2π · a
/ N) (3) Further, a in the expressions (1) to (3) is a value shown in parentheses in a flowchart of FIG. 3 described later, and each of the butterfly operations of the radix-2 time-decimation type fast Fourier transform of N complex data is used. It is already known to determine the value of a at a stage.

Using the schematic diagram of FIG. 2, for example, for eight complex data (x1, x2,..., X8) in the time domain,
The butterfly operation of the radix-2 time-decimating fast Fourier transform is shown in the flowchart of FIG. 3, where the operation result of the input eight complex data (x1, x2,..., X8) is (X1, X2, ..., X8). As is already known, in the flowchart of FIG. 3, the interval between bcs composed of four butterfly operations is the first stage butterfly operation of the radix-2 time-decimating fast Fourier transform.

To realize the first-stage butterfly operation of the radix-2 time-decimating fast Fourier transform by hardware, first, as shown in FIG. 4, eight input complex data (x1, x2,..., x8) are stored in the input storage unit 1 controlled by the address generated by the input write address generation unit 2 in the order of input. The stored complex data is the real part data of this complex data,
The imaginary part data is data represented by, for example, L bits (L is a natural number) using a two's complement representation.

Next, after all the eight complex data to be inputted are stored in the input storage unit 1, an address for controlling the input storage unit 1 is generated by the address switching unit 4 and read by the address generation unit 3. Switch to address,
A data sequence (x1, x
2,. . . , X8), (x1, x2, x3, x
4) and the data up to (x5, x6, x7, x8) are output alternately.
Is output to

[0007] In the timing adjustment section 5, the continuous data string (x1, x5, x
2,. . . , X8) are taken out two by two in the order of output, and the data output earlier and the data output later are input to the butterfly operation unit 7 at the same timing.

[0008] Here, the first-stage butterfly operation time decimation type fast Fourier transform base 2, as shown in the flow diagram of Figure 3, the rotation factors W ^a butterfly operation are all W ^0. Therefore, the expression (3) becomes: W ⁰ = cos (2π · 0 / N) −j · sin (2π · 0 / N) = 1 (4) When W ⁰ = 1 is used, the expression (1) Equations (2) are as follows.

X = (x + y) (5) Y = (xy) (6) The butterfly operation unit 7 calculates the expressions (5) and (6) as shown in FIG. 9, and calculates two sets of real part data and imaginary part data sequentially input from the timing adjustment unit 5 of FIG. Output as the result of the first stage butterfly operation of the Fourier transform.

As described above, as an example of the conventional butterfly operation circuit, the first-stage butterfly operation of the eight radix-2 time-decimation type fast Fourier transform composed of time-domain complex data has been described. It is a well-known fact that the number N of complex data in the time domain to be transformed may be any natural number that is a power of two, and the number of butterfly operations in the first stage is N / 2. Also,
Regardless of the number N of complex data, the rotation factors W ^a of the first stage butterfly operation, it is also a well-known fact is all W ^0.

[0011]

As described above, it is known that the first-stage butterfly operation of the N radix-2 time-decimating fast Fourier transform of radix-2 is realized by hardware. However, the hardware configuration of this butterfly operation requires a complex adder / subtractor composed of the adder / subtractor 8 as shown in FIG.
The circuit scale also increases. Furthermore, in this complex adder / subtractor, the longer the bit length to be operated, the longer the operation time and the circuit scale, which hinders the butterfly operation by hardware.

The present invention has been made in view of the above points,
An object of the present invention is to provide a butterfly operation circuit capable of performing a butterfly operation at high speed without using a complex adder / subtractor.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a ^2M data comprising real part data and imaginary part data.
(Where M is a natural number) In the butterfly operation circuit that performs the first stage butterfly operation of the radix-2 time-decimating fast Fourier transform on the type of complex data , the M bits corresponding to ^2M types of complex data Memorize the data of
An input storage unit to be read out, and N pieces of M-bit data (where N is a natural number of a power of 2) stored in the input storage unit in the order of input, and then N / 2 data in the first half of the N storage data Writing / reading means for alternately reading the latter N / 2 data, and a timing adjusting unit for simultaneously reading two consecutive data out of the data read from the input storage unit at the same timing as 2M bits; ,
Of 2 ^M types of complex data, as input to any two complex data, time radix-2 decimation-type fast Fourier transform
A combination of two ^22M kinds of complex data existing as an operation result when the first-stage butterfly operation is performed is stored in advance and output from the timing adjustment unit.
With 2M bits, in which one combination of a combination of 2 ^2M kinds of two complex data is composed of a Starring <br/> calculation data storage unit you Outputs selected.

Conventionally, when 2 ^M kinds of complex data that can be represented by M bits are subjected to a first-stage butterfly operation of a radix-2 time-decimating fast Fourier transform, complex data to be subjected to a fast Fourier transform is represented by L The real part data and the imaginary part data of a binary number represented by bits (L is a natural number) are represented by binary number real time data and imaginary part data. It was output as the result of the first stage butterfly operation of the fast Fourier transform.

On the other hand, according to the present invention, N pieces of ^2M kinds of complex data to be subjected to fast Fourier transform are stored in the input storage section as corresponding M bits in the input storage section. And the N / 2 data in the latter half are alternately read and input to the timing adjustment unit. Here, two data are extracted in the order of input, and the data input earlier and the data input later are the same. The data is output to the operation data storage unit in accordance with the timing. In the operation data storage unit, 2 ^M combinations represented by M bits are applied to 2 ^M kinds of L-bit complex data to obtain 2 ^{M combinations.}
Any two of the types of L-bit complex data are input and
When a radix-2 butterfly operation is performed when the value of the twiddle factor is "1", a combination of ^22M kinds of two L-bit complex data existing as an operation result is stored in advance, 2M output simultaneously from the adjustment unit
A combination of stored complex data is selected from ^22M combinations represented by bits, and is output as a first-stage butterfly operation result of a butterfly operation of a radix-2 time-decimating fast Fourier transform.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a butterfly operation circuit according to the present invention. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals. Embodiment shown in FIG. 1, the input memory unit 1, an input write address generator 2, an input read address generator 3, the address switching unit 4 is configured from the timing adjusting unit 5 and the calculation data storage section 6. In this embodiment, 1024 (= 2 ¹⁰ ) data strings (x1, x2) of 2-bit digital signals are used.
2,. . . , X1024), and outputs the result as a first-stage butterfly operation result (X1, X2,..., X1024) of the radix-2 time-decimating fast Fourier transform.

In FIG. 1, a 2-bit data string (x1, x2,..., X102)
4) is data indicating which of the four types of complex data to be subjected to the fast Fourier transform, which is generated by the input write address generation unit 2 and input to the input storage unit 1 via the address switching unit 4 Are stored in the order of input. When 1024 data (x1, x2,..., X1024) are stored in the input storage section 1, the address switching section 4 switches the read address generated by the input read address generation section 3 subsequently. Select and input to the input storage unit 1. According to the read address, the input storage unit 1 converts the stored data string (x1, x2,..., X1024) into the first half (x1
1, x2,. . . , X512) and the second half of (x512)
513, x514,. . . , X1024) are output alternately as shown in FIG.

As shown in FIGS. 6 and 7A, a 2-bit continuous data string (x1, x2) output from the input storage unit 1 is output.
513, x2, x514,. . . , X512, x102
4) is input to the timing adjustment unit 5 of FIG. 1 and is extracted two by two in the order of data input.
As shown in (B), the time timing is adjusted so that the first-half data input first and the second-half data input later have the same timing.

From the timing adjustment unit 5Two by twosame
Sometimes taken out2 bits each, total4-bit data
Is the operation data storage unitTo 6SuppliedYou. And the operation data
The data storage unit 6 stores operation data corresponding to the input 4 bits.
Base 2 decimated time stored in data storage unit 6
Result of the first stage butterfly operation of the fast Fourier transform
And outputs two complex data. Note that complex data
Data consists of real part data and imaginary part data.
In FIG. 1, for example, each 10-bit real part data
Data consisting of data and imaginary part data
You. Further, the complex data stored in the operation data storage unit 6 is stored.
Data from the four types of complex dataAny twotype
(May be the same type)If, The twiddle factor
When the value is "1", that is, the time-decimated height in base 2
When the first stage butterfly operation of the fast Fourier transform is performed
ComeExistExist,total16Set (one set is two complex data)
Is stored. Therefore,Timing adjustment
Part 52-bit data taken out two at a time from
Is 4 bits, and 16 types can be selected.
From the 16 sets of performances stored in the operation data storage unit 6.
Perform an operation by selecting one set from the calculation results
WithoutFirst stage of radix-2 time-decimated fast Fourier transform
Result of butterfly operationCan get.

As described above, in this embodiment, 2 ^M (here, M = 2) types of complex data to be subjected to fast Fourier transform are input as 2 (= M) bits corresponding to the four types of complex data. Are stored in the input storage unit 1. On the other hand, when arbitrary two complex data of the four types of complex data are input and a radix-2 butterfly operation is performed when the value of the twiddle factor is "1", 16 (= 2) ^2M )
A combination of two types of complex data is stored in the operation data storage unit 6 in advance.

Then, from the combination of the 16 types of two complex data stored in the operation data storage unit 6, two 2-bit data input from the timing adjustment unit 5 to the operation data storage unit 6 4 (= 2M) expressed by
Since one combination is selected according to the bits and the result is output as the first-stage butterfly operation result of the radix-2 time-decimating fast Fourier transform, the first stage of the radix-2 time-decimating fast Fourier transform is performed. This eliminates the need for a complex data signal line and a complex adder / subtractor that are input to the eye butterfly operation.

[0023]

As described above, according to the present invention,
N pieces of 2 ^M kinds of complex data to be subjected to fast Fourier transform are stored in the input storage section as corresponding M bits in the input storage section, and the N / 2 pieces of data in the first half and the N / 2 pieces in the second half are written and read therefrom by writing / reading means. type DOO timing adjustment unit reads alternately, the calculation data storage section is represented by M bits, fitting of 2 ^M number of combinations to 2 ^M kinds of L-bit complex data, 2 ^M kinds of L bits When inputting any two pieces of complex data of, and performing a radix-2 butterfly operation when the value of the twiddle factor is “1”, two L bits of 2 ^2M types existing as an operation result A combination of complex data is stored in advance, and a combination of stored complex data is selected from ^22M combinations expressed by 2M bits output simultaneously from the timing adjustment unit,
Since the result is output as the first-stage butterfly operation result of the radix-2 time-decimated fast Fourier transform butterfly operation, the complex input to the first-stage radix-2 time-decimated fast Fourier transform butterfly operation is output. The number of data signal lines can be reduced, and a complex adder / subtracter that takes a long time to perform arithmetic processing by hardware can be omitted. Therefore, the first stage butterfly operation of the radix-2 time-decimating fast Fourier transform can be performed at high speed. And the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of a butterfly operation of a radix-2 time thinning-out fast Fourier transform.

FIG. 3 is a flowchart of a butterfly operation of a radix-2 time-decimating fast Fourier transform of eight complex data.

FIG. 4 is a block diagram of an example of the related art.

FIG. 5 is a block diagram of a first stage of the butterfly operation unit in FIG. 4;

FIG. 6 is a diagram illustrating an order of data input to a timing adjustment unit in FIG. 1;

FIG. 7 is a timing chart showing a relationship between input and output data of the timing adjustment unit in FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 input storage unit 2 input write address generation unit 3 input read address generation unit 4 address switching unit 5 timing adjustment unit 6 operation data storage unit

Claims (2)

(57) [Claims] 1. A system comprising real part data and imaginary part data.
^A butterfly operation circuit that performs a first-stage butterfly operation of a radix-2 time-decimation type fast Fourier transform on ^M (where M is a natural number) types of complex data corresponds to the ^2M types of complex data . An input storage unit for storing and reading M-bit data; and storing the M-bit data in the input storage unit in N input order (where N is a natural number of a power of 2).
Writing / reading means for alternately reading the first half N / 2 data and the second half N / 2 data of the N pieces of storage data; the data and the timing adjustment section for reading a 2M bits simultaneously in the same timing, the 2 ^M types of complex data, as input to any two complex data, the radix-2 decimation-in-time high-speed Fourier
A combination of ^22M types of two complex data which is present as a calculation result when the first-stage butterfly calculation of the conversion is performed is stored in advance, and the 2M bits output from the timing adjustment unit are used to store the combination. 2 One combination is selected from the combination of ^2M kinds of two complex data.
Butterfly operation circuit and having a arithmetic data storage unit you output is. 2. The writing / reading means stores an address of the input storage unit such that the input storage unit stores the M-bit data in N input order (where N is a natural number of a power of 2). An input write address generating unit to be controlled; and the N input data stored in the input storage unit, so that N / 2 data of the first half and N / 2 data of the second half are alternately read. An input read address generator for controlling an address of the storage unit; and an address switching unit for switching the input signal generated by the input write address generator and the address signal generated by the input read address generator and inputting the signal to the input storage unit. The butterfly operation circuit according to claim 1, wherein: