JP3087488B2 - Data restoration circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data restoring circuit for restoring data at a high speed when transferring compressed data to reduce the memory capacity while transferring the data in a test system. .

[0002]

2. Description of the Related Art First, a method of compressing compressed data to be expanded will be described. Check whether the data at a certain address matches the data at the previous address. If they match, 0 is set in the control data, indicating that the data matches the previous data, and the data is not included in the compressed data. . If they do not match, 1 is set in the control data, the data is not compressed, and the data is treated as data accompanying 1 of the control data. That is, the same data is not made to exist continuously, and the data amount is reduced. Also, compressed data is created by repeating control data and data accompanying it. There are several methods for creating decompressed compressed data, which are due to differences in the method of comparing data at each address.

Some compression methods are shown in FIG. In the first compression method, the data at each address is compared with the data at the one address, a match is obtained, and control data is created. Also, one of the first control data
The bit is a bit indicating the presence / absence of data at the 0th address (the first address) of the data to be compressed. If there is data, 1 is set in the control data, and the accompanying data continues below the control data. If there is no, that is, if the data is all bits 0, 0 is set in the control data, indicating that the first address of the data is all bits 0.

In the compression method 2, control data is created by comparing the data at each address with the data on the two addresses to obtain a match. The first and second bits of the first control data are bits indicating the presence / absence of the data of the 0th and 1st addresses of the data to be compressed. If the data to be written continues below the control data, and there is no data, that is, if the data is all bits 0, 0 is set in the control data, indicating that the data of the address corresponding to the bit where 0 is set is all 0s. .

Similarly, in the compression method 3, control data is created by comparing the data at each address with the data on the three addresses and obtaining a match, and the first control data 1, 1 The second and third bits indicate the presence or absence of data at the address corresponding to the bit. Also, the compression method 4 and the subsequent compression methods are considered in the same manner.

By the way, as shown in FIG. 3, a possible compression method is to compare the data at each address with the data on its N (N is an integer) address and create control data by obtaining a match. Depending on the data volume of the data to be compressed, a huge variety of compression methods can be considered. However, in practice, how many compression methods are used is determined by the number of bits of one control data, that is, the data width of the computer used in the test system.

For example, in the case of a test system using a computer having an 8-bit CPU, the number of bits of control data is 8 bits. The compression method is as shown in FIG. A compression method 1 for comparing data with data, a compression method 2 for comparing data with two addresses, a compression method 4 for comparing data with four addresses, and a compression method 8 for comparing data with eight addresses Is limited to a total of four types.

Similarly, in a test system using a computer having a 16-bit CPU, the number of control data bits is 16 bits, and the compression method is 8 bits.
In addition to the compression method for the bit control data, a method for comparing with the data on 16 addresses is added, and the total is limited to 5 types. In other words, a compression method using only a submultiple of the data width of the computer can be considered.

Next, expansion of compressed data will be described with reference to FIGS. FIG. 5 is an explanatory diagram of a data flow showing a conventional method of decompressing compressed data by software. The compressed data in the compressed data storage unit 19 is distributed to a plurality of memories 20 while being expanded by software. Note that the distribution destination in the plurality of memories 20 is determined by the compression method.

FIG. 6 shows a compression method 1, that is, a case where data is compressed by comparison with data on one address. Data after expansion is stored in a in a plurality of memories 20. FIG.
Shows a compression method 2, that is, a case in which data is compressed by comparison with data on two addresses. The data after expansion is distributed to a and b in a plurality of memories 20 and stored. FIG. 8 shows a compression method 3, that is, a case where data is compressed by comparison with data on three addresses. The data after expansion is sorted into a, b, and c in a plurality of memories 20 and stored. For decompression of compressed data using the following compression methods,
It is distributed to more memories 20.

[0011]

In the conventional test system, the data is decompressed by software in order to decompress the data compressed as described above. Therefore, the operation of decompressing the data, transferring and decompressing the data is performed. It takes time.

The present invention comprises a circuit for outputting decompressed data of compressed data and a memory with a buffer for taking in the decompressed data. It is an object to provide a data restoration circuit for restoring.

[0013]

According to the present invention, compressed data consisting of control data and accompanying data stored in a compressed data storage unit 1 is expanded and decompressed by a compressed data decompression circuit 3, and the decompressed data is decoded. In the data decompression circuit stored in the memory 4, the compressed data decompression circuit 3 inputs a control circuit 12 for outputting various control signals for decompression processing of the compressed data, and a compressed data signal and its address signal. An address pointer 9 which counts an address value in response to a development start / stop signal from the control circuit 12 and an output signal and an address signal from the address pointer 9 are inputted, and are switched in response to a selector switching signal from the control circuit 12. And a compressed data signal as a data input, and an output signal of the selector 10 as an address input. A memory 11 for temporarily storing the compressed data, and a control signal included in the compressed data in response to a data fetch signal from the control circuit 12 to fetch and decode the control data in the compressed data, A data address generating circuit 13 for generating a write signal.

[0014]

According to the present invention, a compressed data expanding circuit 3 for expanding compressed data includes an address pointer 9, a selector 1
0, the memory 11, the control circuit 12, and the data address generation circuit 13 are all realized as hardware as shown in FIG.

Therefore, data development is performed on hardware by various signals A to J shown in the circuit of FIG. 1 changing according to timing waveforms as shown in FIG.

[0016]

Next, an embodiment of a data restoration circuit according to the present invention will be described with reference to FIGS. In FIG. 2, 1 is a compressed data storage unit, 2 is a computer for control in a test system, 3 is a compressed data expansion circuit, and 4 is a buffered memory including a buffer unit 5 and a memory unit 6. FIG. 1 is a configuration diagram of the compressed data expansion circuit 3, in which 7 is a data input / output pin, 8 is an address input pin, 9 is an address pointer for counting up, 10 is a selector, 11 is a memory, 12
Is a control circuit, 13 is a data address generation circuit including a data storage unit 14, a bit search unit 15, and a data address generation unit 16, 17 is an output data buffer, 18 is a development data output pin, and 19 is an address output pin.

Symbols A to J in FIG. 1 indicate various signals in the circuit, and their timing waveforms are shown in FIG.

A is an expansion start / stop signal, B is an address signal, C is a data signal, D is a control take-in signal, E is a control data signal, F is a data address signal, G is a write signal, and H is a data clock. Signal, I
Represents an output data signal, and J represents an output signal.

The storage of the compressed data in the memory 11 and the setting of the address pointer 9 and the control circuit 12 are performed by the input from the data input / output pin 7 and the address input pin 8. When storing the compressed data in the memory 11, the selector 10 selects the address from the address input pin 8.
Thereafter, the count-up of the address pointer 9 starts by the expansion start signal A from the control circuit 12, and the expansion starts. At this time, the selector 10 changes the signal from the address pointer 9 to the address signal of the memory 11 by the selector switching signal. Select as

The control data in the compressed data is stored in a data storage section 14 in a data address generation circuit 13 by a data fetch signal, and the control data is decoded by a bit search section 15 by a data address generation clock. The data address generation unit 16 generates a data address signal F and a write signal G of data accompanying the control data read from the memory.

The decoding of the control data is performed by detecting a bit in which 1 is set in the control data and sending the bit to the data address generator 16 as information for generating the data address signal F and the write signal G. When the decoding of one control data is completed, the control data fetch request signal D is generated from the bit search unit 15 and the control data output from the memory 11 is stored in the data storage unit 14 again.

The data address signal H generated in this manner becomes an address signal for selecting the buffered memory 4 to be stored after the decompressed data is output from the compressed data decompression circuit 3, and the write signal G is a transfer signal from the buffer unit 5 in the buffered memory 4 to the memory unit 6. The number of times the write signal G is output varies depending on the compression method. For example, if there is data that has been compressed by comparison with data on two addresses as shown in FIG. That is, the write signal G is output to two memories with buffers, and one write signal is output for two bits of control data. If the compression mode is 3, control data 3
A write signal G of one signal is output for each bit.

The difference between these outputs is set in the control circuit 12 in advance, and the data generated from the data address generator 16 changes according to the mode signal from the control circuit 12. These data address signal F and write signal G are
It is output from the address output pin 19. Data accompanying the control data read from the memory 11 is taken into the output buffer 17 by the data clock,
It is output from the expansion data output pin 18. However, when a write signal is generated, no data clock is generated, and the previous data is held in the output data buffer 17. Similarly, the data address retains the previous data by the data address generator 16.

FIG. 9 shows the data width of 8 bits and the compression method 4
10 is a time chart showing the expansion of the data compressed in FIG.

[0025]

According to the present invention, since the decompression of compressed data by software is performed by hardware, the time for decompressing compressed data can be shortened.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a compressed data expansion circuit according to the present invention.

FIG. 2 is a configuration diagram of a data restoration circuit according to the present invention.

FIG. 3 is a diagram illustrating an example of data compression.

FIG. 4 is a diagram illustrating a compression method for 8-bit control data.

FIG. 5 is a diagram illustrating a data restoration method according to the related art.

FIG. 6 is a development view of compressed data according to a compression method 1;

FIG. 7 is a development view of compressed data according to a compression method 2;

FIG. 8 is a development view of compressed data according to a compression method 3;

FIG. 9 is a time chart showing a state of data expansion according to an embodiment of the present invention.

FIG. 10 is a data restoration diagram showing data restored by the operation of FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Compressed data storage part 2 Computer 3 Compressed data expansion circuit 4 Memory with buffer 5 Buffer part 6 Memory part 7 Compressed data input pin 8 Address input pin 9 Address pointer 10 Selector 11 Memory 12 Control circuit 13 Data address generation circuit 17 Output data buffer 18 Data output pin 19 Address output pin

Claims (1)

(57) [Claims] A compressed data expansion circuit (3) decompresses and decompresses compressed data comprising control data and accompanying data stored in a compressed data storage section (1), and stores the decompressed data in a memory (4). In a data decompression circuit for storing compressed data, a compressed data decompression circuit (3) inputs a control circuit (12) for outputting various control signals for decompression processing of compressed data, a compressed data signal and its address signal, An address pointer (9) for counting an address value in response to a development start / stop signal from the control circuit (12), an output signal from the address pointer (9) and the address signal, and a control circuit ( A selector (10) that outputs one of the switches in response to a selector switching signal from (12), a compressed data signal as a data input, and an output signal of the selector (10) as an address input and the compressed data as (11), and in response to a data fetch signal from a control circuit (12), fetches and decodes control data in the compressed data from the memory (11) and decodes the control data from the memory (11). A data restoration circuit comprising: a data address of a read associated data and a data address generation circuit (13) for generating a write signal.