JP3336537B2 - Encoding device, decoding device, encoding / decoding device, and arithmetic encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data conversion technology for performing a predetermined conversion process on data relating to an image, and more particularly, to encoding and decoding using a static information table.
The present invention relates to an image data conversion processing method and apparatus for performing predetermined conversion processing such as decoding.

[0002]

BACKGROUND OF THE INVENTION Various image conversion processes are performed to make image information recognized by human vision recognizable by a machine such as a computer. For example, when transmitting image information via a transmission medium such as a telephone line or a radio wave, the transmitting side compresses image data to be transmitted in order to reduce the amount of information of the image to be transmitted, and the receiving side performs the compression. A technique of expanding compressed data is generally used. FIG. 15 conceptually shows how image data is transmitted. The image data supplied from the image information source is encoded by the encoding device 10 on the transmission side, and
Transmitted by The encoded data transmitted to the receiving side is decoded by the decoding device 14 into original image data.

In image data conversion processing such as encoding and decoding, a plurality of conversion parameters may be stored in a static information table in advance. That is, when performing conversion processing of input image data, a conversion parameter corresponding to the image data is read from the information table,
The conversion processing of the image data is performed using the read conversion parameters. In such conversion processing, there is an adaptive conversion processing method in which conversion parameters for the same image data are changed based on the statistical properties of the image so as to match the local properties at that time.

[0004]

2. Description of the Related Art FIG. 16 shows a conventional image coding apparatus employing an adaptive arithmetic coding system as an example of an image data conversion processing apparatus. Here, arithmetic coding means that a probability number line is divided into sections according to the appearance probability of a symbol sequence to be coded, and a binary decimal value indicating a position in the divided section is a code for the sequence. In this case, codewords are sequentially formed by arithmetic operations. Such an arithmetic coding method is particularly applied to the transmission and reception of binary images by facsimile.

The image encoding apparatus shown in FIG. 16 includes a symbol sequence reading section 100 for inputting input image data as a binary symbol sequence, and a symbol sequence for storing the binary symbol sequence read by the symbol sequence reading section 100. In order to compress the binary symbol sequence stored in the symbol sequence storage unit 102, the storage unit 102 and the symbol pattern most closely correlated with the encoding target symbol to be compressed (hereinafter, referred to as “ Image reference symbol selection unit 104 for selecting a “template” from a binary symbol sequence. A state number / dominant symbol storage unit 10 for storing data having the contents shown in FIG.
6 and a value indicated by the content of the reference symbol extracted by the image reference symbol selection unit 104 (hereinafter referred to as “context”).
Alternatively, whether the symbol to be encoded is equal to the estimated value (symbol value that appears with a high probability, dominant symbol “MPS”) stored in the state number / dominant symbol storage unit 106 based on “CX”). And a prediction conversion processing unit 108 that outputs such information.

In FIG. 16, reference numeral 110 denotes a probability estimation table that stores a predetermined probability area size (LSZ) of the inferior symbol LPS and transition information of the state number ST for each state number. Reference numeral 112 denotes the output of the prediction conversion processing unit 108 and the state number / dominant symbol storage unit 1
06, the state number ST and the MPS value read from the probability estimation table 110, and the inferior symbol LP read from the probability estimation table 110.
An arithmetic encoding unit that performs an arithmetic encoding process on the encoding target symbol based on the value (LSZ) of the appearance probability area width of S and the state transition information.

When the binary arithmetic coding process is performed by the above-described device, first, the entire binary arithmetic coding device is initialized. That is, the state number (ST) and the value of the dominant symbol MPS stored in the state number / dominant symbol storage unit 106 are set to zero for all contexts CX.

Next, the width of the MPS area of the probability area indicated by the section register (not shown) is set to 10000 Hex.
, The lower limit of the width A of the MPS area in the probability area indicated by the sign register (not shown) is set to 0, and a counter for counting the number of shifts for sign output (hereinafter referred to as “CT”) ) Is set to 11. next,
The image reference symbol selection unit 104 uses the above-described template to store the encoding target symbol and the context for encoding in the symbol sequence storage unit 102.
Load from the value symbol sequence.

Next, a binary arithmetic coding process is started. First, in the predictive conversion processing unit 108, the value of the symbol to be encoded and the state symbol corresponding to the context CX / the superior symbol MPS stored in the superior symbol storage unit 106
(Hereinafter referred to as “MPS (CX)”).
If the value of the encoding target symbol is equal to MPS (CX), the encoding target symbol is a dominant symbol MPS.

The symbol to be coded is the dominant symbol MPS
In the binary arithmetic coding unit 112, the current state of the context CX is set to ST (CX), and the area width allocated to the inferior symbol LPS in the state ST (CX) is set to LSZ (ST (CX )), The area width allocated to the dominant symbol MPS is calculated as A-LSZ (ST (CX)) (see FIG. 18). Then, the probability area width A corresponding to the appearance probabilities of the symbol strings encoded up to now is divided by the expected inferiority symbol LPS and the estimated occurrence probability of the superiority symbol MPS expected for the next symbol to be encoded. If the estimated occurrence probability of the symbol MPS is equal to or greater than the occurrence probability of the inferior symbol LPS, the region of the superior symbol MPS in the probability region in FIG. 18 is assigned to the encoding target symbol.

In FIG. 18, the value indicating the size of the probability region in which the symbol to be coded appears is the value of A ′, so that the dominant symbol MPS appears as the symbol to be coded by calculating A-LSZ. The probability region width to be assigned in the case can be obtained. Next, the value of the probability region width assigned when the dominant symbol MPS appears is 8000H indicated by Half in FIG.
ex, the process is terminated if it is 8000 Hex or more, and normalization is performed if it is less than 8000 Hex.

As a pre-process for performing the normalization processing, when the value of A-LSZ indicating the width of the probability region to be allocated when the dominant symbol MPS appears as the encoding target symbol and the inferior symbol LPS appears as the encoding target symbol Is compared with the width LSZ of the probability region assigned to A-LS
If the value of Z is smaller than the value of LSZ, the superior symbol MPS and the inferior symbol LPS
A process (conditional exchange process) for exchanging the meaning of the probability region assigned to is performed (see FIG. 19).

Next, the value indicated by ST (CX), that is, the next transition state of the state number ST corresponding to the context CX (hereinafter referred to as “NMPS (ST (CX))”) is stored in the probability estimation table 110. From the current ST
A process of updating the value of (CX) is performed. At this time, when the encoding target symbol is the superior symbol MPS, the “probability region width assigned to the inferior symbol LPS” LSZ in the next state is always smaller than the LSZ in the current state. Is set.
For example, when only the encoding target symbol MPS is generated, as shown in FIG. 20, when the LPS area width is large, (1), (2), and (3) are used when the encoding process is performed three times. One normalization has occurred, and a 1-bit code has been output. On the other hand, as shown in FIG. 21, when the LPS area width is small, normalization occurs once when the encoding target symbol is encoded in 6 bits, and a 1-bit code is output. That is, in the former case (FIG. 20), the compression ratio is 1/3, in the latter case (FIG. 21), the compression ratio is 1/6, and when the dominant symbol MPS is continuously generated, The smaller the LPS area width, the better the compression ratio. That is, when the dominant symbol MPS occurs, the smaller the value of LSZ, the smaller the number of times the normalization processing is performed for the same input data amount, and the smaller the number of codes output by one normalization processing.

Next, returning to FIG. 19, the normalization processing procedure will be described. In the normalization processing, the probability region of the dominant symbol MPS smaller than 8000 Hex is set to 8000
A process for making the value larger than Hex is performed. That is, an interval register indicating the width of the probability region assigned to the symbol sequence encoded to date and the coordinates representing the probability region assigned to the symbol sequence encoded to date are indicated. By shifting the value of the sign register in the most significant bit direction (MSB direction) in each register, a process of enlarging each area and coordinates by two times is performed.

8000 Hex is a value of １ ／ of the maximum area width on a number line that can be taken by the section register. This indicates that the value of the most significant 1-bit in the code register indicating the coordinates representing the probability area assigned to the symbol sequence is determined on a number line. During the shift in the normalization processing, codes are output sequentially from the most significant bit of the code register. The output timing of the code is counted by the counter CT, and when 8 bits of the output code are accumulated, CT becomes zero and the code is output in byte units.

Next, a description will be given of a binary arithmetic encoding procedure when the encoding target symbol is the inferior symbol LPS. The difference from the processing in the case where the encoding target symbol is MPS is that the probability estimation table 110 has a processing of checking a bit called a predetermined switch bit, and that when the inferior symbol LPS occurs, That the normalization process needs to be performed and the update of the value of ST (CX) accompanying the normalization process are performed by the superior symbol MP
When S occurs, LSZ (ST (CX)) is updated in a direction to decrease, whereas the inferior symbol LPS is updated.
Is to be updated in the direction in which LSZ (ST (CX)) increases.

The switch bit indicates the state number / dominant symbol storage section 106 when the inferior symbol LPS appears.
Symbol MPS and LPS LPS stored in
It is necessary to perform the process of replacing the value of. The process of exchanging the superior symbol MPS and the inferior symbol LPS is used to increase the coding efficiency. That is, the value of the dominant symbol MPS stored in the state number / dominant symbol storage unit 106 in the initialization processing of the encoding device is cleared to zero as an initial value, and 1 is appropriately set as the value of the dominant symbol MPS for a certain context. In the binary symbol sequence, the value of the dominant symbol MPS changes such that 1 is appropriate as the value of the dominant symbol MPS in a certain portion and 0 is appropriate in a certain portion. Case, dominant symbol MPS
And the value of the less-probable-symbol LPS are changed according to the change in the characteristics of the binary symbol sequence, thereby improving the coding efficiency. The reason why the normalization process is always performed when the inferior symbol LPS occurs is that the value of the inferior symbol LPS, that is, the value of LSZ (ST (CX)) is always set to a value smaller than 8000Hex, and the inferior symbol LPS appears. In this case, the value of the section register must be 8000 Hex
It is because it becomes smaller than the above.

When normalization is performed using the superior symbol MPS, the state is updated in the direction in which LSZ (ST (CX)) decreases, whereas the inferior symbol LPS is updated.
LSZ (ST (C
The reason why the state is updated in the direction of increasing X)) is as follows. That is, as shown in FIGS. 22 and 23, when the area width allocated to the inferior symbol LPS is small, the code amount (shift) output in one normalization process in the register shift process in the normalization process Number of operations). On the other hand, the inferior symbol L
When the area width allocated to the PS area width is large, the number of register shift operations in the normalization processing due to the appearance of the inferior symbol LPS decreases. In a certain context, when a symbol determined to be the inferior symbol LPS appears, if the LPS region width is assigned with the same estimated probability as before, the encoding is performed when the next inferior symbol LPS appears. Efficiency decreases. Therefore, even if a more inferior symbol LPS appears, state transition is performed in a direction in which LSZ (ST (CX)) increases so as not to output many codes. In the case where a change occurs in the characteristics of the symbol sequence to be encoded on the way, for example, when a photographic image is included in a facsimile image in which characters are described, the inferior symbol LPS frequently occurs. It is necessary to follow the state transition so as to follow the change in the characteristic. Thus, the compression ratio is improved by appropriately selecting the probability region to be assigned to the inferior symbol LPS according to the state transition.

FIG. 24 shows a configuration of a binary arithmetic decoding device for decoding a binary symbol sequence encoded by the binary arithmetic coding device in the prior art. In FIG. 24, the probability estimation table 130 indicates which optimal probability area is to be allocated to the inferior symbol LPS in each state of the context, and which state number ST is a state transition destination when normalization occurs. This is a table created by statistically determining whether it is appropriate or not, and is the same as the probability estimation table 120 of the encoding device shown in FIG. The state number / dominant symbol storage unit 132 is a storage device having the same format and data as the state number / dominant symbol storage unit 106 in the encoding device. The symbol sequence storage unit 133 stores the decoded binary symbol sequence output from the inverse prediction conversion processing unit 136.

The image reference symbol selection unit 134 selects a reference symbol from the decoded binary symbol sequence stored in the symbol sequence storage unit 133 according to the same template as that of the encoding device. Inverse prediction conversion processing unit 136
Is determined from the information indicating whether the dominant symbol MPS value read from the state number / dominant symbol storage unit 132 and the decoding target symbol obtained by the arithmetic decoding unit 138 are the dominant symbol MPS or the inferior symbol LPS, Output a value symbol sequence. Arithmetic decoding section 138 includes code data, state number and MPS value read from state number / dominant symbol storage section 132, value of occurrence probability area width of inferior symbol LPS read from probability estimation table 130, and state transition information. , Outputs whether the decoding target symbol is the superior symbol MPS or the inferior symbol LPS in the context, and executes the state transition to update the state number / dominant symbol storage unit 132.

Next, in the binary arithmetic decoding device, 2
The processing procedure of the value arithmetic decoding will be described. First, in order to initialize the entire binary arithmetic decoding device, the state number /
The transition state for each context stored in the superior symbol storage unit 132 and the value of the superior symbol MPS are set to zero for all contexts. next,
Lower bound value of the MPS area of the probability area (representative coordinates of the probability area)
Is set to zero and the sign is set in the sign register on a byte-by-byte basis. After that, the sign register is set in the most significant bit direction (MSB direction).
By repeating the operation of shifting by 8 bits three times, the initialization of the code register is completed. Subsequently, 10000 Hex (maximum probability area width) is set in a section register (not shown) indicating the probability area of the dominant symbol MPS, and the initialization processing of the decoding device is completed.

Next, the image reference symbol selection unit 134 selects a reference symbol using the same template as that of the encoding device, and generates a context for decoding. Next, when performing the binary arithmetic decoding process in the arithmetic decoding unit 138, the image reference symbol selecting unit 134
Based on each of the output contexts, the state number ST corresponding to the context is read from the state number / dominant symbol storage unit 132. Next, the width LSZ of the probability region corresponding to the read state number ST is read from the probability estimation table 130, and the width LSZ of the probability region is supplied to the arithmetic decoding unit 138. The arithmetic decoding unit 138 subtracts the value of LSZ supplied from the probability estimation table 130 from the section register.

Next, the value of the section register after the subtraction processing is compared with the contents of the 16 bits (CHIGH) on the MSB side of the sign register. In the section register, the area width divided by the decoded symbols up to the present is expanded by the already decoded symbols. That is, the section register contains a value expanded by the number of shifts. 16 bits on the MSB side of the sign register (CHIG
H) includes, among coordinate information (lower-bound coordinates) representative of a probability region assigned to a symbol sequence to be encoded,
The value obtained by subtracting the lower bound coordinate of the area assigned to the already decoded symbol from the approximate value of the coordinate excluding the code not yet input (the lower bound coordinate is completed when all codes are input to the decoder) Are given the same enlargement as the interval register and are held. The section register is divided by the estimated area width for the next symbol to be decoded, and the CHI
Decoding is performed depending on whether the GH register belongs to the dominant symbol MPS or the inferior symbol LPS from the boundary of the divided area. That is, A-
The decoding process is performed by comparing the magnitude of LSZ (ST (CX)) and CHIGH.

The symbol to be decoded is the dominant symbol MPS
If the width of the section register is 8000 Hex or more, the process is continued to the inverse prediction conversion processing unit 136, and
If the value is smaller than 00 Hex, a conditional exchange process of the dominant symbol MPS is performed, a normalization process is performed, and the process continues to the inverse prediction conversion processing unit 136. On the other hand, when the decoding target symbol is the inferior symbol LPS, the normalization process is always performed as in the case of the encoding process, and the process is continued to the inverse prediction conversion processing unit 136.

The normalization processing procedure in the binary arithmetic decoding device is exactly the same as the normalization processing procedure in the binary arithmetic coding processing shown in FIG. Regardless of the encoding / decoding processing, in the normalization processing, the values of the section register and the code register are shifted in the most significant bit direction (MSB direction) in the register, and the contents of the section register smaller than 8000 Hex are read from 8000 Hex. If the code in the code register is insufficient, the next code is read into the code register and decoding is continued.

Next, the operation of the inverse prediction conversion processing section 136 will be described. Using the context output from the image reference symbol selection unit 134, the arithmetic decoding unit 138 extracts the MPS value corresponding to the context from the state number / dominant symbol storage unit 132, and performs an inverse prediction conversion processing unit 136.
To supply. In the inverse prediction conversion processing section 136, MPS / L output from the binary arithmetic decoding section 138 and indicating whether “the decoded symbol is the superior symbol MPS or the inferior symbol LPS”
By comparing the PS information with the MPS value supplied from the state number / dominant symbol storage unit 132, a symbol before encoding is obtained and output. As described above, the state number / dominant symbol storage unit 10 follows the nature of the information source.
By rewriting 6,132, it is possible to realize an arithmetic coding / decoding device with high coding efficiency.

However, in the conventional encoding / decoding device as described above, as shown in FIG. 25, the state number / dominant symbol storage unit (106,
132) and a probability estimation table (110, 13)
0) search, (reverse) predictive conversion processing, area calculation, section register update, coordinate calculation, code register update, state number /
The dominant symbol storage units (106, 132) are updated. That is, for one symbol to be encoded (decoded), reading of the state number / dominant symbol storage unit (106, 132) in cycle 1, retrieval of the probability estimation table (110, 130) in cycle 2 and state number After finishing the / update operation of the predicted value and writing to the state number / dominant symbol storage unit (106, 132) in cycle 3, processing of the next symbol to be encoded (decoded) (cycles 4, 5, 6) ). For this reason, there is a limit in improving the processing speed.

Therefore, a technique relating to an apparatus for performing arithmetic encoding / decoding at high speed is proposed in Japanese Patent Laid-Open No. 5-67978. This publication discloses a rewritable memory that stores a state number and a dominant symbol corresponding to each context, a state number and a dominant symbol for the encoding target symbol read from this memory, or
A register for holding a state number and a dominant symbol after a rewrite process for the immediately preceding symbol, and determining whether or not the symbol to be encoded matches the predicted value, and according to the result, the state number of the memory in the context A control circuit for rewriting the dominant symbol, a detector for detecting whether or not the context for the symbol to be encoded matches the context for the immediately preceding symbol, and updating the contents of the register according to the detection result; and a detector output from the register. And an arithmetic encoder for encoding the prediction error signal based on the state number and the superior symbol.

The state number and the dominant symbol used in the encoding process depend on whether the context for the encoding target symbol and the context for the immediately preceding symbol match, and determine the state after the rewriting process for the immediately preceding encoding target symbol. The number and the dominant symbol or the output from the memory are selected and used. As a result, the search of the state number and the dominant symbol for the next symbol (search in the memory) and the area calculation processing of the number line for the symbol can be performed in parallel. As a result, the encoding and decoding speed can be improved.

[0030]

However, in the various types of conventional techniques described above, there is a limit in improving the speed of conversion processing such as encoding and decoding. That is, for example, in the adaptive arithmetic coding process, the area calculation of the number line for the symbol to be coded is performed by searching the area width table (accessing the probability estimation table), (reverse) predictive conversion processing, area calculation, and section calculation. Since the processing includes register update, coordinate calculation, code register update, and the like, the time required for searching for the state number and the dominant symbol for the next symbol to be encoded is generally much longer. For this reason, the cycle of the system clock is governed by the area calculation of the number line for the symbol to be encoded. As a result, it is difficult to improve the speed of the entire encoding process.

The present invention has been made in view of the above situation, and a first object of the present invention is to provide an encoding apparatus capable of further improving the encoding processing speed of image data. .

It is a second object of the present invention to provide a decoding apparatus capable of further improving the decoding processing speed of image data.

It is a third object of the present invention to provide an encoding / decoding device capable of further improving the encoding and decoding processing speed of image data.

[0034]

A first aspect of the present invention for solving the above-mentioned problems is an apparatus for encoding sequentially inputted image data, which requires encoding parameters for the same image data. An adaptive coding apparatus that changes in accordance with the coding information table includes a coding information table (224) storing, for each input image data, a coding parameter when not changed and a coding parameter when changed. Also, during the encoding process of the (n-1) th input image data, at least two encoding parameters estimated for the nth image data are read from the encoding information table, and the read code is read. Selecting means (244, 23) for selecting an appropriate parameter from the optimization parameters
6). Further, when the encoding processing of the (n-1) th image data is completed, the encoding processing means (220, 246) which performs the encoding processing of the nth image data using the encoding parameter selected by the selection means. ).

In the first aspect of the present invention as described above, at least two coding parameters estimated for the n-th image data (the coding parameter at the time of no change and the coding parameter after the change) From the encoding information table (224). Then, an appropriate encoding parameter is selected from the plurality of encoding parameters, and an encoding process is performed using the selected encoding parameter. As a result, even if the immediately preceding (n−1) th data is the same as the nth data and the encoding parameter is changed by the encoding process for the (n−1) th image data, the nth data is changed. At least two encoding parameters estimated for the image data of the encoding information table (22).
4), and an appropriate one can be selected based on the encoding processing result for the (n-1) th image data. As a result, the encoding process of the immediately preceding (n-1) th input data and the operation of reading the encoding parameter of the nth input data from the encoding information table (224) can be performed in parallel. The cycle of the system clock of the entire data encoding process can be shortened, and the encoding process can be speeded up.

In the invention as described above, it is possible to further include a coding parameter holding means (236) for holding the coding parameter selected by the selection means (244). In that case, the encoding processing means (2
20, 246), when the encoding process of the (n-1) th image data is completed, the encoding parameter holding unit (23).
The encoding process of the n-th image data is performed using the encoding parameter stored in 6). In this case, when the encoding process of the (n-1) th image data is completed, the encoding parameter of the nth image data can be held in the encoding parameter holding means (236).

A storage means (20) for storing state data (ST) indicating the state of the image data corresponding to the coding parameters stored in the coding information table (224).
4,216) can be further provided. In this case, the encoding information table (224) stores the encoding parameter (L
In addition to SZ), state transition destination information (NMPS, NLPS) indicating the updated value of the corresponding state data (ST) is stored. Further, state transition destination information (L_NMPS, L_NMS) indicating the updated value of the state transition destination (NMPS, NLPS)
NLPS, M_NMPS, M_NLPS).
The encoding parameter holding unit (236) holds at least state transition destination information stored in the encoding information table (224) as an encoding parameter estimated for the n-th image data. With such a configuration, during the conversion processing of the immediately preceding (n−1) th input data, all the conversion parameters estimated for the nth input data are read from the information table (224) in advance and held. It is possible to do.

A second aspect of the present invention for solving the above-mentioned problems is a decoding apparatus for decoding code data encoded by the encoding apparatus according to the first aspect into original image data. The data includes a decoding information table (324) that stores a decoding parameter when the data is not changed and a decoding parameter when the data is changed. In addition, during decoding of the (n-1) th input code data, at least two decoding parameters estimated for the nth input code data are read from the decoding information table (324). Selecting means (344, 336) for selecting an appropriate one from the read decoding parameters. Further, when the decoding process of the (n-1) th code data is completed, the decoding process of decoding the nth code data by using the decoding parameter selected by the selection means (344, 336). Means (320, 346).

In the second aspect of the present invention as described above, similarly to the first aspect, the decoding processing of the immediately preceding (n-1) th input data and the decoding of the nth input data are performed. Since the operation of reading the decryption parameter from the information table (324) is performed in parallel, the period of the system clock of the entire decoding process can be shortened, and the decoding process can be sped up.

A third aspect of the present invention is an encoding / decoding apparatus in which the encoding apparatus according to the first aspect and the decoding apparatus according to the second aspect are combined.

In a fourth more specific aspect of the present invention, means (210) for generating a context (CX) for a symbol to be encoded using a plurality of reference symbols at predetermined positions of a symbol sequence of an information source. ), A state number (ST) indicating a state of the context (CX), and a predicted value (MPS) of the encoding target symbol (2).
04, 216), and context holding means (203, 212) for temporarily holding a plurality of contexts (CX) corresponding to a plurality of symbols to be sequentially encoded. Also, the context holding means (203, 203)
212) Multiple contexts (CX) held in
First comparing means (214) for comparing
04, 216) and a second comparing means (222) for comparing the predicted value (MPS) of the encoding target symbol read from the encoding target symbol with the actual encoding target symbol value. Further, the probability region width (LSZ) corresponding to the state number (ST) stored in the storage means (204, 216), and the state transition destination information (NMPS, NLPS) and the state transition destination (NMPS,
NLPS) value (L_LSZ, M)
_LSZ) and state transition destination information (L_NMPS, L_) indicating the updated value of the state transition destination (NMPS, NLPS).
NLPS, M_NMPS, and M_NLPS) and encodes the encoding target symbol based on the probability region width read from the information table (224) and the result of the comparison by the second comparing means (222). Context (CX) for encoding target symbol based on state transition destination information read from information table (224)
Arithmetic coding means (220) for updating the state number (ST) and the predicted value (MPS) of the data. Further, the state number (ST) read from the storage means (204, 216)
And a first register (22) holding the predicted value (MPS).
8), a second register (230) for holding a state number (ST) and a predicted value (MPS) written to the storage units (204, 216), and a second register (230) for holding an output of the second register (230). 3 (232) and a fourth register (234) for holding the context state number (ST1) for the (n-1) th input image data. Also, based on the comparison result of the first comparing means (214), the first, second, third or fourth register (22
8, 230, 232, 234), a probability region width (LSZ1) of the context corresponding to the (n-1) th input image data, and state transition destination information ( NMPS1, NLPS1) and a fifth register (236).

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to embodiments.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is one in which the technical idea of the present invention is applied to a coding apparatus for coding a binary image by an adaptive arithmetic coding system. Show. The encoding apparatus according to the present embodiment converts the input symbol data to 2
Symbol sequence reading unit 2 for inputting as a value symbol sequence
06, a symbol sequence storage unit 208 connected to the output of the symbol sequence reading unit 206, and the image reference symbol selection unit 21 connected to the output of the symbol sequence storage unit 208.
0, a context buffer 203 connected to the output of the image reference symbol selection unit 210, a detector 214 connected to the output of the context buffer 203, and a single-port memory in which the address terminal AD is connected to the output of the context buffer 203. 204 (state number / dominant symbol storage unit), read / write control unit 20 connected to output of detector 214 and single port memory 204
5 and the arithmetic coding unit 2 connected to the output of the detector 214 and connected to the read data terminal RDT and the write data terminal WDT of the single port memory 204.
20, a predictive conversion processing unit 222 connected to the output of the symbol sequence storage unit 208 and the arithmetic coding unit 220, and a probability estimation table 224 connected to the arithmetic coding unit 220.

In the coding apparatus having the above configuration,
The symbol sequence storage unit 208 stores the binary symbol sequence read by the binary symbol sequence reading unit 206. The image reference symbol selection unit 210 includes a symbol series storage unit 2
A plurality of reference symbols at predetermined positions with respect to the encoding target symbol are selected from the binary symbol string stored in 08 to generate a context (CX).

The context buffer 203 holds the context data sequentially output from the image reference symbol selection section 210 and buffers four consecutive context data. As shown in FIG. 2, the context buffer 203 includes four registers 203a and 203
b, 203c and 203d. The latest context CX is held in the first-stage register 203a, and the output CX1 is shifted to the second-stage register 203b. The registers 203b, 203c, 203d are
One before the latest context CX, two before, 3
The previous contexts CX2, CX3, CX4 are held. The contexts CX1 and CX4, which are the outputs of the registers 203a and 203d, are supplied to the selector 226,
Either one is selected as the address signal AD.

The detector 214 outputs the context data (C
X) and the context data (CX1, CX2, CX3, CX) held in the context buffer 203.
It is determined whether or not 4) has the same value. Here, the determination result of the contexts CX1 and CX2 by the detector 214 is used as an output EQ12, and the contexts CX1 and CX2 are output.
The judgment result of X3 is set as output EQ13, and the context CX
1 and CX4 are determined as output EQ14, the determination results of contexts CX2 and CX3 are defined as output EQ23, the determination results of contexts CX2 and CX4 are defined as output EQ24, and the output of a register (not shown) storing EQ14 is defined as output d1_EQ14. And Each judgment result EQ12, EQ
13, EQ14, EQ23, and EQ24 indicate 1 if they are the same value, and 0 if they are not the same value.

The single port memory 204 (state number /
The dominant symbol storage unit stores the state number (ST) and the MPS (dominant symbol) value of the context of all combinations. Then, one of the latest context CX1 (see FIG. 2) in the context data held in the context buffer 203 and the context CX4 (see FIG. 2) input most recently is stored in the address of the single port memory 204. And

The read / write control unit 205 includes the detector 2
Based on the determination result (EQ12 and the like) at 14, reading and writing of the single port memory 204 are controlled.
When reading data from the single port memory 204, the read address CX1 is stored in another context data CX held in the context buffer 203.
When it is not equal to any of CX2, CX3, and CX4, that is, when EQ12 = EQ13 = EQ14 = 0, the context data CX1 is selected as the read address of the single port memory 204 for selecting. On the other hand, the read address CX1 is different from the other context data CX.
If the value is equal to any one of CX2, CX3, and CX4, the single port memory 204 is not read. Also, when writing data to the single-port memory 204, when the write address CX4 is not equal to any of the other context data CX1, CX2, CX3 held in the context buffer 203,
That is, when EQ14 = EQ24 = EQ34 = 0, the context data CX4 is selected as the address of the single port memory 204. On the other hand, the write address CX4 is different from the other context data CX1, CX1.
2 and CX3, the writing to the single port memory 204 is not performed.

The predictive conversion processing unit 222 outputs data indicating whether or not the encoding target symbol matches a symbol (dominant symbol: MPS) whose appearance probability is expected to be high in the context (prediction error: if it matches, 0, and 1) is output if they do not match.

The probability estimation table 224 stores the size (L) of a predetermined LPS (inferior symbol) probability region corresponding to the state number (ST) indicating the state of the context CX.
SZ) and state transition information (NMPS, NLPS, Switc)
h) is remembered. Here, LPS indicates an inferior symbol expected to have a low probability of occurrence in the context,
NMPS indicates a state number to be applied next when the encoding target symbol is the dominant symbol MPS, and NLPS
Indicates a state number to be applied next when the encoding target symbol is the inferior symbol LPS, and Switch indicates an exchange command of the superior symbol MPS and the inferior symbol LPS. Further, the probability estimation table 224 includes NLP
The size of the LPS probability region corresponding to the value of S (L_LS
Z) and state transition information (L_NMPS, L_NLPS, L
_Switch), the size (M_LSZ) of the probability region of the LPS corresponding to the value of NMPS, and the state transition information (M_NM)
PS, M_NLPS, and M_Switch). For example, when ST = 1, NLPS = 14, so L_LS
Z, L_NMPS, L_NLPS, L_Switch are respectively LSZ values 0x5A7F corresponding to ST = 14,
The NLPS value is 15, the NMPS value is 15, and the switch value is 1.
Also, when ST = 1, NMPS = 2, so M_LS
Z, M_NMPS, M_NLPS, and M_Switch are LSZ values 0x1114 and N respectively corresponding to ST = 2.
The LPS value is 16, the NMPS value is 3, and the switch value is 0. Details of the probability estimation table 224 are shown in FIGS. The arithmetic code stock 220 outputs a code output of a symbol to be coded,
The update of the state number ST and the MPS value for each context is performed.

FIG. 6 is a block diagram showing the first embodiment of the present invention constructed as described above.
An operation example in the case where are equal is shown. In the figure, context # 1 is the read address of the single port memory (state number / predicted value storage unit) 204 in cycle 1.
In cycle 2, the state number ST1 read from the single port memory 204 becomes a read address of the probability estimation table 224, and data corresponding to the state number ST1 is read. In cycle 3, the probability estimation table 22
LSZ (ST1), N of the data read from
LPS (ST1), NMPS (ST1), Switch (ST
1), the encoding process of the encoding target symbol is performed using the LSZ (ST1), and the transition destination NST1 of the state number ST1 is obtained. In cycle 4, the state transition destination NST1 for context # 1 is held in the register.

On the other hand, the context # 2 input next to the context # 1 becomes the read address of the single port memory (state number / predicted value storage unit) 204 in cycle 2. (Only the read address is set, no read operation is performed.) In cycle 3, context # 2
Is being calculated, and the state transition destination of context # 1 is NLP.
The state number ST1 of the context # 1 is provided as a read address of the probability estimation table 224 to read out data so that any one of S (ST1), NMPS (ST1), and ST1 can be handled. In cycle 4, since the state transition destination NST1 for context # 1 is determined, the data corresponding to NST1 is selected from the data read from the probability estimation table 224 in cycle 3, and the encoding process of the encoding target symbol is performed. At the same time, the state transition destination NST2 of the context # 2 is obtained. In cycle 5, the state transition destination NST2 for context # 2 is held in the register.

FIG. 7 shows a more detailed example of the read / write operation of the first embodiment. In this example, contexts # 1, # 2, #
3, # 4, # 5, # 6, # 7, # 8, # 9, # 10 show processing (encoding) operations, and # 3 {# 4, # 3}
# 5, # 3, # 6, # 4, # 6, # 5, # 6, # 5, #
7, # 5 ≠ # 8, # 6 = # 8. First, looking at the context # 1, the context # 1 becomes the read address of the single port memory (state number / predicted value storage unit) 204 in cycle 1. In cycle 2, data corresponding to state number ST1 read from single port memory 204 is stored in probability estimation table 224.
Read from In cycle 3, the probability estimation table 22
4 based on the data read from the context #
In addition to the encoding of the encoding target symbol corresponding to No. 1, the updated value of the state number ST1 of the context # 1 is obtained. In cycle 4, the updated value of state number ST1 obtained in cycle 3 is used as the write address of single port memory 204. Context # 2 is also processed in the same manner as context # 1.

After the context # 3 becomes the read address of the single port memory (state number / predicted value storage) 204 in cycle 3, the updated value of the corresponding state number ST3 is changed to the single port memory 20 in cycle 6.
4 write data. Where context # 3
Are not equal to the context # 3, the context # 3 is selected as the address (write address) of the single-port memory 204 and corresponds to the context # 3. The updated value of the state number ST3 is written in the single port memory 204.

Since the context # 5 is not equal to any of the contexts # 6, # 7 and # 8 generated later,
In cycle 9, context # 5 is selected as the address (write address) of single port memory 204, and the updated value of state number ST5 corresponding to context # 5 is written to single port memory 204.
Here, since contexts # 6 and # 8 are equal, it is not necessary to read context # 8 in cycle 9.

Context # 6 is originally a single port memory (state number / predicted value storage) 204 in cycle 6.
Since the updated value of the state number ST3 corresponding to the context # 3 is the write address in cycle 6, the read address is read from the single port memory 204 in cycle 7 after sliding by one cycle.

FIG. 8 shows an adaptive arithmetic coding apparatus according to a second embodiment of the present invention, in which components identical or corresponding to those of the first embodiment are denoted by the same reference numerals. The encoding device according to the present embodiment employs a dual-port memory 216 instead of the single-port memory 204 in the encoding device according to the first embodiment shown in FIG. 1, and shares many components. Therefore, in this embodiment, only the differences from the first embodiment will be described in detail, and the detailed description of the other common parts will be omitted.

The encoding apparatus according to the present embodiment includes a symbol sequence reading unit 206 for inputting input symbol data as a binary symbol sequence, a symbol sequence storage unit 208 connected to the output of the symbol sequence reading unit 206, An image reference symbol selection unit 210 connected to the output of the storage unit 208, a context buffer 212 connected to the output of the image reference symbol selection unit 210, a detector 214 connected to the output of the context buffer 212,
A dual port memory 216 (state number / dominant symbol storage unit) in which a read address terminal RAD and a write address terminal WAD are connected to the output of the context buffer 212, the output of the detector 214, and the control terminal of the dual port memory Leads connected to R and W /
The arithmetic control unit 220 connected to the output of the detector 214 and connected to the read data terminal RDT and the write data terminal WDT of the dual port memory 216, and the output of the symbol sequence storage unit 208 It includes a predictive conversion processing unit 222 connected to the arithmetic coding unit 220, and a probability estimation table 224 connected to the arithmetic coding unit 220. Probability estimation table 224
Are the same as those in FIGS. 3 to 5 shown in the first embodiment.

As shown in FIG. 9, the context buffer 212 has four registers 212a, 212b, 212
c, 212d. The latest context CX is held in the first-stage register 212a,
The output CX1 is shifted to the second-stage register 212b.
The registers 212b, 212c, and 212d respectively hold the contexts CX2, CX3, and CX4 one before, two before, and three before the latest context CX.

The dual port memory 216 (state number /
The dominant symbol storage unit stores the state number (ST) and the MPS (dominant symbol) value of the context of all combinations. Then, the latest context CX1 (see FIG. 9) in the context data held in the context buffer 212 is set as a read address, and the context CX4 (see FIG. 9) input most recently is set as a write address. It is to be noted that the configuration is such that reading of data to the read address RAD and writing of data to the write address WAD can be executed simultaneously. The data stored in the dual port memory 216 is shown in FIG.
As shown in FIG. 7, ST indicates a state number serving as a read address of the probability estimation table 224 described in detail later.

The read / write control unit 218 detects the detector 2
Based on the determination result (EQ12 and the like) at 14, the reading and writing of the dual port memory 216 are controlled.
When reading data from the dual port memory 216, when the read address RAD (= CX1) is not equal to any of the other context data CX2, CX3, and CX4 held in the context buffer 212, that is, EQ12 = EQ13 = When EQ14 = 0, the read signal R of the dual port memory 216 is activated to perform the read operation. on the other hand,
When the read address RAD (= CX1) is equal to any one of the other context data CX2, CX3, CX4, the read signal R of the dual port memory 216 is made inactive. When writing data to the dual port memory 216, the write address WAD (= CX4) is stored in the context buffer 2
12 are stored in the other context data CX1,
When not equal to CX2 or CX3, that is, E
When Q14 = EQ24 = EQ34 = 0, the write signal W of the dual port memory 216 is activated to perform the write operation. On the other hand, the write address WAD (= CX4) is
If it is equal to any one of CX1, CX2 and CX3, the write signal W of the dual port memory 216 is deactivated.

The arithmetic coding unit 220 outputs the code output of the symbol to be coded and the state number ST for each context.
And an update calculation of the MPS value. FIG. 10 shows the details. The arithmetic coding unit 220 according to the present embodiment includes five registers 228, 230, 232, 234, and 236.
And four selectors (multiplexers) 238, 240,
242, 244, code output and state number update operation unit 2
46, a write data selection circuit 248, and an exclusive OR circuit 250.

In such an arithmetic coding unit 220,
The input terminal of the register 228 has a dual port memory 2
Sixteen read data terminals RDT are connected, and the output terminal of the register 228 is connected to the input terminal of the selector 238. The other input terminals of the selector 238 are connected to the output terminal of the register 232, the output terminal of the register 230, and the output terminal of the register 234, respectively. An output terminal of the selector 238 is connected to an address terminal of the probability estimation table 224 and an input terminal of the selector 242. The other input terminal of the selector 242 is connected to the output terminal of the selector 240, and the output terminal of the selector 242 is connected to the input terminal of the register 234. To the output terminal of the register 234, in addition to the input terminal of the selector 238, the input terminal of the selector 240, the predictive conversion processing unit 222, and one input terminal of the exclusive OR circuit 250 are connected. .

Here, the output signal (MPS1, ST1) of the register 234 is directly input to one input terminal of the selector 240, while the output signal (MPS1, ST1) of the register 234 is input to the other input terminal. A composite signal (MPS1, NMPS1) of the dominant symbol MPS1 of the MPS1, ST1) and the NMPS1 of the output signals (NMPS1, NLPS1, LSZ1, Switch1) of the register 236 is supplied. Further, the output signal (MPS) of the exclusive OR circuit 250 is provided to the remaining one input terminal of the selector 240.
1 ′) and the output signal of the register 236 (NMPS1, N
A composite signal (MPS1 ′, NLPS1) with NLPS1 in LPS1, LSZ1, Switch1) is supplied. The output of the write data selection circuit 248 is connected to the control terminal of the selector 240.

The output of the probability estimation table 224 is connected to three input terminals of the selector 244.
The input terminal of the register 236 is connected to the output terminal 4.

The output terminal of the register 236 is connected to the above-mentioned selector 240 and the code output and state number update operation unit 24.
6 and the exclusive OR circuit 250 are connected. Switch1 is supplied to the exclusive OR circuit 250, and LSZ1 is supplied to the code output and state number update operation unit 246.

Next, the operation (function) of each component of the arithmetic coding unit 220 of this embodiment will be described in more detail.
The register 228 holds the data read from the dual port memory 216, and the register 230 holds the data written to the dual port memory 216, that is, the context C held in the context buffer 212.
Updated state number ST (CX4) and MP corresponding to X4
Holds S (CX4) value. The state number ST (CX3) and MPS (CX3) value of the context CX3 held in the context buffer 212 are stored in the register 2
34. Register 236 includes register 234
Holds the size LSZ1 of the probability region of the inferior symbol corresponding to the state number ST1 and the state transition information NMPS1,
NLPS1, Switch1) are held. Register 232
Is a register that holds the output of the register 230,
The updated state number and MPS value of the context input one clock before the context CX4 (that is, input three clocks before the CX2) are held. Note that FIG.
All the registers shown in FIG. 10 operate with the same system clock.

The selector 238 selects the output of the registers 228, 230, 232, 234 as the output of the selector 238 based on the output of the detector 214. For example, in the next system clock cycle in which the read signal R of the dual port memory 216 generated based on the output of the detector 214 becomes active, the output of the register 228, that is, the data read from the dual port memory 216 is read. select. Because the context CX
The state number and MPS value corresponding to 2 are stored in registers 230, 2
32, 234, but not in the register 228. On the other hand, when EQ23 = 1,
That is, when the context data CX2 and CX3 are the same, the state number ST (CX3) of the context CX3
And the output of the register 234 holding the MPS (CX3). When EQ23 = 0 and EQ24 = 1, that is, when the context data CX2 and CX3 are different and CX2 and CX4 are equal, the state number for the context CX2 and the latest value of MPS are the updated state number of the CX4. And the MPS value, the register 23
Select an output of 0. Also, EQ23 = 0 and EQ24
= 0 and dl_EQ14 = 1, that is, if the context data CX2 and CX3 are different, CX2 and CX4 are different, and the output of the register storing EQ14 is 1, the state with respect to the context input three clocks before CX3 Since the number and MPS value become the latest state number and MPS value for CX2, the output of the register 232 holding those values is selected. Then, the state number part ST0 of the output of the selector 238 becomes the address input of the probability estimation table 224.

The code output and state number update calculation unit 246 performs arithmetic coding calculation based on the probability region width LSZ of the inferior symbol LPS from the register 236 and the prediction error value from the prediction conversion processing unit 222, and outputs a code. , Update calculation of the state number. The exclusive OR circuit 250
When the Switch information output from the register 236 is 1,
The MPS value output from the register 234 is inverted. In the selector 240, the MPS value and ST value signals (MPS 1, ST 1) output from the register 234, the MPS value of the signals (MPS 1, ST 1) output from the register 234, and the output from the register 236. NMPS
The signal (MPS1, NMPS1) obtained by combining the values, the MPS value output from the exclusive OR circuit 250, and the register 2
36 (MPS)
1 ′, NLPS1) and the output signal of the selector 240. Then, the data selected by the selector 240 is held in the register 230.

The write data selection circuit 248 selects the selector 2 based on the prediction error value from the prediction conversion processing unit 222, the code output, and the operation result of the state number update operation unit 246.
Forty selection signals (sel_wdt) are generated. For example, if the prediction error is 0 and A-LSZ <0x8000, (MPS1, NMPS1) is used.
If Z> = 0x8000, (MPS1, ST1) is selected, and if the prediction error is 1, (MPS1 ′, NLPS1) is selected. It should be noted that the same arithmetic processing as the method described in the section of the related art can be applied to specific arithmetic processing, and a detailed description of the arithmetic processing is omitted here.

The selector 242 selects one of the output (MPS0, ST0) of the selector 238 and the output of the selector 240, and the selected output is held in the register 234. Here, a selection signal for controlling the selection operation of the selector 242 is generated based on the output signal EQ23 of the detector 214. For example, when EQ23 = 0, ie,
When the context data CX2 and CX3 held in the context buffer 212 are not equal, the updated latest state number corresponding to the context data CX2 is determined, and is held in any of the registers 228, 230, and 232. Since the selection of which register is held is performed by the selector 238, the selector 2
Reference numeral 42 selects the output of the selector 238. On the other hand, EQ23
= 1, that is, context data CX2 and CX
3 are equal, the state number ST1 for the context data CX3 having the same value as the context data CX2 is held in the register 234, and the state transition destination number corresponding to the state number ST1 and the MPS value (the state number for the context data CX2 and the MPS value). MPS value) ST1, NLP
Either S1 or NMPS1 is being selected by the selector 240. Therefore, the output of the selector 240 is selected, and at the same time as updating the state number for the context data CX3, the updated value is held in the register 234 as the state number for the context data CX2.

In the selector 244, the output of the probability estimation table 224 is (LSZ, NLPS, NMPS, Sw
itch), (L_LSZ, L_NLPS, L_NMPS,
L_Switch), (M_LSZ, M_NLPS, M_NM
PS, M_Switch), one of them is selected, and the selected data is stored in register 2
36. A selection signal for controlling the selection operation of the selector 244 is generated based on the output EQ23 of the detector 214 and the output (sel_wdt) of the write data selection circuit 248. For example, when EQ23 = 0, ie,
If the context data CX2 and CX3 held in the context buffer 212 are not equal, the updated latest state number corresponding to the context data CX2 has been determined, and the registers 228, 230, and 232 have been determined.
The selection of which register is held is performed by the selector 238, and the selector 23
8 is the address input of the probability estimation table 224, the selector 244 selects the probability estimation table 224.
Output (LSZ, NLPS, NMPS, Switch)
Select

On the other hand, when EQ23 = 1, that is, when the context data CX2 and CX3 held in the context buffer 212 are equal, the state number ST1 for the context data CX3 having the same value as the context data CX2 is stored in the register 234. And the state transition destination number (the state number for the context CX2) corresponding to the state number ST1 is ST1, NLPS.
1, NMPS1 is being selected by the selector 240. Therefore, in parallel with the process of selecting the state transition destination number of the context data CX3, the context data CX3
Size LS of the probability region of the LPS corresponding to the state number 2
Z1 and state transition information are obtained.

That is, since the state number of the context data CX2 is any one of ST1, NLPS1, and NMPS1, the selector 2 is set so that ST1 output from the register 234 becomes the address input of the probability estimation table 224.
At 38, the output of the register 234 is selected. Then, the selector 244 selects read data of the probability estimation table 224 classified into three groups as described above based on the sel_wdt signal. Finally, the selector 24
When (MPS1, ST1) is selected at 0, the selector 244 selects (LSZ, NLPS, NMPS, Switch).
Is selected, and (MPS1 ′, NLP)
When S1) is selected, the selector 244 selects (L_LS)
Z, L_NLPS, L_NMPS, L_Switch) are selected, and when (MPS1, NMPS1) is selected in the selector 240, (M_LSZ, M_N) is selected in the selector 244.
LPS, M_NMPS, M_Switch).

Next, an operation example of the above embodiment will be described with reference to a timing chart shown in FIG. 11, CX1 to CX4 are context data held in the context buffer 212, CX1 is input as a read address of the dual port memory 216, and CX4 is input as a write address of the dual port memory 216. Also, the read signal R and the write signal W
Are signals indicating that the HIGH state is active.

First, consider the process for context # 4. In Cycle 1, context # 4 is the read address (CX1) of dual port memory 216, and is different from any of contexts # 3 to # 1 previously input to context buffer 212 (# 4 （#).
3, # 4 ≠ # 2, # 4 ≠ # 1). That is, the detector 21
In the output of 4, EQ12 = EQ13 = EQ14 = 0
And the read signal R of the read / write control unit 218
Becomes active. As a result, the corresponding data from the dual port memory 216, that is, the context #
The state number ST and MPS value of No. 4 are read out and held in the register 228 in Cycle 2. In Cycle 2, E
Q23 = EQ24 = dl_EQ14 = 0 (# 4 ≠ # 3,
(# 4 ≠ # 2, # 4 ≠ # 1), the selector 238 selects the output of the register 228, and uses the context # 4 as the address input of the probability estimation table 224. Selector 242
Since EQ23 = 0 (# 4 ≠ # 3), the selector 2
38, the output of register 228 is selected. Since the selector 244 also has EQ23 = 0 (# 4 ≠ # 3), the output of the probability estimation table 224 includes (LSZ,
NLPS, NMPS, Switch).

Next, in Cycle 3, the output of the selector 242 is stored in the register 23 as the state number of the context # 4.
4 is held. The output of the selector 244 is held in the register 236 as the state transition information of the context # 4 and the probability area width LSZ of the inferior symbol LPS. Then, the code output and state number update calculating section 246 performs predetermined calculation processing based on the data held by these registers 234 and 236, and at the same time, causes the selector 240 to select the update of the state number ST of the context # 4. To instruct.

In Cycle 4, the output of the selector 240 is held in the register 230 as a new state number / MPS value of the context # 4. At this time, context # 4 is input as the write address (CX4) of the dual port memory 216, but EQ34 = 1, that is, context # 5 having the same value as context # 4 has the next cycle.
5 is input as a write address, so Cylce 4
Then, data writing to the dual port memory 216 is not performed.

Next, consider the process for context # 5. The context # 5 is the read address (CX1) of the dual port memory 216 in Cycle2, but has the same value as the context # 4 previously input to the context buffer 212 (# 5 = # 4). That is, since EQ12 = 1 in the output of the detector 214, the read signal R of the read / write control unit 218 becomes inactive, and data is not read.

In Cycle 3, since EQ23 = 1, the selector 238 selects the output of the register 234 holding the state number of the context # 4, and
2 is the context number that is the status number of context # 5
The output of the selector 240 selecting the state transition destination of No. 4 is selected. The selector 244 determines whether the output of the probability estimation table 224 is (LSZ, NLPS, NMPS, Switch),
(L_LSZ, L_NLPS, L_NMPS, L_Swit
ch) or (M_LSZ, M_NLPS, M_NMPS,
M_Switch). Which output is selected is linked to the determination of the state transition destination of the context # 4 as described above. In Cycle 3, since the state transition destination of context # 4 is determined, the state number and state transition information for context # 5 having the same value as context # 4, and the probability area width LSZ of inferior symbol LPS are also determined.

In Cycle 4, the state number for context # 5 determined in Cycle 3 (output of selector 242)
Is stored in the register 234, and the state transition information and the probability region width LSZ (output of the selector 244) of the inferior symbol LPS are stored in the register 236. These registers 23
The code output and state number update operation unit 246 performs an operation process based on the data held by the
0 is instructed to select the update of the status number of context # 5.

In Cycle 5, the output of the selector 240 is held in the register 230 as a new state number / MPS value of the context # 5. At this time, the context # 5 is input as the write address (CX4) of the dual port memory 216. However, EQ24 = 1, that is, the context # 7 having the same value as the context # 5 has a write address (Cycle 7) two cycles later. CX4) is input as Cycle5.
16 is not written.

Next, consider the processing for context # 6. In Cycle 3, context # 6 is the read address (CX1) of dual port memory 216, but has the same value as context # 3 previously input to context buffer 212 (# 6 = # 3, # 6).
6 # 5, # 6 # 4). That is, since EQ14 = 1 in the output of the detector 214, the read signal R of the read / write control unit 218 becomes inactive,
Data is not read from the dual port memory 216.

In Cycle 4, dl_EQ14 = 1, EQ
Since 24 = 0, the output of the register 232 holding the updated state number of the context # 3, which is the state number of the context # 6 (because # 6 = # 3), is selected by the selector 238. , Probability estimation table 2
24 address inputs. EQ23 = 0 (# 6 ≠ #
5), the selector 242 outputs the output of the selector 238,
That is, the output of the register 232 is selected. Also, EQ
Since 23 = 0 (# 6 ≠ # 5), the selector 244 outputs (LSZ, NLP) of the output of the probability estimation table 224.
S, NMPS, Switch).

In Cycle 5, the output of the selector 242 is held in the register 234 as the state number of context # 6. The output of the selector 244 is the state transition information of the context # 6 and the probability region width L of the inferior symbol LPS.
It is held in the register 236 as SZ. Based on the data held by these registers 234 and 236, the code output and state number update operation unit 246 performs an operation process, and instructs the selector 240 to update and select the state number of the context # 6.

In Cycle 6, the output of the selector 240 is held in the register 230 as a new state number / MPS value of the context # 6. At this time, the context # 6 is input as the write address (CX4) of the dual port memory 216, but EQ24 = 1, that is, the context # 8 having the same value as the context # 6 is written at the write address (Cycle 8) two cycles later. CX4), the dual port memory 2 in Cycle6
No data is written to 16.

Next, processing for context # 7 will be considered. In Cycle 4, context # 7 is a read address (CX1) of dual port memory 216, but has the same value as context # 5 previously input to context buffer 212 (# 7 = # 5, # 7).
7 # 6, # 7 # 4). That is, since EQ13 = 1 in the output of the detector 214, the read signal R of the read / write control unit 218 becomes inactive,
Data is not read from the dual port memory 216.

In Cycle 5, EQ24 = 1 and EQ23 =
0, the updated state number of context # 5, which is the state number of context # 7 (because of #
7 = # 5) is selected by the selector 238 and becomes the address input of the probability estimation table 224. Since EQ23 = 0 (# 7 ≠ # 6), the selector 242 selects the output of the selector 238, that is, the output of the register 230. EQ23 = 0 (# 7
≠ # 6), the selector 244 outputs (LSZ, NLPS, NMPS, Sw) in the output of the probability estimation table 224.
itch).

In Cycle 6, the output of the selector 242 is held in the register 234 as the state number of the context # 7. The output of selector 244 is context # 7
Is stored in the register 236 as the state transition information and the probability region width LSZ of the inferior symbol LPS. Based on the data held by these registers 234 and 236, the code output and state number update calculation unit 246 performs calculation processing,
The selector 240 is instructed to select the update of the state number of the context # 7.

In Cycle 7, the output of the selector 240 is held in the register 230 as a new state number / MPS value of the context # 7. At this time, the context # 7 is input as the write address (CX4) of the dual port memory 216. However, EQ24 = 1, that is, the context # 9 having the same value as the context # 7 is written at the write address (Cycle 8) two cycles later. CX4), the dual port memory 2 in Cycle6
No data is written to the 16.

As can be seen in Cycle 1 when data is written to the dual port memory 216, when the context CX4 serving as the write address is different from any of the other contexts stored in the context buffer 212 (EQ14 = EQ24 = EQ34 =
0).

The code output is performed while updating the state number ST and the MPS value of the context corresponding to the symbol to be coded while repeating the above-described operation. FIG.
FIG. 12 is a simplified timing chart shown in FIG. As can be seen from FIG. 12, in the present embodiment, reading of the dual-port memory 216 (state number / dominant symbol storage unit), search of the probability estimation table,
The update operation of the state number / MPS value and the processing of writing to the dual port memory 216 (state number / dominant symbol storage unit) can be performed simultaneously in parallel.

FIG. 13 shows a configuration of a decoding apparatus according to the third embodiment of the present invention. This decoding device corresponds to the encoding device shown in FIG. 8, and is a device that decodes encoded data encoded by the encoding device into original image data. The decoding device according to the present embodiment includes a symbol sequence storage unit 308, an image reference symbol selection unit 310,
Context buffer 312, detector 314, dual port memory (state number / dominant symbol storage unit) 3
16, a read / write control unit 318, an arithmetic decoding unit 320, an inverse prediction conversion processing unit 322, and a probability estimation table 324. This decoding device has almost the same configuration as that of the encoding device of FIG. 8, and a detailed description of the same components as those of the encoding device of the above embodiment is omitted to avoid redundant description.

[0094] The probability estimation table 324 indicates which optimal probability area is to be allocated to the inferior symbol LPS in each state of the context, and which state number is appropriate as a state transition destination when normalization occurs. Is statistically obtained and is the same as the probability estimation table 224 of the encoding device. The dual port memory 316 is a storage device having the same format and data as the dual port memory 216 in the encoding device.

Arithmetic decoding section 320 has input code data, state number / MPS value read from dual port memory 316, and occurrence probability area width LSZ of inferior symbol LPS read from probability estimation table 324. / State transition information is supplied. Based on these pieces of information, information on whether the decoding target symbol is the superior symbol MPS or the inferior symbol LPS in the context and the MPS value of the context are output to the inverse prediction conversion processing unit 322, and the The state number / MPS value is updated.

[0096] Inverse prediction conversion processing section 322 outputs a decoded symbol based on the output signal from arithmetic decoding section 320. The decoded symbol output from the inverse prediction conversion processing unit 322 is stored in the symbol sequence storage unit 308.

FIG. 14 shows the configuration of the arithmetic decoding unit 320. The arithmetic decoding unit 320 of the present embodiment includes five registers 328, 330, 332, 334, 336 and four selectors (multiplexers) 338, 340, 342, 34.
4, a code input and state number update operation unit 346, a write data selection circuit 348, and an exclusive OR circuit 350
And The arithmetic decoding unit 320 has almost the same configuration as that of the arithmetic encoding unit 220 in FIG. 10, and the description of the same components as those of the arithmetic encoding unit 220 in the above embodiment will be omitted to avoid redundant description. . The difference from the arithmetic coding unit 220 shown in FIG. 10 is that the code input and state number update calculation unit 346 and the write data selection circuit 348
It is.

The write data selection circuit 348 generates a selection signal for controlling the selection operation of the selector 340 based on the operation result of the code input and state number update operation section 346. The operation of updating the state number and MPS value for the context of each decoding target symbol is the same as the operation of updating the state number and MPS value for the encoding target symbol in the case of the encoding device. The arithmetic processing operation of the decoding apparatus described above can employ the same method as the method shown in the section of the prior art, and the details of the arithmetic processing of the arithmetic decoding are omitted here.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and does not depart from the gist of the technical idea of the present invention shown in the claims. Various changes are possible within the scope.

[0100]

As described above, according to the present invention,
Regardless of the type of image data, there is an effect that the processing speed of encoding and decoding of image data can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an adaptive arithmetic coding device according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a configuration of a main part (context buffer) of the first embodiment shown in FIG. 1;

FIG. 3 is a table showing a part of the contents of a probability estimation table according to the first embodiment, and is connected to the contents of FIGS. Has become.

FIG. 4 is a table showing a part of the contents of the probability estimation table according to the first embodiment, and is connected to the contents of FIGS. 3 and 5 so that the probability estimation table is completed. Has become.

FIG. 5 is a table showing a part of the contents of a probability estimation table according to the first embodiment, and is linked to the contents of FIGS. Has become.

FIG. 6 is a timing chart showing a schematic operation in the first embodiment.

FIG. 7 is a timing chart showing a detailed operation in the first embodiment.

FIG. 8 is a block diagram showing a configuration of an adaptive arithmetic coding device according to a second embodiment of the present invention.

FIG. 9 is a schematic block diagram showing a configuration of a main part (context buffer) of the second embodiment shown in FIG. 8;

FIG. 10 is a block diagram illustrating a detailed configuration of a main part (arithmetic encoding unit) of the second embodiment.

FIG. 11 is a timing chart showing a detailed operation in the second embodiment.

FIG. 12 is a time chart showing an overall schematic operation of the second embodiment.

FIG. 13 is a block diagram showing a configuration of an adaptive arithmetic decoding device according to a third embodiment of the present invention.

FIG. 14 is a block diagram illustrating a detailed configuration of a main part (arithmetic decoding unit) according to a third embodiment;

FIG. 15 is a schematic block diagram showing a background art of the present invention.

FIG. 16 is a block diagram showing a configuration of a conventional adaptive arithmetic coding device.

17 is an explanatory diagram showing the contents of data stored in a state number / dominant symbol storage section of the conventional adaptive arithmetic coding device shown in FIG. 16;

FIG. 18 is an explanatory diagram showing a concept of a probability region subtraction process in an arithmetic coding device (decoding device).

FIG. 19 is an explanatory diagram showing the concept of conditional exchange processing and normalization processing in an arithmetic coding device (decoding device).

FIG. 20 is a diagram illustrating a subtraction process performed when an area width LSZ of an LPS (inferior symbol) is relatively large in a case where an MPS (dominant symbol) continuously occurs in an arithmetic encoding device (decoding device). It is explanatory drawing which shows the concept of a normalization process.

FIG. 21 is a diagram illustrating a subtraction process performed when an area width LSZ of an LPS (inferior symbol) is relatively small in a case where an MPS (dominant symbol) continuously occurs in an arithmetic encoding device (decoding device); FIG. 4 is an explanatory diagram illustrating a concept of a normalization process.

FIG. 22 is a diagram illustrating a subtraction process performed when an area width LSZ of an LPS (inferior symbol) is relatively large in a case where an LPS (inferior symbol) continuously occurs in the arithmetic encoding device (decoding device). It is explanatory drawing which shows the concept of a normalization process.

FIG. 23 is a diagram illustrating a subtraction process in a case where the region width LSZ of an LPS (inferior symbol) is relatively small when an LPS (inferior symbol) is continuously generated in the arithmetic encoding device (decoding device); It is explanatory drawing which shows the concept of a normalization process.

FIG. 24 is a block diagram showing a configuration of a conventional adaptive arithmetic decoding device.

FIG. 25 is a timing chart showing the operation of the conventional adaptive arithmetic coding device (decoding device) shown in FIGS. 16 and 24.

[Explanation of symbols]

200: Conversion processing unit 201: Conversion information table 201a: Conversion parameter holding unit 202: Control unit 204: Single port memory 210, 310 ... Image reference symbol selection unit 212, 312 ..Context buffers 214,314 ... Detectors 216,316 ... Dual port memory 220 ... Arithmetic coding unit 222 ... Predictive transformation processing unit 224,324 ... Probability estimation tables 228,230, 232,234,236,328,3
30, 332, 3343, 336... Registers 238, 240, 242, 244, 338, 340, 3
42, 344... Selector

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/40 H03M 7/30 H04N 1/41

Claims (6)

(57) [Claims] An adaptive arithmetic encoding device for encoding binary image data which is sequentially input, wherein the encoding parameter for the image data is changed as required. And at least two encoding parameters estimated for the n-th image data during the encoding processing of the (n-1) -th input image data from the encoding information table.
Encoding parameter holding means for reading and holding ; when the coding processing of the ( n-1) th image data is completed
In that at least two of the holding means
Selection to select an appropriate coding parameter
Means for coding the n-th image data by using the coding parameter selected by the selecting means. 2. The image processing apparatus according to claim 1 , further comprising storage means for storing state data indicating a state of said image data, said storage means corresponding to an encoding parameter stored in said encoding information table. In addition to the above, storing state transition destination information indicating the updated value of the corresponding state data, the encoding parameter holding means, as the encoding parameter estimated for the n-th image data,
2. The encoding apparatus according to claim 1 , wherein at least the state transition destination information stored in the encoding information table is held. 3. An adaptation for decoding code data encoded by the encoding device according to claim 1 into original image data.
In type arithmetic decoding apparatus, an encoding information table storing decoding parameters; during decoding processing of image data input to the n-1 th, at least estimated for the n-th image data 2 Two decoding parameters from the decoding information table
Decoding parameter holding means for reading and holding ; when decoding processing of the ( n-1) th image data is completed
In that at least two of the holding means
Selection to select an appropriate one from decoding parameters
Means for decoding the n-th image data using the decoding parameter selected by the selecting means. 4. An encoding / decoding device comprising the encoding device according to claim 1 and the decoding device according to claim 3. 5. An image processing system comprising:
Adaptive arithmetic coding device that encodes as elephant symbols
Means for using a plurality of reference symbols at predetermined positions in a symbol sequence of an information source to generate a context for a symbol to be coded; a state number indicating a state of the context; and a prediction of the symbol to be coded. Storage means for storing values; and context holding means for temporarily holding a plurality of contexts corresponding to a plurality of symbols to be sequentially encoded; and comparing a plurality of contexts held in the context holding means. First comparing means for comparing the predicted value of the encoding target symbol read from the storage means with the actual value of the encoding target symbol; and stored in the storage means. The probability region width corresponding to the state number, state transition destination information indicating an updated value of the state number, and An information table that stores a corresponding second probability region width and second state transition destination information indicating an updated value of the state transition destination; a probability region width read from the information table and the second The encoding of the encoding target symbol is performed based on the result of the comparison by the comparing means of No. 2, and the state number and the context number of the context for the encoding target symbol are determined based on the state transition destination information read from the information table. Arithmetic coding means for updating a predicted value; a first register for holding a state number and a predicted value read from the storage means; and a first register for holding a state number and a predicted value written to the storage means. A third register for holding an output of the second register; and a state number of a context corresponding to the (n-1) th input image data. A fourth register; based on the comparison result of said first comparison means, said first,
A first selector for selecting an output of the second, third, or fourth register; and a second selector for holding a probability region width and state transition destination information of a context corresponding to the (n-1) th input image data. 5
Wherein the information table uses an output of the first selector as an address, and the arithmetic encoding means outputs the n-th input image data as a result of the comparison by the first comparing means. When the context corresponding to (i) is the same as the (n-1) th context, the encoding process of the nth context is performed using the second probability region width and the second state transition destination information. Arithmetic coding device characterized by the above-mentioned. 6. with arithmetic coding apparatus according to claim 5, encoding / decoding device.