JP4994515B2 - Arithmetic coding device, arithmetic decoding device - Google Patents

Description

The present invention, when transmitting and compression encoding an image, the arithmetic code KaSo location of arithmetic coding parameters to be encoded, in which relates the parameter to be decoded in the arithmetic decoding equipment to arithmetic decoding.

For example, H.264 recommended by ITU-T (International Telecommunication Union Telecommunication Standardization Sector). In the arithmetic coding apparatus used in the H.264 video coding system, when encoding the encoding target parameter, the encoding target parameter is converted into binary data, and each binary data is converted into binary data. Perform arithmetic coding as a symbol to be coded. In arithmetic coding, an event that is assumed to have a high occurrence frequency between 0 and 1 in binary data in each symbol is represented by MPS (Most Probable Symbol: dominant symbol), and an event that is not represented by LPS ( Least Probable Symbol: Inferior Symbol = Inferior Symbol), and arithmetic coding operation processing is performed according to the “occurrence probability” that is the probability of occurrence of MPS.
Here, since the occurrence probability in each encoded symbol is different, the occurrence probability is stored in a separate memory for each symbol. H. The H.264 video coding system is configured to hold approximately 1000 types of occurrence probabilities.
In addition, the arithmetic coding apparatus refers to the occurrence probability of the symbol and updates the occurrence probability of the symbol when the binary data of the symbol is arithmetically encoded.

That is, in order to improve the coding efficiency, the arithmetic coding device changes the direction in which the occurrence probability of the symbol is increased (learns the occurrence probability) if the symbol that is the occurrence event is MPS.
On the other hand, if the symbol that is the occurrence event is LPS, the occurrence probability of the symbol is changed to be lowered (learning of the occurrence probability).

H. In the H.264 arithmetic coding apparatus, it is possible to reduce the capacity of a memory for storing the occurrence probability of each symbol and the amount of calculation when learning the occurrence probability of each symbol by using the state transition diagram of the occurrence probability. .
Here, FIG. 13 is an explanatory diagram illustrating an example of a state transition diagram of occurrence probabilities used by the arithmetic coding apparatus.
Moreover, FIG. 14 is explanatory drawing which shows the value expressing the probability in each state.
13 and 14, pStateIdx is the transition state index, transIdrLPS is the transition state index of the next state when the symbol that is the occurrence event is LPS, and transIdrMPS is the next state when the symbol that is the occurrence event is MPS The transition state index is shown.
Further, qCodIRRangeIdx is a value representing the probability, and in the example of FIG. 14, is a value approximating the reciprocal of the occurrence probability.

FIG. 15 is an explanatory diagram showing the principle of arithmetic coding in the arithmetic coding device.
In FIG. 15, when MPS = 0, the probability of occurrence of MPS is 0.75, and the probability of occurrence of LPS is 0.25, the input binary string “0001” is arithmetically encoded, and the output binary of “011” is obtained. Shows an example of arithmetic coding.

FIG. 16 is an explanatory diagram showing a moving image to be encoded.
In the moving image of FIG. 16, the car is moving leftward. In the figure, in the thick-lined block, the background is only the background up to the previous block in the coding order (raster scan order). Since the head of is approaching, it is a block that is different in nature from the previous block.
FIG. 17 shows first binary data as binarized MVD (Motion Vector Difference: motion vector difference value), which is an encoding parameter indicating, for example, block motion information as a specific encoding target symbol. And the second binary data that is the first binary data when binarizing CBP (Coded Block Pattern) which is an encoding parameter indicating whether or not an orthogonal transform coefficient exists in the block. The amount of information for each block is illustrated by paying attention to the symbol.
Here, since the orthogonal transform coefficient is likely to be generated when the motion is large and the orthogonal transform coefficient is difficult to be generated when the motion is small, there is a correlation between the occurrence probability of the MPS of the first symbol and the second symbol. is there.
From FIG. 17, since blocks having the same nature as the background image are encoded between several blocks from the beginning, the generated symbols are always MPS, and the amount of generated information for each symbol gradually decreases due to the learning effect of the occurrence probability. Go.
In this way, when the occurrence probability learning is sufficiently performed, when arithmetic coding is performed on a block having different properties such as a thick frame block in the figure, an occurrence event becomes LPS depending on the symbol. For example, as shown in FIG. Therefore, the amount of generated information of the encoding target symbol increases rapidly.

  For example, in the arithmetic coding device disclosed in Patent Document 1 below, the probability of occurrence of each symbol using a predetermined mathematical formula based on the quantization scale at the beginning of a slice in order to enhance error tolerance and improve coding efficiency (Transition state index) is initialized, and the occurrence probability is learned in accordance with the occurrence event of each symbol in the slice (state transition is performed).

Japanese Patent No. 4211873

  Since the conventional arithmetic coding apparatus is configured as described above, when the amount of generated symbol information increases rapidly in the middle of slicing, it cannot follow the change, and other correlated symbols cannot be tracked. The amount of generated information also increases, resulting in an increase in the total code amount.

The present invention has been made to solve the above problems, and quickly suppress the generation amount of information symbols, and arithmetic coding apparatus capable of enhancing the coding efficiency, the arithmetic coding device and to obtain the arithmetic decoding equipment capable of correctly decoding the coding efficiency is enhanced symbol.

The arithmetic coding apparatus according to the present invention refers to the occurrence probability of the first symbol stored in the occurrence probability storage means and performs arithmetic operation on the binarized data of the first symbol output from the binarization means. After encoding, the binarized data of the second symbol output from the binarizing means is arithmetically encoded with reference to the occurrence probability of the second symbol stored in the occurrence probability storing means, and Arithmetic coding operation processing means for updating the occurrence probabilities of the first and second symbols stored in the occurrence probability storage means is provided, and the occurrence probability initialization means outputs the first symbol output from the binarization means. It is determined whether or not the steady state of the binarized data is interrupted. If the steady state is interrupted, before arithmetic coding of the binarized data of the second symbol is performed by the arithmetic coding arithmetic processing means. , Probability of occurrence And a probability initializing means for initializing the occurrence probability of the second symbol stored by憶means, the occurrence probabilities initializing means 2 value of the first symbol output from the binarizing means When the binarized data is an inferior symbol and the occurrence probability of the first symbol stored in the occurrence probability storage means is equal to or greater than a predetermined threshold, the steady state of the binarized data of the first symbol is interrupted It is determined that it is.

According to this invention, the binarized data of the first symbol output from the binarizing means is arithmetically encoded with reference to the occurrence probability of the first symbol stored in the occurrence probability storing means. The binarized data of the second symbol output from the binarizing means is arithmetically encoded with reference to the occurrence probability of the second symbol stored in the occurrence probability storing means, and the occurrence probability storing means 2 includes arithmetic coding operation processing means for updating the occurrence probabilities of the first and second symbols stored in the above, and the occurrence probability initialization means outputs binarized data of the first symbol output from the binarization means. If the steady state is interrupted, if the steady state is interrupted, the occurrence probability memory is stored before the arithmetic coding of the binary data of the second symbol is performed by the arithmetic coding operation processing means. By means And a probability initializing means for initializing the occurrence probability of the second symbol being 憶, the occurrence probabilities initialization means, binary data of the first symbol output from the binarizing means If the occurrence probability of the first symbol that is an inferior symbol and is stored by the occurrence probability storage means is greater than or equal to a predetermined threshold, the steady state of the binarized data of the first symbol is interrupted Since the determination is made, there is an effect that the amount of information generated in the second symbol can be quickly suppressed and the encoding efficiency can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the moving image encoding apparatus by which the arithmetic encoding apparatus by Embodiment 1 of this invention is mounted. It is a block diagram which shows the entropy encoding part 11 which is the arithmetic encoding apparatus by Embodiment 1 of this invention. It is a flowchart which shows the processing content of the moving image encoding apparatus by which the arithmetic encoding apparatus by Embodiment 1 of this invention is mounted. It is a flowchart which shows the processing content of the entropy encoding part 11 which is the arithmetic encoding apparatus by Embodiment 1 of this invention. It is a flowchart which shows the determination process of the state reset determination part 26 in the entropy encoding part 11. FIG. It is explanatory drawing which shows the fluctuation | variation of the generation information amount of two symbols with a correlation. It is a block diagram which shows the entropy encoding part 11 which is the arithmetic encoding apparatus by Embodiment 3 of this invention. It is a block diagram which shows the moving image decoding apparatus by which the arithmetic decoding apparatus by Embodiment 4 of this invention is mounted. It is a block diagram which shows the entropy decoding part 31 which is the arithmetic decoding apparatus by Embodiment 4 of this invention. It is a flowchart which shows the processing content of the moving image decoding apparatus by which the arithmetic decoding apparatus by Embodiment 4 of this invention is mounted. It is a flowchart which shows the processing content of the entropy decoding part 31 which is an arithmetic decoding apparatus by Embodiment 4 of this invention. It is a block diagram which shows the entropy decoding part 31 which is the arithmetic decoding apparatus by Embodiment 6 of this invention. It is explanatory drawing which shows an example of the state transition diagram of the occurrence probability which an arithmetic coding apparatus uses. It is explanatory drawing which shows the value expressing the probability in each state. It is explanatory drawing which shows the principle of the arithmetic encoding in an arithmetic encoding apparatus. It is explanatory drawing which shows the moving image of encoding object. It is explanatory drawing which shows the fluctuation | variation of the generation information amount of two symbols with a correlation.

Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a moving picture coding apparatus in which an arithmetic coding apparatus according to Embodiment 1 of the present invention is mounted.
In FIG. 1, an image input unit 1 inputs a moving image to be encoded, divides the moving image into units of macroblocks, and images of each divided macroblock (hereinafter referred to as “macroblock images”). Is executed.
The intra prediction unit 2 performs intra prediction, thereby generating a prediction image from a locally decoded image stored in the frame memory 10 to be described later, and performing a process of outputting a prediction mode of intra prediction to the entropy encoding unit 11 To do.

The motion compensation prediction unit 3 detects a motion vector from the macroblock image output from the image input unit 1 and the reference image stored in the frame memory 10, and performs motion compensation prediction on the reference image using the motion vector. Thus, a process of generating a predicted image and outputting the motion vector to the entropy encoding unit 11 is performed.
The encoding control unit 4 controls the selection switch 5 and performs a process of outputting a control signal and a quantization scale for the selection switch 5 to the entropy encoding unit 11.
According to the control signal output from the encoding control unit 4, the selection switch 5 predicts the prediction image with the higher prediction accuracy among the prediction image generated by the intra prediction unit 2 or the prediction image generated by the motion compensation prediction unit 3. A process of selecting an image is performed.

The subtractor 6 calculates a prediction error signal that is a difference image between the macroblock image output from the image input unit 1 and the prediction image selected by the selection switch 5, and outputs the prediction error signal to the quantization conversion unit 7. Perform the process.
The quantization transform unit 7 orthogonally transforms the prediction error signal output from the subtracter 6, quantizes the orthogonal transform coefficient of the prediction error signal, and converts the orthogonal transform coefficient after quantization to the inverse quantization transform unit 8 and the entropy. Processing to output to the encoding unit 11 is performed.

The inverse quantization transform unit 8 performs inverse quantization on the orthogonal transform coefficient after quantization output from the quantization transform unit 7 and performs inverse orthogonal transform on the orthogonal transform coefficient after inverse quantization to output from the subtractor 6. A process of outputting a prediction error signal corresponding to the predicted error signal to the adder 9 is performed.
The adder 9 performs a process of adding the prediction image selected by the selection switch 5 and the prediction error signal output from the inverse quantization transform unit 8 to generate a local decoded image.
The frame memory 10 is a recording medium that stores the locally decoded image generated by the adder 9 as a reference image.

The entropy encoding unit 11 is an arithmetic encoding apparatus according to Embodiment 1 of the present invention, and is an encoding target parameter (a plurality of parameters having a correlation: for example, a macroblock type, a motion vector difference value, a luminance intraframe prediction). A mode, a color difference intra-frame prediction mode, a CBP (Coded Block Pattern), a difference quantization parameter, and the like are entropy-coded, and a process of outputting encoded data is performed.
In the example of FIG. 1, the prediction mode output from the intra prediction unit 2, the motion vector detected by the motion compensation prediction unit 3, and the quantization scale / control output from the encoding control unit 4 are the encoding target parameters. The signal and the quantized orthogonal transform coefficient information (including CBP) output from the quantization transform unit 7 are entropy coded.

FIG. 2 is a block diagram showing an entropy encoding unit 11 which is an arithmetic encoding apparatus according to Embodiment 1 of the present invention.
In FIG. 2, two symbols (MVD (Motion Vector Difference: motion vector difference value) which is an encoding parameter indicating a motion vector difference value) are binarized data (first bit) when binarized Symbol), the first bit of binarized data (second symbol) when CBP, which is an encoding parameter indicating whether or not a non-zero orthogonal transform coefficient exists in the block, is entropy The description will be made assuming that the encoding is performed.
However, it goes without saying that the number of parameters to be encoded that the entropy encoding unit 11 performs entropy encoding is not limited to two, and may be three or more.
Also, the first symbol is not limited to the first bit of MVD, the second symbol is not limited to the first bit of CBP, and the first symbol is not the first bit of MVD. It goes without saying that the binarized data of the binarization parameter, the binarized data whose second symbol is not the first bit of CBP, or the binarized data of the coding parameter other than CBP may be used.

In FIG. 2, a transition state storage memory 21 is a recording medium that stores a transition state index (see FIG. 13) in a state transition diagram of each symbol to be encoded.
The probability table memory 22 is a recording medium that stores a probability table (see FIG. 14: the probability table of FIG. 14 stores an approximate value of the reciprocal of the occurrence probability) indicating the occurrence probability in each state.
The transition state storage memory 21 and the probability table memory 22 constitute an occurrence probability storage means.
Further, conventional H.264. In H.264, the occurrence probability is updated / stored by using the state transition diagram of FIG. 13 and the probability table of FIG. 14. However, the present invention is not limited to this, and any means can be used as long as the occurrence probability is updated / stored. Even so, the present invention can be applied. For example, a method may be used in which the number of occurrences of binary data of a symbol to be encoded is “0” and the number of times “1” is counted, and the probability is calculated statistically. .

The context generation unit 23 refers to the type signal for identifying the encoding target symbol and information on the peripheral blocks (macroblocks existing around the encoding target macroblock), and is stored in the transition state storage memory 21. A process of selecting a memory area to be referred to by the arithmetic coding arithmetic processing unit 25 from the memory area storing the transition state index assigned to each symbol is executed.
The binarization unit 24 binarizes MVD and CBP, which are parameters to be encoded, and performs processing for outputting the respective binarized data. The binarization unit 24 constitutes binarization means.

  The arithmetic coding arithmetic processing unit 25 refers to the occurrence probability of the first bit of MVD (hereinafter referred to as “MVD1” = first symbol) (memory area allocated to MVD1 selected by the context generation unit 23) (Refer to the transition state index stored in FIG. 2 and the probability table stored in the probability table memory 22), after binarizing data of the first symbol output from the binarizing unit 24 is arithmetically encoded. , With reference to the occurrence probability of the first bit of CBP (hereinafter referred to as “CBP1” = second symbol) (stored in the memory area assigned to the symbol of CBP1 selected by the context generator 23) The transition state index and the probability table stored in the probability table memory 22 are referred to). The binary data of BP1 (second symbol) is arithmetically encoded and the transition state index of MVD1 (first symbol) and CBP1 (second symbol) stored in the transition state storage memory 21 is arithmetically operated. Update processing is performed based on the state transition diagram held by the encoding operation processing unit 25. The arithmetic coding arithmetic processing unit 25 constitutes arithmetic coding arithmetic processing means.

  The state reset determination unit 26 determines whether or not the steady state of the binarized data of the MVD1 (first symbol) output from the binarization unit 24 is interrupted. The current transition state of CBP1 (second symbol) stored in the transition state storage memory 21 before the binarized data of CBP1 (second symbol) is arithmetically encoded by the conversion operation processing unit 25 Perform the process of initializing the index. The state reset determination unit 26 constitutes an occurrence probability initialization unit.

FIG. 3 is a flowchart showing the processing contents of the moving picture coding apparatus in which the arithmetic coding apparatus according to Embodiment 1 of the present invention is mounted.
FIG. 4 is a flowchart showing the processing contents of the entropy encoding unit 11 which is an arithmetic encoding apparatus according to Embodiment 1 of the present invention.
FIG. 5 is a flowchart showing the determination process of the state reset determination unit 26 in the entropy encoding unit 11.

Next, the operation will be described.
When the moving image to be encoded is input, the image input unit 1 divides the moving image into units of macroblocks and outputs the divided macroblock images as macroblock images (step ST1 in FIG. 3). .
When the macroblock image is output from the image input unit 1 and the prediction image is output from the selection switch 5, the subtractor 6 calculates a prediction error signal that is a difference image between the macroblock image and the prediction image, and the prediction The error signal is output to the quantization conversion unit 7 (step ST2).

Upon receiving the prediction error signal from the subtractor 6, the quantization transform unit 7 orthogonally transforms the prediction error signal, quantizes the orthogonal transform coefficient of the prediction error signal, and inverse-quantizes the quantized orthogonal transform coefficient. It outputs to the conversion unit 8 and the entropy encoding unit 11 (step ST3).
Upon receiving the quantized orthogonal transform coefficient from the quantizing transform unit 7, the inverse quantization transform unit 8 performs inverse quantization on the orthogonal transform coefficient after quantization, and performs inverse orthogonal transform on the orthogonal transform coefficient after inverse quantization. Thus, a prediction error signal corresponding to the prediction error signal output from the subtracter 6 is output to the adder 9 (step ST4).

When the intra prediction unit 2 receives the macroblock image from the image input unit 1, the intra prediction unit 2 performs intra prediction (intraframe prediction) to generate a predicted image from the reference image stored in the frame memory, and also performs intra prediction. Are output to the entropy encoding unit 11 (step ST5).
When the motion compensation prediction unit 3 receives a macroblock image from the image input unit 1, the motion compensation prediction unit 3 detects a motion vector from the macroblock image and the reference image stored in the frame memory 10, and uses the motion vector to detect the reference image. By performing motion compensated prediction for, a predicted image is generated and the motion vector is output to the entropy encoding unit 11 (step ST6).

The encoding control unit 4 determines the macroblock mode (step ST7), and the prediction with the higher prediction accuracy among the prediction image generated by the intra prediction unit 2 or the prediction image generated by the motion compensation prediction unit 3 is performed. A control signal for instructing image selection is output to the selection switch 5, and the control signal and the quantization scale are output to the entropy encoding unit 11.
The selection switch 5 selects a prediction image generated by the intra prediction unit 2 or a prediction image generated by the motion compensation prediction unit 3 according to the control signal output from the encoding control unit 4, and the selected prediction image Is output to the subtractor 6.

The entropy encoding unit 11 encodes parameters to be encoded (a plurality of correlated parameters: macroblock type, motion vector difference value, luminance intra-frame prediction mode, chrominance intra-frame prediction mode, CBP (Coded Block Pattern), Entropy encoding is performed on the difference quantization parameter and the like, and encoded data is output (step ST8).
In the example of FIG. 1, the prediction mode output from the intra prediction unit 2, the motion vector detected by the motion compensation prediction unit 3, the quantization scale and the quantum output from the encoding control unit 4 are used as symbols to be encoded. The quantized orthogonal transform coefficient information (including CBP) output from the conversion transform unit 7 is entropy-coded.
In the example of FIG. 1, the control signal for the selection switch 5 is also entropy encoded.

Hereinafter, the processing content of the entropy encoding part 11 is demonstrated concretely.
Here, two symbols (binarized data of the first bit (MVD1 = first symbol) when MVD, which is an encoding parameter indicating a motion vector difference value) is binarized, are non-zero in the block. An example in which entropy encoding is performed on binarized data (CBP1 = second symbol) of the first bit when CBP that is an encoding parameter indicating whether or not an orthogonal transform coefficient exists is binarized Will be described.
When the binarization unit 24 of the entropy encoding unit 11 receives MVD and CBP as parameters to be encoded, the binarization unit 24 binarizes the MVD and CBP, and arithmetically codes the binarized data including the MVD1 and CBP1. The data is output to the conversion calculation processing unit 25 and the state reset determination unit 26 (step ST11 in FIG. 4).

  The context generation unit 23 refers to the type signal for identifying the encoding target symbol and information on the peripheral blocks (macroblocks existing around the encoding target macroblock) and stores them in the transition state storage memory 21. A memory area referred to by the arithmetic coding arithmetic processing unit 25 is selected from the memory area storing the transition state index assigned to each symbol, and context information for identifying the memory area is generated ( Step ST12).

The arithmetic coding arithmetic processing unit 25 is the memory on the transition state storage memory 21 indicated by the context information generated by the context generation unit 23 among the memory areas allocated for each symbol stored in the transition state storage memory 21. By referring to the transition state index stored in the memory area allocated to the encoding target symbol (step ST13) and referring to the probability table stored in the probability table memory 22, the encoding target symbol The occurrence probability is specified (step ST14).
When the arithmetic coding arithmetic processing unit 25 specifies the occurrence probability of MVD1 (first symbol), the arithmetic coding unit 25 refers to the occurrence probability and arithmetically encodes the binarized data of MVD1 output from the binarizing unit 24. (Step ST15).
Next, the arithmetic coding arithmetic processing unit 25 compares the current transition state index of MVD1 (first symbol) with the state transition diagram, and specifies the next transition state index of MVD1 (first symbol). The transition state index stored in the memory area assigned to MVD1 in the transition state storage memory 21 is updated to the specified next transition state index. (Step ST16).

For example, when the current transition state index of MVD1 (first symbol) is “7” and the binarized data of MVD1 (first symbol) is MPS (dominant symbol), the next transition state index Is identified as “8” (see FIG. 13).
On the other hand, when the current transition state index of MVD1 (first symbol) is “7”, if MVD1 (first symbol) is binary data LPS (inferior symbol), the next transition state index Is identified as “5” (see FIG. 13).

That is, when the arithmetic coding arithmetic processing unit 25 arithmetically encodes the binarized data of MVD1 (first symbol), the current transition state of MVD1 (first symbol) stored in the transition state storage memory 21. Update the index.
When the arithmetic coding arithmetic processing unit 25 updates the transition state index of MVD1 (first symbol), it outputs encoded data that is the result of arithmetic coding of the binary data of MVD1 (first symbol) ( Step ST17).

When the arithmetic coding arithmetic processing unit 25 outputs the encoded data related to MVD1 (first symbol), the state reset determining unit 26 binarizes CBP1 (second symbol) by the arithmetic coding arithmetic processing unit 25. Before the arithmetic coding operation of data is performed, it is determined whether or not the steady state of the binarized data of the MVD1 (first symbol) is interrupted (step ST18).
That is, as shown in FIG. 5, the state reset determination unit 26 breaks the steady state of the binarized data of MVD1 (first symbol) when all of the following three conditions are satisfied (steps ST21 to ST23). If any of the following conditions is not satisfied (steps ST21 to ST23), it is determined that the steady state of the binarized data of MVD1 (first symbol) is not interrupted (step ST24). Step ST25).

Condition (1) The occurrence probability of MPS specified by the transition state index of MVD1 (first symbol) before being updated this time by the arithmetic coding arithmetic processing unit 25 is not less than a first threshold (for example, 0.875). It is.
(2) The binarized data of MVD1 (first symbol) output from the binarizing unit 24 is the inferior symbol LPS.
(3) The occurrence probability of MPS specified by the transition state index of CBP1 (second symbol) before being updated this time by the arithmetic coding arithmetic processing unit 25 is not less than a second threshold (for example, 0.75). is there.

  Here, the condition that the MPS occurrence probability of CBP1 (second symbol) before being updated this time by the arithmetic coding arithmetic processing unit 25 is equal to or higher than a second threshold (for example, 0.75) is also included in the condition. However, it may be determined whether or not the steady state is interrupted only by the above conditions (1) and (2). In this case, although the determination accuracy is somewhat lowered, it can be determined with a small amount of processing whether or not the steady state is interrupted.

When the state reset determination unit 26 determines that the steady state of the binarized data of MVD1 (first symbol) is interrupted, the arithmetic coding arithmetic processing unit 25 performs binarized data of CBP1 (second symbol). Before the arithmetic coding calculation process is performed, the current transition state index of CBP1 (second symbol) stored in the transition state storage memory 21 is initialized (step ST19).
For example, by resetting the current transition state index of CBP1 (second symbol) to an initial value (for example, transition state index “0” or transition state index = “n” (n is an arbitrary value)) The occurrence probability of CBP1 (second symbol) is reset to an initial value (for example, “0.5” or “x” (x is an arbitrary value)).

When the determination process of the state reset determination unit 26 ends, the arithmetic coding calculation processing unit 25 performs the occurrence probability of CBP1 (second symbol) in the same manner as when the occurrence probability of MVD1 (first symbol) is specified. Is identified.
That is, the arithmetic coding arithmetic processing unit 25 refers to the current transition state index of CBP1 (second symbol) stored in the transition state storage memory 21 and uses the probability table stored in the probability table memory 22 to The occurrence probability of CBP1 (second symbol) is specified.

When the occurrence probability of CBP1 (second symbol) is specified, the arithmetic coding arithmetic processing unit 25 refers to the occurrence probability in the same manner as when the binary data of MVD1 (first symbol) is arithmetically coded. Then, the binary data of CBP1 (second symbol) output from the binarization unit 24 is arithmetically encoded.
When the binary coding data of CBP1 (second symbol) is arithmetically coded, the arithmetic coding arithmetic processing unit 25 performs the transition state storage memory similarly to the case of updating the transition state index of MVD1 (first symbol). 21. Update the transition state index of CBP1 (second symbol) stored in 21.
When the arithmetic coding operation processing unit 25 updates the transition state index of CBP1 (second symbol), the arithmetic coding operation processing unit 25 outputs encoded data that is an arithmetic coding result of the binary data of CBP1 (second symbol).

  However, when it is determined by the state reset determination unit 26 that the steady state of the binarized data of MVD1 (first symbol) is interrupted, it is stored in the transition state storage memory 21 as described above. Since the transition state index of CBP1 (second symbol) is reset to the initial value, the steady state of the binarized data of MVD1 (first symbol) is interrupted, thereby generating MVD1 (first symbol). Even if the amount of information increases rapidly, an increase in the amount of generated information of CBP1 (second symbol) correlated with MVD1 (first symbol) is suppressed.

Here, FIG. 6 is an explanatory diagram showing fluctuations in the amount of generated information of two correlated symbols.
In the example of FIG. 6, when the unpredictable block is encoded, the steady state of the binarized data of MVD1 (first symbol) is interrupted, so that the amount of generated information of MVD1 (first symbol) increases rapidly. However, when the current transition state index of CBP1 (second symbol) is reset to the initial value, the amount of generated information of CBP1 (second symbol) correlated with MVD1 (first symbol) It is shown that the increase of is suppressed.
Incidentally, when the transition state index of CBP1 (second symbol) is not reset to the initial value, the amount of generated information of CBP1 (second symbol) increases rapidly as shown in FIG.

In the first embodiment, an example in which MVD1 (first symbol) and CBP1 (second symbol) are implemented as correlated symbols is shown, but the correlated symbols will be briefly described below.
For example, H.M. In H.264, a macroblock mode that specifies a coding mode of a macroblock (whether intraframe prediction or interframe prediction is used, or the unit of intraframe prediction is any of 4 × 4, 8 × 8, and 16 × 16 images). Or information indicating whether the motion vector transmission unit is 16 × 16, 16 × 8, 8 × 16, 8 × 8 or less), and all the macroblocks are reconstructed with only predicted values. A skip flag for specifying whether or not a skip mode is selected, a differential motion vector for specifying motion (a difference value between a motion vector prediction value and an actual motion vector), CBP indicating the presence or absence of each block of prediction difference information, and luminance Signal intra-frame prediction mode, color difference signal intra-frame prediction mode, difference quantization parameter that is the difference of quantization parameter from previous macroblock, prediction error signal Encoding the coding parameters such as exchange transform coefficients as the macro block data.

Prediction is easy in a portion where there is little change in motion or texture, such as the background portion of the screen, so the probability of selecting the skip mode increases. Furthermore, since there is little change in motion and texture, the block size tends to be large for intra-frame prediction and motion prediction. Therefore, the probability of selecting a mode for processing in units of 16 × 16 pixels is selected as the macroblock mode. Becomes higher.
In addition, since there is no change in the image signal, the probability that the difference motion vector becomes 0 increases. Since it is difficult for the CBP to generate the prediction difference information, the probability of becoming 0 becomes high.
In the intra-frame prediction mode, neither the luminance nor the color difference changes so much in any prediction mode, so the probability that the intra-frame prediction mode is the same as that of an adjacent block increases. Since there is no change in the differential quantization parameter, the probability of becoming 0 is increased.

On the other hand, in a macro block including a moving object or a macro block having a complicated texture, the probability that the skip mode is not selected increases. Since the encoding efficiency is improved when the predicted pixels are finely generated in accordance with the movement or texture change, the macroblock type has a higher probability of having a smaller block size. Also, the difference motion vector naturally has a higher probability of becoming a non-zero value.
As for the intra-frame prediction mode, the probability that various modes are selected according to the texture increases.
The difference quantization parameter also has a higher probability of not being 0 because the quantization parameter is changed to a large value in order to suppress the code amount.

  Therefore, each binarized data when binarizing encoding parameters such as a macroblock mode, a skip flag, a motion vector difference value, CBP, a luminance intraframe prediction mode, a chrominance intraframe prediction mode, and a differential quantization parameter is When any one of the first symbols is selected and one or more of the other symbols is used as the second symbol, and the present invention is applied, both the first symbol and the second symbol are MPS. If the first symbol changes to LPS when the state of high probability continues, the second symbol is likely to change to LPS at the same time, so the occurrence probability of the second symbol is initialized. By doing so, the amount of information generated in the second symbol can be suppressed, and encoding with high encoding efficiency can be realized.

  As is apparent from the above, according to the first embodiment, the binary of MVD1 (first symbol) output from the binarization unit 24 with reference to the occurrence probability of MVD1 (first symbol) After the encoded data is arithmetically encoded, the binary data of CBP1 (second symbol) output from the binarization unit 24 is arithmetically encoded with reference to the occurrence probability of CBP1 (second symbol). In addition, an arithmetic coding arithmetic processing unit 25 that updates the transition state index of MVD1 (first symbol) and CBP1 (second symbol) stored in the transition state storage memory 21 is provided, and the state reset determination unit 26 It is determined whether the steady state of the binarized data of MVD1 (first symbol) output from the binarizing unit 24 is interrupted. If the steady state is interrupted, the arithmetic coding operation processing unit 25 Before the arithmetic coding of the binary data of CBP1 (second symbol) is performed, the transition state index of CBP1 (second symbol) stored in the transition state storage memory 21 is initialized. Since it comprised, there exists an effect which can suppress the generation | occurrence | production information amount of CBP1 (2nd symbol) rapidly, and can improve encoding efficiency.

Embodiment 2. FIG.
In the first embodiment, the state reset determination unit 26 determines whether or not the steady state of the binarized data of the MVD1 (first symbol) output from the binarization unit 24 is interrupted, and the steady state is If there is a break, before the arithmetic coding of the binary data of CBP1 (second symbol) is performed by the arithmetic coding arithmetic processing unit 25, CBP1 (second symbol) stored in the transition state storage memory 21 is stored. The symbol (transition state) of the transition state index is shown. When the steady state of the binary data of MVD1 (first symbol) is interrupted, the CBP1 (first order) stored in the transition state storage memory 21 is displayed. Instead of initializing the transition state index of 2 symbols), MPS (dominant symbol) and LPS (inferior) in the binary data of CBP1 (second symbol) The meaning of symbols) may be reversed.

Also, the transition state index of CBP1 (second symbol) may be forcibly transitioned to a transition state index that transitions when one or more LPS (inferior symbols) are received. In this case, the effect of reversing the meanings of MPS and LPS cannot be obtained, but the processing to be updated using the state transition diagram can be diverted, so that it is not necessary to increase the circuit scale.
Also in these cases, similarly to the first embodiment, it is possible to quickly suppress the amount of information generated in CBP1 (second symbol) and increase the coding efficiency.

Embodiment 3 FIG.
FIG. 7 is a block diagram showing an entropy encoding unit 11 which is an arithmetic encoding apparatus according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG.
Similarly to the transition state storage memory 21 in FIG. 2, the transition state storage memory 27 is a recording medium that stores the current transition state index of each symbol of each symbol to be encoded. As in the storage memory 21, the current transition state index of CBP1 (second symbol) is not initialized by the state reset determination unit 26. For example, the intra prediction unit 2 and the motion compensation prediction unit 3 When the transition state reset flag (state transition information) indicating that the steady state of the binarized data of the MVD1 (first symbol) output from the binarization unit 24 is interrupted is received, the arithmetic coding calculation processing unit 25 MVD1 (first symbol) and CB before arithmetic coding of the binary data of MVD1 (first symbol) and CBP1 (second symbol) is performed. It is different 1 the current transition state index (second symbol) at the point to be initialized.
The transition state storage memory 27 constitutes an occurrence probability storage unit and an occurrence probability initialization unit.

Next, the operation will be described.
Since the intra prediction unit 2 (or the motion compensation prediction unit 3) analyzes the unpredictable block when generating a predicted image in a block (referred to as an unpredictable block) having a different property from the previously encoded block, It can be determined whether or not the steady state of the binarized data of MVD1 (first symbol) in the disabled block is interrupted.
If the intra prediction unit 2 (or motion compensation prediction unit 3) determines that the steady state of the binarized data of the MVD1 (first symbol) in the unpredictable block is interrupted, it indicates that the steady state is interrupted. The transition state reset flag shown is output to the transition state storage memory 27 of the entropy encoding unit 11.

When the transition state storage memory 27 receives the transition state reset flag from the intra prediction unit 2 (or motion compensation prediction unit 3), the arithmetic coding arithmetic processing unit 25 performs MVD1 (first symbol) and CBP1 (second symbol). Before the arithmetic coding of the binary data of (symbol) is performed, the current transition state index of MVD1 (first symbol) and CBP1 (second symbol) is initialized.
In this case, before arithmetic coding of the binary data of MVD1 (first symbol) is performed by the arithmetic coding arithmetic processing unit 25, the transition state storage memory 27 stores the binary value of MVD1 (first symbol). Since it is possible to recognize that the steady state of the data is interrupted, not only the current transition state index of CBP1 (second symbol) but also the current transition of MVD1 (first symbol) The state index is also initialized.
Since other processing contents are the same as those in the first embodiment, description thereof is omitted.

  As is apparent from the above, according to the third embodiment, the transition state reset indicating that the steady state of the binarized data of the MVD1 (first symbol) output from the binarization unit 24 is interrupted. When the flag is received, the transition state storage memory 27 performs MVD1 before arithmetic coding of the binary data of MVD1 (first symbol) and CBP1 (second symbol) is performed by the arithmetic coding arithmetic processing unit 25. Since the current transition state index of (first symbol) and CBP1 (second symbol) is initialized, the amount of generated information of MVD1 (first symbol) and CBP1 (second symbol) is There is an effect that it is possible to quickly suppress and increase the encoding efficiency.

Embodiment 4 FIG.
FIG. 8 is a block diagram showing a moving picture decoding apparatus in which an arithmetic decoding apparatus according to Embodiment 4 of the present invention is mounted.
In FIG. 8, an entropy decoding unit 31 is an arithmetic decoding device according to Embodiment 4 of the present invention. When the encoded data transmitted from the entropy encoding unit 11 in FIG. 1 is received, from the encoded data, for example, , A macroblock mode for specifying a coding mode of a macroblock (whether intraframe prediction or interframe prediction is used, or the unit of intraframe prediction is any of 4 × 4, 8 × 8, and 16 × 16 images) Or information indicating which unit of motion vector transmission is 16 × 16, 16 × 8, 8 × 16, 8 × 8 or less), and all macroblocks are reconfigured with only predicted values. A skip flag for specifying whether or not the mode is selected, a difference motion vector for specifying motion (a difference value between a motion vector prediction value and an actual motion vector), and a prediction difference information block CBP indicating the presence / absence of each block, luminance signal intra-frame prediction mode, chrominance signal intra-frame prediction mode, differential quantization parameter that is a difference in quantization parameter from the previous macroblock, orthogonal transform coefficient of prediction error signal Etc. are subjected to entropy decoding and output as decoding parameters.
In the example of FIG. 8, the prediction mode output from the intra prediction unit 2, the motion vector detected by the motion compensation prediction unit 3, the quantization scale and quantization output from the encoding control unit 4 are the decoding target parameters. The quantized orthogonal transform coefficient output from the transform unit 7 is entropy decoded.
In the example of FIG. 8, the control signal for the selection switch 5 is also entropy decoded.

The inverse quantization transform unit 32 performs inverse quantization on the orthogonal transform coefficient after quantization entropy-decoded by the entropy decoding unit 31, and performs inverse orthogonal transform on the orthogonal transform coefficient after the inverse quantization, so that the subtractor of FIG. A process of calculating a prediction error signal corresponding to the prediction error signal output from 6 is performed.
The intra prediction image generation unit 33 performs intra prediction according to the prediction mode of the intra prediction entropy decoded by the entropy decoding unit 31, so that a prediction image corresponding to the prediction image generated by the intra prediction unit 2 of FIG. 1 is obtained. Perform the process to generate.

The motion compensation unit 34 performs motion compensation prediction on the reference image stored in the frame memory 37 using the motion vector entropy-decoded by the entropy decoding unit 31, thereby generating the motion compensation prediction unit 3 in FIG. 1. A process of generating a predicted image corresponding to the predicted image that has been performed is performed.
The selection switch 35 performs a process of selecting the prediction image generated by the intra prediction image generation unit 33 or the motion compensation unit 34 according to the control signal for the selection switch 5 of FIG. 1 entropy decoded by the entropy decoding unit 31.

The adder 36 adds the prediction error signal calculated by the inverse quantization conversion unit 32 and the prediction image selected by the selection switch 35, and corresponds to a macro block image output from the image input unit 1 in FIG. A process of outputting a block image is performed.
The frame memory 37 is a recording medium that stores the macroblock image generated by the adder 36 as a reference image.

FIG. 9 is a block diagram showing an entropy decoding unit 31 which is an arithmetic decoding device according to Embodiment 4 of the present invention.
In FIG. 9, two symbols (MVD1 (first symbol) that is binary data of the first bit when MVD that is an encoding parameter indicating a motion vector difference value is binarized, and non-zero in the block It is assumed that CBP1 (second symbol), which is binary data of the first bit when CBP, which is an encoding parameter indicating whether or not an orthogonal transform coefficient exists, is binarized, is entropy-decoded. To do.
However, it goes without saying that the number of parameters to be decoded that the entropy decoding unit 31 performs entropy decoding is not limited to two, and may be three or more.
Also, the first symbol is not limited to the first bit of MVD, the second symbol is not limited to the first bit of CBP, and the first symbol is not the first bit of MVD. It goes without saying that the binarized data of the binarization parameter, the binarized data whose second symbol is not the first bit of CBP, or the binarized data of the coding parameter other than CBP may be used.

9, the transition state storage memory 41 is a recording medium that stores the transition state index in the state transition diagram of each symbol, similarly to the transition state storage memory 21 of FIG.
Like the probability table memory 22 in FIG. 2, the probability table memory 42 is a probability table indicating the occurrence probability in each state (see FIG. 14: the probability table in FIG. 14 stores an approximate value of the reciprocal of the occurrence probability. ) Is stored.
The transition state storage memory 41 and the probability table memory 42 constitute an occurrence probability storage means.
Further, conventional H.264. In H.264, the occurrence probability is updated / stored by using the state transition diagram of FIG. 13 and the probability table of FIG. 14. However, the present invention is not limited to this, and any means can be used as long as the occurrence probability is updated / stored. Even so, the present invention can be applied. For example, a method may be used in which the probability is statistically calculated by counting the number of occurrences of the decoded symbol binarized data “0” and the number of times “1”.

  The context generation unit 43 refers to the type signal for identifying the symbol to be decoded and information on the peripheral blocks (macroblocks existing around the macroblock to be decoded), and is stored in the transition state storage memory 41. A process of selecting a state transition diagram referred to by the arithmetic decoding arithmetic processing unit 44 from the memory area storing the transition state index assigned for each symbol is performed.

  The arithmetic decoding calculation processing unit 44 refers to the occurrence probability of the MVD1 (first symbol) (the state stored in the memory area on the transition state storage memory 41 assigned to the MVD1 selected by the context generation unit 43) (Refer to the transition index and the probability table stored in the probability table memory 42), the binary data of MVD1 (first symbol) is arithmetically decoded, and the occurrence probability of CBP1 (second symbol) is calculated. Referring to the state transition index stored in the memory area on the transition state storage memory 41 assigned to the symbol of CBP1 selected by the context generation unit 43 and the probability table stored in the probability table memory 42 The binary data of CBP1 (second symbol) is arithmetically decoded, Processing for updating transition state indexes of MVD1 (first symbol) and CBP1 (second symbol) stored in the transition state memory 41 based on a state transition diagram held by the arithmetic decoding arithmetic processing unit 44 To implement. The arithmetic decoding arithmetic processing unit 44 constitutes arithmetic decoding arithmetic processing means.

The state reset determination unit 45 determines whether or not the steady state of the binarized data of the MVD (first symbol) arithmetically decoded by the arithmetic decoding arithmetic processing unit 44 is interrupted, and if the steady state is interrupted, The current transition state of CBP1 (second symbol) stored in the transition state storage memory 41 before the arithmetic decoding of the binary data of CBP1 (second symbol) is performed by the arithmetic decoding arithmetic processing unit 44. Perform the process of initializing the index. The state reset determination unit 45 constitutes an occurrence probability initialization unit.
The inverse binarization unit 46 binarizes the binarized data including the MVD1 (first symbol) and the binarized data including the CBP1 (second symbol), which are arithmetically decoded by the arithmetic decoding arithmetic processing unit 44. Thus, a process of outputting MVD and CBP which are parameters to be decoded as a decoding result is performed. The inverse binarization unit 46 constitutes an inverse binarization unit.

FIG. 10 is a flowchart showing the processing contents of the moving picture decoding apparatus in which the arithmetic decoding apparatus according to the fourth embodiment of the present invention is mounted.
FIG. 11 is a flowchart showing the processing contents of the entropy decoding unit 31 which is an arithmetic decoding device according to Embodiment 4 of the present invention.

Next, the operation will be described.
The arithmetic decoding apparatus according to the fourth embodiment is an apparatus that decodes an image by correctly decoding symbols whose encoding efficiency has been increased by the arithmetic encoding apparatus of FIG.
When receiving the encoded data transmitted from the entropy encoding unit 11 in FIG. 1, the entropy decoding unit 31 decodes and outputs a plurality of correlated parameters from the encoded data (step ST31 in FIG. 10).
That is, the entropy decoding unit 31 receives the prediction mode output from the intra prediction unit 2 in FIG. 1, the motion vector difference value that is the prediction difference value of the motion vector detected by the motion compensation prediction unit 3, The output quantization scale, the orthogonal transform coefficient information (including CBP) output from the quantization conversion unit 7 and the control signal for the selection switch 5 are entropy decoded.
Details of processing contents of the entropy decoding unit 31 will be described later.

When the entropy decoding unit 31 entropy-decodes the quantized orthogonal transform coefficient, the inverse quantization transform unit 32 dequantizes the quantized orthogonal transform coefficient and performs inverse orthogonal transform on the orthogonal transform coefficient after dequantization. Thus, a prediction error signal corresponding to the prediction error signal output from the subtracter 6 of FIG. 1 is calculated (step ST32).
When the entropy decoding unit 31 entropy decodes the prediction mode of intra prediction, the intra prediction image generation unit 33 performs intra prediction (intraframe prediction) according to the prediction mode of the intra prediction, so that the intra prediction unit of FIG. A prediction image corresponding to the prediction image generated in step 2 is generated (step ST33).

When the entropy decoding unit 31 entropy decodes the motion vector, the motion compensation unit 34 performs motion compensation prediction on the reference image stored in the frame memory 37 using the motion vector, thereby performing the motion compensation of FIG. A prediction image corresponding to the prediction image generated by the prediction unit 3 is generated (step ST34).
When the entropy decoding unit 31 entropy decodes the control signal for the selection switch 5 in FIG. 1, the selection switch 35 selects the prediction image generated by the intra prediction image generation unit 33 or the motion compensation unit 34 according to the control signal. .
The adder 36 adds the prediction error signal calculated by the inverse quantization conversion unit 32 and the prediction image selected by the selection switch 35, and corresponds to the macroblock image output from the image input unit 1 in FIG. The macro block image is stored in the frame memory 37, and the macro block image is output to the outside (step ST35).

Hereinafter, the processing content of the entropy decoding part 31 is demonstrated concretely.
Here, two symbols (MVD1 (first symbol) which is binary data of the first bit when MVD which is an encoding parameter indicating a motion vector difference value is binarized, and non-zero orthogonal in the block As an example, entropy decoding is performed on CBP1 (second symbol) which is binarized data of the first bit when CBP which is an encoding parameter indicating whether or not a transform coefficient exists is binarized. explain.
The context generation unit 43 refers to the type signal for identifying the symbol to be decoded and the information about the peripheral block (the macro block existing around the macro block to be decoded), and is stored in the transition state storage memory 41. A memory area referred to by the arithmetic decoding operation processing unit 44 is selected from memory areas allocated on the transition state storage memory 41 to store a transition state index for each symbol, and the memory area is identified. Context information is generated (step ST41 in FIG. 11).

The arithmetic decoding arithmetic processing unit 44 is the code on the transition state storage memory 41 indicated by the context information generated by the context generation unit 43 in the memory area allocated for each symbol stored in the transition state storage memory 42. By referring to the transition state index stored in the memory area allocated to the conversion target symbol (step ST42) and referring to the probability table stored in the probability table memory 42, the occurrence probability of the decoding target symbol is determined. Identify. (Step ST43)
When the occurrence probability of MVD1 (first symbol) is specified, the arithmetic decoding calculation processing unit 44 refers to the occurrence probability and arithmetically decodes the binarized data of MVD1 (first symbol) (step ST44). .

Next, similarly to the arithmetic coding arithmetic processing unit 25 in FIG. 2, the arithmetic decoding arithmetic processing unit 44 compares the current transition state index of MVD1 (first symbol) with the state transition diagram, and sets the MVD1 (first (1 symbol) next transition state index is specified, and the transition state index stored in the memory area assigned to MVD1 in the transition state storage memory 41 is updated to the specified next transition state index (step ST45).
When the arithmetic decoding arithmetic processing unit 44 arithmetically decodes the binarized data including MVD1 (first symbol), the inverse binarizing unit 46 performs inverse binarization on the binarized data (step ST46), and performs decoding. MVD is output as a parameter (step ST47).

When the arithmetic decoding arithmetic processing unit 44 arithmetically decodes the binarized data of MVD1 (first symbol), the state reset determination unit 45 performs the MVD1 (first symbol) as in the state reset determination unit 26 of FIG. ) Is determined whether the steady state of the binarized data is interrupted (step ST48).
That is, as shown in FIG. 5, the state reset determination unit 45 breaks the steady state of the binarized data of MVD1 (first symbol) when all of the following three conditions are satisfied (steps ST21 to ST23). If any of the following conditions is not satisfied (steps ST21 to ST23), it is determined that the steady state of the binarized data of MVD1 (first symbol) is not interrupted (step ST24). Step ST25).

Condition (1) The occurrence probability of MPS specified by the transition state index of MVD1 (first symbol) before being updated this time by the arithmetic decoding arithmetic processing unit 44 is not less than a first threshold (for example, 0.875). is there.
(2) The binarized data of MVD1 (first symbol) arithmetically decoded by the arithmetic decoding arithmetic processing unit 44 is the inferior symbol LPS.
(3) The occurrence probability of MPS specified by the transition state index of CBP1 (second symbol) before being updated this time by the arithmetic decoding arithmetic processing unit 44 is equal to or higher than a second threshold (for example, 0.75). .

  Here, it is also included in the condition that the MPS occurrence probability of CBP1 (second symbol) before being updated this time by the arithmetic decoding arithmetic processing unit 44 is equal to or higher than a second threshold (for example, 0.75). However, it may be determined whether or not the steady state is interrupted only by the above conditions (1) and (2). In this case, although the determination accuracy is somewhat lowered, it can be determined with a small amount of processing whether or not the steady state is interrupted.

  When the state reset determination unit 45 determines that the steady state of the binarized data of MVD1 (first symbol) is interrupted, the arithmetic decoding operation processing unit 44 performs CBP1 similarly to the state reset determination unit 26 of FIG. Before the arithmetic decoding of the binarized data of (second symbol) is performed, the current transition state index of CBP1 (second symbol) stored in transition state storage memory 41 is initialized (step ST49). ).

When the determination process of the state reset determination unit 45 ends, the arithmetic decoding calculation processing unit 44 determines the occurrence probability of CBP1 (second symbol) in the same manner as when the occurrence probability of MVD1 (first symbol) is specified. Identify.
That is, the arithmetic decoding arithmetic processing unit 44 refers to the current transition state index of CBP1 (second symbol) stored in the transition state storage memory 41, and calculates CBP1 from the probability table stored in the probability table memory 42. The occurrence probability of (second symbol) is specified.

When the occurrence probability of CBP1 (second symbol) is specified, the arithmetic decoding operation processing unit 44 refers to the occurrence probability as in the case of arithmetic decoding of the binarized data of MVD1 (first symbol). , CBP1 (second symbol) binarized data is arithmetically decoded.
When the arithmetic decoding operation unit 44 arithmetically decodes the binary data of CBP1 (second symbol), the transition state storage memory 41 uses the transition state storage memory 41 to update the transition state index of MVD1 (first symbol). The transition state index of the stored CBP1 (second symbol) is updated.
When the arithmetic decoding operation processing unit 44 arithmetically decodes the binarized data including CBP1 (second symbol), the inverse binarizing unit 46 inversely binarizes the binarized data and uses CBP as a decoding parameter. Output.

  As is apparent from the above, according to the fourth embodiment, the binary data of MVD1 (first symbol) is arithmetically decoded with reference to the occurrence probability of MVD1 (first symbol), and then Referring to the occurrence probability of CBP1 (second symbol), the binary data of CBP1 (second symbol) is arithmetically decoded and MVD1 (first symbol) stored in transition state storage memory 41 And CBP1 (second symbol) are updated by an arithmetic decoding operation processing unit 44, and the state reset determining unit 45 performs arithmetic decoding of the MVD1 (first symbol) 2 by the arithmetic decoding operation processing unit 44. It is determined whether or not the steady state of the digitized data is interrupted. If the steady state is interrupted, the binary data of CBP1 (second symbol) is obtained by the arithmetic decoding operation processing unit 44. Since the transition state index of CBP1 (second symbol) stored in the transition state storage memory 41 is initialized before arithmetic decoding is performed, the arithmetic coding apparatus can improve the coding efficiency. It is possible to correctly decode the received symbols.

Embodiment 5 FIG.
In the fourth embodiment, the state reset determination unit 45 determines whether or not the steady state of the binarized data of MVD1 (first symbol) arithmetically decoded by the arithmetic decoding arithmetic processing unit 44 is interrupted. If the state is interrupted, the CBP1 (second symbol) stored in the transition state storage memory 41 is obtained before the arithmetic decoding operation processing unit 44 performs arithmetic decoding of the binary data of CBP (second symbol). Although the symbol (transition state index) is initialized, the steady state of the binarized data of MVD1 (first symbol) is interrupted as in the video encoding apparatus of the second embodiment. When the meanings of MPS (dominant symbol) and LPS (inferior symbol) in the binary data of CBP1 (second symbol) are reversed, the transition state storage memory 4 Instead of initializing the transition state index stored CBP1 (second symbol) by, it operates to reverse the meaning of MPS and LPS in binary data CBP1 (second symbol).

Also, the transition state index of CBP1 (second symbol) operates to forcibly transition to a transition state index that transitions when one or more LPSs are received.
Also in these cases, as in the fourth embodiment, there is an effect that a symbol whose coding efficiency is improved by the arithmetic coding apparatus can be correctly decoded.

Embodiment 6 FIG.
FIG. 12 is a block diagram showing an entropy decoding unit 31 which is an arithmetic decoding apparatus according to Embodiment 6 of the present invention. In the figure, the same reference numerals as those in FIG.
The transition state storage memory 47 is a recording medium that stores the transition state index of each symbol to be decoded, similar to the transition state storage memory 41 of FIG. 9, but like the transition state storage memory 41 of FIG. The current transition state index of CBP1 (second symbol) is not initialized by the state reset determination unit 45, but, for example, from the intra prediction unit 2 or the motion compensation prediction unit 3 of the video encoding device, MVD1 ( When the transition state reset flag (state transition information) indicating that the steady state of the binarized data of the first symbol) is interrupted, the arithmetic decoding operation processing unit 44 causes the MVD1 (first symbol) and CBP1 ( The current transition of MVD1 (first symbol) and CBP1 (second symbol) before the arithmetic decoding of the binarized data of the second symbol) It is different in that to initialize the state index.
The transition state storage memory 47 constitutes an occurrence probability storage means and an occurrence probability initialization means.

Next, the operation will be described.
When the intra prediction unit 2 (or motion compensation prediction unit 3) of the moving image encoding device generates a predicted image in a block (referred to as an unpredictable block) having a property different from that of a previously decoded block, the unpredictable block Therefore, it is possible to determine whether or not the steady state of the binarized data of MVD1 (first symbol) in the unpredictable block is interrupted.
If the intra prediction unit 2 (or motion compensation prediction unit 3) determines that the steady state of the binarized data of the MVD1 (first symbol) in the unpredictable block is interrupted, it indicates that the steady state is interrupted. The transition state reset flag shown is output to the entropy encoding unit 11.
The entropy encoding unit 11 entropy encodes a plurality of parameters and entropy encodes the transition state reset flag.

When the transition state storage memory 47 of the entropy decoding unit 31 in the video decoding device receives the transition state reset flag from the video encoding device, the arithmetic decoding calculation processing unit 44 causes the MVD1 (first symbol) and the CBP1 (second symbol). The current transition state index of MVD1 (first symbol) and CBP1 (second symbol) is initialized before the arithmetic decoding of the binarized data of the first symbol) is performed.
In this case, before the arithmetic decoding operation processing unit 44 performs arithmetic decoding of the binary data of MVD1 (first symbol), the transition state storage memory 47 stores the binary data of MVD1 (first symbol). Since the steady state is interrupted, not only the transition state index of CBP1 (second symbol) but also the transition state index of MVD1 (first symbol) is initialized. .
Since other processing contents are the same as those of the fourth embodiment, description thereof is omitted.

  As is apparent from the above, according to the sixth embodiment, when the transition state reset flag indicating that the steady state of the binarized data of MVD1 (first symbol) is interrupted is received, the transition state storage memory 47, before arithmetic decoding of the binary data of MVD1 (first symbol) and CBP1 (second symbol) is performed by the arithmetic decoding arithmetic processing unit 44, MVD1 (first symbol) and CBP1 (second symbol) Since the transition state of (symbols) is initialized, it is possible to correctly decode symbols whose coding efficiency has been improved by the arithmetic coding apparatus.

  DESCRIPTION OF SYMBOLS 1 Image input part, 2 Intra prediction part, 3 Motion compensation prediction part, 4 Coding control part, 5 Selection switch, 6 Subtractor, 7 Quantization conversion part, 8 Inverse quantization conversion part, 9 Adder, 10 Frame memory , 11 Entropy encoding unit, 21, 27 Transition state storage memory, 22 Probability table memory, 23 Context generation unit, 24 Binarization unit, 25 Arithmetic encoding operation processing unit, 26 State reset determination unit.

Claims (4)

A binarizing unit that binarizes a parameter to be encoded and outputs binarized data, stores an occurrence probability of a first symbol that is a symbol included in the binarized data, and stores the first With reference to the occurrence probability storage means for storing the occurrence probability of the second symbol included in the binarized data correlated with the symbol, and the occurrence probability of the first symbol stored in the occurrence probability storage means Then, after arithmetically encoding the binarized data of the first symbol output from the binarization means, the occurrence probability of the second symbol stored in the occurrence probability storage means is referred to, and Arithmetic codes for arithmetically encoding the binarized data of the second symbol output from the binarizing means and updating the occurrence probabilities of the first and second symbols stored in the occurrence probability storage means It is determined whether the steady state of the binarized data of the first symbol output from the binarizing means and the binarizing means is interrupted. If the steady state is interrupted, the arithmetic coding means before arithmetic coding of the binary data of 2 symbols is performed, a probability initializing means for initializing the occurrence probability of the second symbol stored by the probability storage means, the occurrence The probability initializing means is such that the binarized data of the first symbol output from the binarizing means is an inferior symbol, and the occurrence probability of the first symbol stored in the occurrence probability storage means is a predetermined value. An arithmetic coding apparatus characterized by determining that the steady state of the binarized data of the first symbol is interrupted when it is equal to or greater than a threshold value . A binarizing unit that binarizes a parameter to be encoded and outputs binarized data, stores an occurrence probability of a first symbol that is a symbol included in the binarized data, and stores the first With reference to the occurrence probability storage means for storing the occurrence probability of the second symbol included in the binarized data correlated with the symbol, and the occurrence probability of the first symbol stored in the occurrence probability storage means Then, after arithmetically encoding the binarized data of the first symbol output from the binarization means, the occurrence probability of the second symbol stored in the occurrence probability storage means is referred to, and Arithmetic codes for arithmetically encoding the binarized data of the second symbol output from the binarizing means and updating the occurrence probabilities of the first and second symbols stored in the occurrence probability storage means It is determined whether the steady state of the binarized data of the first symbol output from the binarizing means and the binarizing means is interrupted. If the steady state is interrupted, the arithmetic coding means An occurrence probability initialization means for initializing the occurrence probability of the second symbol stored in the occurrence probability storage means before performing the arithmetic coding of the binary data of the two symbols. The probability initialization means is such that the binarized data of the first symbol output from the binarization means is an inferior symbol, and the occurrence probability of the first symbol stored in the occurrence probability storage means is the first. If the occurrence probability of the second symbol stored in the occurrence probability storage means is greater than or equal to the second threshold, the steady state of the binarized data of the first symbol is interrupted. Determined Arithmetic coding apparatus according to claim 1, wherein Rukoto. An occurrence probability storage means for storing an occurrence probability of a first symbol which is a symbol to be decoded, and storing an occurrence probability of a second symbol correlated with the first symbol; and the first and second Input the encoded data which is the result of arithmetic encoding of the binarized data of the symbol, and refer to the occurrence probability of the first symbol stored in the occurrence probability storage means, and the binary of the first symbol The arithmetic decoding of the binarized data, the arithmetic decoding of the binarized data of the second symbol with reference to the occurrence probability of the second symbol stored in the occurrence probability storage means, and the occurrence probability Arithmetic decoding means for updating the occurrence probabilities of the first and second symbols stored in the storage means, and the steady state of the binarized data of the first symbol arithmetically decoded by the arithmetic decoding means If the steady state is interrupted, it is stored in the occurrence probability storage means before the arithmetic decoding of the binary data of the second symbol by the arithmetic decoding means. An occurrence probability initializing means for initializing the occurrence probability of the second symbol, and the binarized data including the first and second symbols arithmetically decoded by the arithmetic decoding means by inverse binarization e Bei an inverse binarization means for outputting, the occurrence probabilities initializing means is a binary data inferior symbol of the first symbol which is arithmetically decoded by the arithmetic decoding means, and by the occurrence probability storage means An arithmetic decoding apparatus characterized by determining that the steady state of the binarized data of the first symbol is interrupted when the occurrence probability of the stored first symbol is equal to or greater than a predetermined threshold . An occurrence probability storage means for storing an occurrence probability of a first symbol which is a symbol to be decoded, and storing an occurrence probability of a second symbol correlated with the first symbol; and the first and second Input the encoded data which is the result of arithmetic encoding of the binarized data of the symbol, and refer to the occurrence probability of the first symbol stored in the occurrence probability storage means, and the binary of the first symbol The arithmetic decoding of the binarized data, the arithmetic decoding of the binarized data of the second symbol with reference to the occurrence probability of the second symbol stored in the occurrence probability storage means, and the occurrence probability Arithmetic decoding means for updating the occurrence probabilities of the first and second symbols stored in the storage means, and the steady state of the binarized data of the first symbol arithmetically decoded by the arithmetic decoding means If the steady state is interrupted, it is stored in the occurrence probability storage means before the arithmetic decoding of the binary data of the second symbol by the arithmetic decoding means. An occurrence probability initializing means for initializing the occurrence probability of the second symbol, and the binarized data including the first and second symbols arithmetically decoded by the arithmetic decoding means by inverse binarization Output binarization means for outputting, wherein the occurrence probability initialization means is binarized data of the first symbol arithmetically decoded by the arithmetic decoding means is an inferior symbol, and is stored by the occurrence probability storage means. The occurrence probability of the first symbol being equal to or higher than the first threshold and the occurrence probability of the second symbol stored in the occurrence probability storage means is equal to or higher than the second threshold. Arithmetic decoding apparatus shall be the determining means determines that the steady state of the binary data of one symbol is broken.

Images