JP3293382B2 - Data compression device and data decompression device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression apparatus for compressing data and a data expansion apparatus for expanding compressed data.

[0002]

2. Description of the Related Art Generally, when data is stored in a storage device, a method of compressing and recording data to be written is used in order to increase the amount of data to be stored. As one of such data compression methods, a run-length compression method for converting data into information of a data value and a continuous length is known. This compression method has the advantage that the circuit configuration can be realized relatively easily, but on the other hand, in the case of a discontinuous data string, the data amount after compression becomes larger than the original data amount. is there.

For example, as shown in FIG. 8, when a data is divided into a data frame and a length frame and a run-length compression format is used, the worst case, ie, a discontinuity in which the data value changes every pixel, is used. In the case of a simple data string, the data amount increases twice as much as the original data.

Conventionally, various measures have been taken to solve such inconveniences. As an example, Japanese Patent Application Laid-Open No. 58-163
No. 44 proposes a data compression storage device using a run-length compression format as shown in FIG. In the run-length compression format, a marker bit for identifying each frame is added to each of a data frame and a length frame. For example, when the data width is set to 8 bits, a discontinuous data string is used. However, the data amount after compression increases only to 9/8 times the original data amount.

In Japanese Patent Application Laid-Open No. 58-75244,
A data compression storage device has been proposed in which a marker bit is added to each of a data frame and a length frame in the same manner as described in the above publication, but the order of the data frame and the length frame is different. Also in this conventional apparatus, when the data width is set to 8 bits, when compressing a discontinuous data string, the data amount after compression is reduced to 9 times the original data amount.
It can be stopped by / 8 times.

As described above, as a conventional compression method for minimizing the worst case compressed data amount, a method of adding a 1-bit marker bit has been known. A conventional data compression circuit for obtaining such compressed data includes, for example, a latch circuit 51, a comparison circuit 52, a controller circuit 53, a counter circuit 54, and a selector 55 as shown in FIG.
Has been realized.

On the other hand, the above-described restoration processing of run-length compressed data to which a 1-bit marker bit has been added has been performed as follows. FIG. 11 shows an example of a circuit for decompressing the run-length compressed data, which comprises a latch circuit 61, a counter circuit 62, and a controller circuit 63. FIG. 15 shows a timing chart of each signal relating to the expansion processing of the data expansion circuit 60.

In FIG. 11, a data decompression circuit 60
When expanding the input data, it is necessary to determine whether the input data is to be latched in the latch circuit 61 or loaded into the counter circuit 62 as a count value, based on a marker bit (see FIG. 9) added to the input data.

A selection circuit for selecting the data latch / counter load is provided in the controller circuit 63. For example, as shown in FIG. 12, an inverter 631 and an AND circuit 632, 633 are arranged.

Here, flip-flops 634, 635
Since the circuit section at the preceding stage acts as a delay element in the selection processing time, a marker bit of input data is selected by this selection circuit in order to select data latch or counter load as soon as possible. Before the rising edge of the clock, a sufficient setup time for compensating the delay time must be satisfied. If a sufficient setup time is not satisfied, the selection timing at the next rising edge of the clock is shifted, and one wait is left.

FIG. 13 shows how the conventional data decompression circuit 60 captures the setup time. Here, when the basic clock is slow, the setup time can be easily satisfied. However, in order to be able to cope with the recent high clock speed, further measures are required.

For example, FIG. 14 shows a configuration of a conventional data decompression circuit compatible with a high-speed clock. In this data decompression circuit 60A, a latch circuit 65 temporarily latches input data to thereby provide a high-speed clock. It is possible to correspond to. FIG. 16 shows a timing chart of each signal of the data decompression circuit 60A. As can be seen from FIG. 11H, even if the configuration in which the latch circuit 65 is added, when the data length is 2, the signal for reading the next input data is delayed by one clock, and the output data is delayed. May be discontinuous. Therefore, when applied to a system requiring continuous data such as a printer system, the FIFO 66
Buffer had to be provided.

[0013]

As described above, in the above-described conventional apparatus, the marker bits in the run-length compressed data are simply used as information for identifying a data frame or a length frame. Therefore, a selection circuit for latching the input data or loading the data into the counter is required on the basis of, for example, a circuit configuration in which a predetermined logic circuit is arranged in the preceding stage of the flip-flop has been inevitable. According to this configuration, since the preceding circuit acts as a delay element, it is necessary to secure a sufficient set-up time to perform an accurate restoration operation. However, there is a problem that a high-speed restoration process cannot be practically supported in terms of a complicated circuit configuration.

An object of the present invention is to provide a data compression apparatus capable of generating compressed data useful for high-speed restoration processing and a data expansion apparatus capable of performing high-speed expansion processing of compressed data by the data compression apparatus. Aim.

[0015]

SUMMARY OF THE INVENTION A data compression apparatus according to the present invention compares a latch circuit for temporarily holding input data with whether the latch data held in the latch circuit matches new input data. A comparison circuit, and a result of the comparison;
A counter circuit that counts up when the latch data matches the new input data; and a counter circuit that counts up when the latch data and the new input data do not match when the count value of the counter circuit is 1. , A marker bit indicating that the length frame does not continue is added to the latch data, and is output. When the count value of the counter circuit is greater than 1, a marker indicating that the length frame continues in the latch data is output. And a switching circuit for outputting a bit after adding the bit, and subsequently outputting the count value of the counter circuit as the length data of the continuous length frame.

Further, the data decompression device of the present invention includes a latch circuit for temporarily holding input data, a counter circuit for loading the input data as an initial count value, and sequentially counting down until the count value becomes zero, and the latch circuit. It is determined whether the marker bit added to the first input data held in is a bit value indicating the continuation of the length frame or a bit value not indicating the continuation, and the bit indicating the continuation of the length frame is determined. When the value is a value, the second input data following the first input data is loaded into the counter circuit, and the countdown is repeated to repeatedly output the first input data as output data. When there is no bit value, the first input data is output as output data, and new second input data is output as the latch time. Constructed and a control circuit for performing control to latch the.

[0017]

According to the present invention, in data compression, when the length of continuous data is 1 (when the same data is not continuous),
A marker bit 0 indicating that the length frame does not continue is added to the n bits of the data value, and when the length of the continuous data is 2 or more (when the same data continues), the n bits of the data value are added. After adding a marker bit 1 indicating that there is a length frame, by further adding a (n + 1) -bit length frame, it is possible to determine whether the frame following the data is a data frame or a length frame. This is to generate run-length compressed data having a format to which the indicated marker bits are added.

According to the present invention, when restoring the data, the input data is temporarily latched, and whether the marker bit added to the latched first input data is a bit value indicating the continuation of the length frame is determined. It is determined whether the bit value is a bit value not to be represented, and when the bit value is a bit value indicating the continuation of the length frame, the second input data following the first input data is loaded into the counter circuit. Input data is repeatedly output as output data, and when the bit value does not indicate the continuation of the length frame, the first input data is output as output data and new second input data is latched. It was done.

As described above, in the present invention, the marker bit of the input data is a run-length compression format that is used as a bit for determining whether the frame following the input data is a data frame or a length frame. When restoring data, it is possible to directly recognize whether the subsequent input data is a data frame or a length frame based on the marker bits. Therefore, the selection circuit for determining whether to load the data latch or the counter load can be realized only by, for example, a flip-flop for inputting the marker bit, eliminating the necessity of a preceding circuit of the flip-flop which is indispensable for the conventional selection circuit of this type. This eliminates the need for a setup time for compensating for the delay of the preceding circuit, thereby realizing high-speed expansion of compressed data.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a data compression circuit according to one embodiment of the present invention, which comprises a latch circuit 1, a comparison circuit (compare circuit) 2, a controller circuit 3, a counter circuit 4, and a selector 5. Be composed.

In this data compression circuit 10, n is 8
The data compression processing operation will be described taking the case of bits as an example. The 8-bit input data is supplied to the latch circuit 1
Is latched once. The latch timing is generated by the controller circuit 3. When latching the first data, the count value of the counter circuit 4 needs to be cleared to 1. A counter reset signal for clearing the counter circuit 4 is also generated by the controller circuit 3.

The data latched by the latch circuit 1 is compared with the next input data by the comparison circuit 2, and the result of the comparison as to whether the data matches or not is transmitted to the controller circuit 3. The controller circuit 3 outputs a count-up signal to the counter circuit 4 if the comparison result indicates "match", and increments the count value by one.

On the other hand, if the result of the comparison indicates that they do not match, the following processing operation according to the count value of the counter circuit 4 is performed. That is, the controller circuit 3 receives the comparison result of “not coincident” from the comparison circuit 2 and then, when the count value of the counter circuit 4 is 1 (when it does not indicate that the same data continues). In order to transfer the latch data of the latch circuit 1 at this time to the storage device 6, the selector 5
In response to this, a select signal for selecting the latch data and data of "0" as a marker bit indicating that the data is not continuous (that is, there is no length frame continuing to the data) are transmitted.

On the other hand, when the count value of the counter circuit 4 is larger than 1 (indicating that the same data is continuous), first, the selector 5 is operated to transfer the latch data of the latch circuit 1 to the storage device 6. In response to this, a select signal for selecting the latch data and data of "1" as a marker bit indicating that the data is continuous (that is, the data has a continuous length frame) are transmitted. Further, following the latch data, a select signal for selecting the count value is transmitted to the selector 5 in order to transfer the count value of the counter circuit 4 to the storage device 6.

Thereafter, the same processing is repeated until the end of the input data. Thereby, the data compression circuit 10
, Run-length compressed data having a format structure as shown in FIG. 2 is obtained from the selector 5 and stored in, for example, the storage device 6.

FIG. 6 is a timing chart of each signal during data compression processing in the data compression circuit 10 of the present invention. In this embodiment, the basic clock (FIG. 2A) is a clock for the system,
A frequency of about 20 [MHz] is assumed. It is assumed that the input data [(c) in the figure] is "AABCCC @".

In synchronization with the rise of the basic clock, the controller circuit 3 generates an input data read signal [FIG. When the input data read signal becomes "Low", the input data is read from the host (not shown), and "A" as the first data is input. When the input data from the host side is stabilized, a latch signal [FIG. 2 (d)] for latching the data becomes active in the latch circuit 1, and "A" is latched as the latch data [FIG. 2 (e)]. Is done. Then, in order to read the second input data subsequent to the “A”, the controller circuit 3 activates the input data read signal and reads the second data “A” from the host.

The second data "A" input from the input signal line is compared in the comparison circuit 2 with the data already latched. In this example, since the latched data already latched is "A", the comparison result signal output from the comparison circuit at this time becomes "High" indicating "match", and this comparison result The signal [(f) in the figure] is transmitted to the controller circuit 3.

The controller circuit 3 recognizes from the comparison result signal that the values match, and activates a count-up signal ((g) in the figure) at the rising timing of the basic clock, thereby causing the counter circuit 4 to operate. Tell The counter circuit 4 counts up the count value [(h) in the figure] from “1” to “2” by the count-up signal.

At the same time as this timing, the output clock to the storage device 6 ((1) in the figure) becomes active,
The marker signal "1" (FIG. 7 (j)) and the latch data "A" of the latch circuit 1 are output and stored in the storage device 6 as output data [FIG.

Subsequently, "B" is read as the third data. The third data "B" is compared with the previous latch data "A". In this case, since the two do not match, the comparison result signal indicates "not matching". “Low” is output.

This comparison result signal is transmitted to the controller circuit 3. Here, the controller circuit 3 activates a latch signal for latching the third data at the rising timing of the basic clock, and latches the third data “B”. At the same time as this timing
The count value “2” of the counter circuit 4 is selected as output data by a select signal [(k) in the figure] and stored in the storage device 6.

Simultaneously with this timing, a counter reset signal [(i)] for resetting the counter circuit 4 becomes active, and the count value of the counter circuit 4 is reset to "1". Then, in order to read the fourth input data from the host, the input data read signal is activated and “C” is read as the fourth input data. The fourth input data “C” is compared with the previous latch data “B” by the comparison circuit 2, but here again, since they do not match, the comparison result signal is “not matching”. "Lo
w "is output.

This comparison result signal is transmitted to the controller circuit 3. Here, the controller circuit 3 activates a latch signal for latching the fourth data at the rising timing of the basic clock, and latches the fourth data “C”. At the same time as this timing, the latch data “B” is stored in the storage device 6 together with the marker signal “0” at the timing of the rising edge of the output clock.

Hereinafter, by repeating the same processing,
The fifth input data “C”, the sixth input data “C”, and the subsequent input data are processed.

Next, the process of decompressing the compressed data generated by the data compression circuit 10 will be described. FIG. 3 is a block diagram showing an embodiment of a data decompression circuit for decompressing the run-length compressed data generated by the data compression circuit 10. This data decompression circuit 20 is different from the conventional circuit in the configuration of the controller circuit 13 and how the marker bits are transmitted to the controller circuit 13.

As for the configuration of the controller circuit 13, particularly, regarding the portion for generating the data latch signal and the counter load signal, in the conventional circuit, an inverter 631 and an AND circuit are provided in front of the flip-flops 634 and 635 as shown in FIG. In contrast to the configuration in which 632 and 633 are arranged, in the present invention, as shown in FIG.
33 are arranged.

According to the configuration of the data latch / counter load selection circuit, the set-up time for compensating the restoration of the input data without interruption is as shown in the timing chart of FIG.

In the data decompression circuit 20 having the above configuration, the decompression process is performed by using the compressed data generated by the data compression circuit 10 and having the format as shown in FIG. 2 as input data. First, in the data expansion circuit 20, first input data is latched by the latch circuit 11. Next, the controller circuit 13 extracts a marker bit in the data latched by the data latch circuit 11, and determines whether or not the marker bit indicates the continuation of the length frame. Here, if the marker bit indicates the continuation of the length frame, a counter load signal is sent to the counter circuit 12 so that the second input data following the latch data is sent to the counter circuit 12 as the initial count value. Load as

On the other hand, if the marker bit does not indicate the continuation of the length frame, the data latch circuit 11 sends out a data latch signal to hold the second input data in the data latch circuit 11. In this case, needless to say, the second input data is not a length frame but a data frame next to the previously input data frame. Thereafter, similarly, the third and subsequent data are processed. In the process, when the count value is loaded into the counter circuit 12, the count value is initialized and the count data is sequentially counted down, and the latch data of the data latch circuit 11 is stored in the printer device or the storage device by the number of count values. The data is transferred as output data to an external device 14 such as a device. When the count value becomes "0", the same operation as described above is repeatedly performed.

FIG. 7 shows a timing chart of each signal relating to the data expansion processing in the data expansion circuit 20. Hereinafter, the data decompression process will be described in more detail with reference to this timing chart.

Also in this example, the basic clock (FIG. 10A) is a clock for the system.
[MHz] is assumed. Note that the input data to be restored in this example [(c) in FIG.
1 + B, 3, 0 + C, ‥‥‥‥ ”.

In synchronization with the rise of the basic clock, the controller circuit 13 generates an input data read signal [FIG. When the input data read signal becomes “Low”, the input data is read from the host, and “1 + A”, which is the first data, is input. When the input data from the host is stabilized, the data latch signal [(d) in the figure] applied to the latch circuit 11 becomes active, and "1 + A" is latched as the latch data [(e) in the figure].

The MSB (most significant bit) of the latch data is transmitted to the controller circuit 13 as a marker signal [(f) in FIG. In the case of this example, the MSB is the data of “1” in the input “1 + A” and has a content indicating the continuation of the length frame. In this case, in order to read the length frame following the input data from the host, the controller circuit 13 activates the input data read signal and sets “2” as the second data (length frame) from the host. Lead.

The second data "2" input from the input signal line is loaded into the counter circuit 12 by a counter load signal [FIG. 9 (g)], and the loaded count value [FIG. 9 (h)]. Is transmitted to the controller circuit 13. A counter load signal for loading the counter circuit 12 with the count value is transmitted from the controller circuit 13 to the counter circuit 12 at the rising timing of the basic clock.

Also, one clock before this timing, the output data latch signal [(j)] for writing the latch data to the external device 14 is activated, and the latch data is externally transmitted twice. Output to the device 14. Then, the controller circuit 13 includes the counter circuit 1
When it is determined that the count value transmitted from 2 is “2”, the input data read signal is activated in synchronization with the rise of the basic clock to read the third input data, and the third input data is read from the host. Input data "1
When the input data from the host side is stabilized, the latch circuit 1
The latch signal for latching the data at 1 becomes active, and "1 + B" is latched as the latch data. The MSB of the latch data is transmitted to the controller circuit 13 as a marker signal. In this case, a bit “1” indicating the continuation of the length frame is transmitted to the controller circuit 13. Then, in order to read the length frame from the host side, the controller circuit 1
No. 3 activates the input data read signal and reads “3” as fourth data (length frame) from the host side. Hereinafter, similarly, the above processing is repeatedly performed until the end of the data to obtain restored data.

In the above embodiment, an example has been described in which the marker bit is added as the MSB (most significant bit) of the data frame.
Needless to say, it can be added to (the least significant bit) or other bits.

[0048]

As described above, according to the present invention,
In the run-length compressed data to which the marker bit is added, the marker bit is used as information indicating whether a frame following the data frame to which the marker bit is added is a data frame or a length frame.
The marker bit contained in the data frame can be directly input to the flip-flop to determine whether to load the data latch or the counter, eliminating the need for the setup time for selecting the data latch / counter load, and expanding the compressed data at high speed. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a data compression circuit according to one embodiment of the present invention.

FIG. 2 is a schematic diagram showing a format of run-length compressed data generated by a data compression circuit of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a data decompression circuit according to one embodiment of the present invention.

FIG. 4 is a block diagram showing a main configuration inside a controller circuit in the data decompression circuit of the present invention.

FIG. 5 is a timing chart for explaining a setup time in the data decompression circuit of the present invention.

FIG. 6 is a timing chart of each signal in the data compression circuit according to the present invention.

FIG. 7 is a timing chart of each signal in the data decompression circuit according to the present invention.

FIG. 8 is a diagram showing an example of a format of a conventional run-length compressed data.

FIG. 9 is a diagram showing another example of the format of conventional run-length compressed data.

FIG. 10 is a block diagram showing a schematic configuration of a conventional data compression circuit.

FIG. 11 is a block diagram showing a schematic configuration of a conventional data decompression circuit.

FIG. 12 is a block diagram showing a main configuration inside a controller circuit in a conventional data decompression circuit.

FIG. 13 is a timing chart for explaining a setup time in a conventional data decompression circuit.

FIG. 14 is a block diagram showing a schematic configuration of a conventional data decompression circuit compatible with a high-speed clock.

FIG. 15 is a timing chart of each signal in a conventional data decompression circuit.

FIG. 16 is a timing chart of each signal in a conventional data decompression circuit compatible with a high-speed clock.

[Explanation of symbols]

Reference Signs List 10 data compression circuit, 1 latch circuit, 2 comparison circuit (compare circuit), 3 controller circuit, 4 counter circuit, 5 selector, 6 storage device, 20 data decompression circuit, 11 data latch circuit, 12 counter circuit, 1
3 controller circuit, 131 flip-flops, 1
32,133 AND circuit, 14 external devices

Continuation of the front page (72) Inventor Naoyuki Iwabuchi 3-7-1, Fuuchi, Iwatsuki-shi, Saitama Fuji Xerox Co., Ltd. Iwatsuki Office (56) References JP-A-58-102314 (JP, A) JP-A-5-102 268485 (JP, A) JP-A-58-16344 (JP, A) JP-A-58-75244 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/46 G06F 5 / 00

Claims (3)

(57) [Claims] A latch circuit for temporarily holding input data; a comparison circuit for comparing whether the latch data held in the latch circuit matches new input data; and a result of the comparison, the latch data A counter circuit that counts up when the input data and new input data match; and, as a result of the comparison, when the latch data does not match the new input data, the count value of the counter circuit is 1
In the case of the above, a marker bit indicating that the length frame does not continue is added to the latch data and output. When the count value of the counter circuit is larger than 1, the length frame continues to the latch data. And a switching circuit for outputting the added marker bit and continuously outputting the count value of the counter circuit as the length data of the continuous length frame. 2. A latch circuit for temporarily holding input data, a counter circuit for loading the input data as an initial count value, and sequentially counting down until the count value becomes zero, and a first input held in the latch circuit. It is determined whether the marker bit added to the data is a bit value indicating the continuation of the length frame or a bit value not indicating the continuation. When the marker bit is a bit value indicating the continuation of the length frame, the first input is performed. Loading second input data following the data into the counter circuit, and repeatedly outputting the first input data as output data together with the countdown;
A control circuit that outputs the first input data as output data when the bit value does not indicate the continuation of the length frame, and controls the latch circuit to latch new second input data. A data decompression device characterized by the above-mentioned. 3. The data decompression device according to claim 2, wherein the marker bit is added as the most significant or least significant bit of the input data.