JPS63159934A - Microcode generating circuit - Google Patents

Abstract

PURPOSE:To realize the bidirectional transfer of data just with a single external interruption by providing plural microcode memories to a memory and using a means to give the external control to the data output gates of those microcode memories. CONSTITUTION:The chip selection signal of an optional microcode memory 3 is set in an enable state for selection by an external selection signal generating circuit 6 before an external interruption is applied to a program sequencer 1. Thus the instructions and the address data are outputted to the sequencer 1 and an address generator 2 from the memory 3 after the reception of the external interruption. At the same time, a memory control signal is outputted to a RAM 4. The memory 3 contains the microcodes of read and write accesses prepared for the RAM 4, therefore a read or write access is possible to the RAM 4 against a single external interruption. In such a way, the bidirectional transfer of data is carried out between RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcode generation circuit for generating addresses (memory addresses) used to control a memory and memory control signals.

[Prior Art] Fig. 2 is an electrical circuit diagram showing a conventional microcode generation circuit. In Fig. 2, 1 is a program sequencer, 2 is an address generator, 3 is a microcode memory, 4 is a RAM, 5 is an external interrupt multiplexer.

Next, the operation will be explained. First, by an interrupt output from the external interrupt multiplexer 5.

The program sequencer 1 outputs an address to the microcode memory 3 in response to interrupt processing. The microcode memory 3, which has received the addresses in this manner, outputs instructions to the program sequencer 1 and outputs instructions and address data to the address generator 2.

Further, a memory write signal or a memory read signal as a memory control signal and a memory chip select signal are output to the RAM 4. The address generator 2 then outputs an address (memory address) to the RAM 4 according to the instruction and address data.

[Problems to be Solved by the Invention] Since the conventional microcode generation circuit is configured as described above, access to RAM 4 is limited to either read mode or write mode for one interrupt. Therefore, there were problems such as two external interrupts being required to read/write the RAM 4.

This invention was made to solve the above-mentioned problems, and it is possible to select whether the memory is in read mode or write mode with a single external interrupt, and it is also possible to mutually transfer data between memories. The purpose of the present invention is to obtain a microcode generation circuit that enables the following.

[Means for Solving the Problems] The microcode generation circuit according to the present invention includes a plurality of microcode memories for each memory, and
This device is provided with means for controlling the data output gate of the microcode memory from the outside.

[Work] In the microcode generation circuit in this invention.

By controlling multiple microcode memories by external control means, it is possible to select whether the memory is in read mode or write mode with a single external interrupt, and it is also possible to transfer data between memories. It becomes possible.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, 1 is a program sequencer, 2 is an address generator, 3 is a microcode memory, and 4 is an RA.
M, 5 is an external interrupt multiplexer, and a plurality of microcode memories 3 are provided for one RAM 4. Reference numeral 6 designates an external selection signal generation circuit as a means for controlling the data output gate of each microcode memory 3 from the outside.

Next, the operation will be explained. When the external interrupt multiplexer 5 outputs an interrupt in response to an external interrupt, the program sequencer 1 outputs an address (address information) to the microcode memory 3 in response to the interrupt processing.

By the way, the microcode memory 3 is selected by enabling the chip select signal of any microcode memory 3 by the external selection signal generation circuit 6 before inputting an external interrupt to the program sequencer 1. Microcode memory 3 to program sequencer 1. Address generator 2 outputs instructions and address data, and also outputs memory control signals (memory read signal, memory write signal) to RAM 4.

These multiple microcode memories 3 each have microcodes for read access and write access to the RAM 4, so either read access or write access to the RAM 4 can be performed in response to one external interrupt. This enables bidirectional data transfer between the RAMs 4, ie mutual transfer of data.

[Effects of the Invention] As described above, according to the present invention, a plurality of microcode memories are provided for each memory, and the access method to the memory can be selected from read mode or write mode by selection from an external control means. Memory data transfer can be performed bidirectionally with one external interrupt, and this has the effect of providing a highly versatile microcode generation circuit.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram showing a microcode generating circuit according to an embodiment of the present invention, and FIG. 2 is an electrical circuit diagram showing a conventional microcode generating circuit. In the figure, 1-program sequencer, 2-address generator, 3-microcode memory, 4-RA
M (memory), 5--external interrupt multiplexer, 6
-・External selection signal generation circuit as external control means. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a microcode generation circuit that controls memory by generating memory addresses and memory control signals, there is a program sequencer that receives interrupt signals from the outside and outputs address information, and a program sequencer that receives the above address information from the program sequencer and generates addresses. The microcode memory includes a microcode memory that outputs a signal for generating the address and the memory control signal, and an address generator that outputs the memory address in response to a signal for generating the address from the microcode memory. A microcode generation circuit, characterized in that a plurality of memories are provided for the above-mentioned memories, and means for externally controlling a data output gate of each of the above-mentioned microcode memories is provided.