JP2000259812A - High-speed image processing method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed image processor capable of high-speed access of image data by a processor parallelly to the fetching operation of the image data from an image pickup device. SOLUTION: The AD conversion output of image signals from ITV cameras 1a-1d is written to line memories 3a-3d and data for one line each in an order for the line memories 3a-3d, for the total of four lines, are read within one line period at a high speed and written to a field buffer storage device 6. The write is performed in the form of writing the data of the 1st pixel-8th pixel of the line 1 of the line memory 3a to FIFO memories #1-#8 and 9th-16th pixels to the FIFO memories #1-#8 and the data of the other line memories are written in the same form as well. The processor 8 accesses the memories #1-#8 altogether at a high speed by a 64-bit bus, reads the data for the continuous eight pixels and executes a high-speed image processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a high-speed image processing method and apparatus capable of processing image data generated from an image pickup signal output from an image pickup apparatus such as an ITV camera at a high speed.

[0002]

2. Description of the Related Art FIG. 5 shows an example of an image processing apparatus for processing image data generated from an image pickup output of a conventional ITV camera (industrial TV camera).

In FIG. 1, reference numeral 20 denotes an ITV camera, and 25-1, 25-2, 25-3,..., 25-n denote image memory units including bidirectional three-state buffers 26, 27 and an image memory 28. Yes, bidirectional 3-state buffer 2
6, 27 and the image memory 28 are connected by a data bus 36 having a bus width of 8 bits. The synchronization signal 30 generated from the synchronization signal generation / address counter circuit 22 is
The image is supplied to the TV camera 20, and the timing of image capture is controlled.

At the time of image capture, an image signal 29 from the ITV camera 20 is converted into a digital signal by the A / D converter 21 and then written into the image memory 28 via the data bus 34 and the bidirectional three-state buffer 26. Is performed. The bus width of the branch portion of the data bus 34 to each image memory unit is 8 bits. At this time, the image memory address 33 of the image memory 28 is
3, an address counter output 31 which is an output of the synchronization signal generation / address counter circuit 22 is connected and selected.

On the other hand, at the time of image processing, an address corresponding to a pixel to be processed is generated in a processor 24, and this address is placed on an address bus 32 to place an address switch 23
To the image memory address 33 via The output from the image memory 28 is read from the data bus 35 to the processor 24 via the bidirectional three-state buffer 27. The bus width of the data bus 35 on the processor 24 side is 8 ×
n (n: number of image memory units). here,
In order to increase the speed of accessing image data from the processor 24, a method of increasing the clock frequency of the entire system or extending the data bus width as disclosed in Japanese Patent Application Laid-Open No. 3-75881 can be considered.

However, even if the clock frequency is increased, there is a certain limit due to problems in the access time of the image memory and the mounting technology. Further, even in a system in which the data bus width is expanded and several pixels are accessed at one time, the data is continuously transferred in pixel units in the image capturing means, which is different from the known example. As a measure to solve this, a plurality of processing units and a plurality of FIFO (First In First Out) memories for buffering the processing speed between the processing units are provided as disclosed in JP-A-61-125275. One.

When this is incorporated into the present configuration, a plurality of image units 25 are prepared, and the data bus 35 is expanded according to the bus width of the processor 24 so that the number of pixels for the plurality of image units 25 is reduced by one. A method of shortening the image processing time by reading in multiple times is conceivable, but the disadvantage is that the number of component parts increases and the image processing device itself becomes very expensive when trying to support multiple ITV cameras. is there.

[0008]

As described above, according to the structure of the conventional apparatus, if it is intended to realize high-speed access to image data from the processor 24, the number of components increases, which makes it expensive and difficult to reduce the size. Had a face.

The present invention is intended to eliminate the disadvantages of the prior art, and can simultaneously or individually acquire image data from one or more imaging devices. High-speed image processing that can be executed in parallel with the operation of capturing image data from the imaging device, while minimizing the increase in the number of component parts to reduce costs and achieve high-speed and flexible processing operations It is an object to provide a method and an apparatus.

[0010] Other objects and novel features of the present invention will be clarified in embodiments described later.

[0011]

According to a first aspect of the present invention, there is provided a high-speed image processing method using an image pickup apparatus, storage means connected to the image pickup apparatus via an interface, and a processor. Means for accessing the means and collectively taking in the read data with the number of output bits corresponding to the bus width of the processor, wherein the storage means performs a collective access operation of the storage means by the processor when the image data is taken in from the imaging device. Is characterized in that a plurality of pixel data obtained by one access is set to be constituted only by pixel data from only one imaging device.

According to a second aspect of the present invention, there is provided a high-speed image processing apparatus which captures and stores image data from an image pickup device via an interface connecting the processor and the image pickup device, and outputs the number of output bits corresponding to a bus width of the processor. And a storage means capable of outputting read data in parallel, wherein the processor accesses the storage means and fetches the read data collectively with the number of output bits corresponding to the bus width of the processor.

According to a third aspect of the present invention, there is provided a high-speed image processing apparatus provided with a processor, an interface for connecting a plurality of imaging devices, and an individual imaging device connected to the interface. A plurality of pre-stage storage means for fetching and temporarily storing image data, and provided at a subsequent stage of the plurality of pre-stage storage means,
Post-storage means capable of outputting read data in parallel with the number of output bits corresponding to the bus width of the processor, wherein the image data stored in the plurality of pre-storage means is stored in a predetermined data The data is sequentially read out at a higher speed than at the time of accumulation, transferred to the latter-stage storage means, and written.The processor accesses the latter-stage storage means and collectively reads out read data with the number of output bits corresponding to the bus width of the processor. It is characterized by taking in.

According to a fourth aspect of the present invention, in the high-speed image processing apparatus according to the third aspect, each of the plurality of pre-stage storage units is constituted by an asynchronous FIFO memory.

According to a fifth aspect of the present invention, in the high-speed image processing apparatus according to the third or fourth aspect, the post-stage storage means comprises a plurality of asynchronous FIFO memories, and the sum of the number of output bits of each FIFO memory is determined by the processor. The configuration corresponds to the bus width.

According to a sixth aspect of the present invention, in the high-speed image processing apparatus according to the fifth aspect, each FIFO provided in the subsequent storage means is provided.
The write data to the memory is stored in each FI by the processor.
In the batch access operation of the FO memory, a plurality of pixel data obtained by one access is set so as to be composed of only pixel data from only one imaging device.

According to a seventh aspect of the present invention, there is provided the high-speed image processing apparatus according to the first to sixth aspects, wherein only the image data from a desired one of the plurality of imaging devices connected to the interface is selected and captured. Selection means for enabling the following.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a method for temporarily storing image data in storage means capable of outputting read data in parallel with the number of output bits corresponding to the expanded bus width of a processor, and then storing the captured data. The processor can be accessed in units of a plurality of continuous pixels by the processor in parallel with the capture operation. Hereinafter, embodiments of the high-speed image processing method and apparatus according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a high-speed image processing apparatus according to the present invention. The present embodiment will be described with reference to time charts of FIGS. 2 and 3 showing the operation of this embodiment. The form will be described.

This embodiment uses an NTSC as an imaging device.
The system uses four ITV cameras 1a to 1d, and the image signals 9a to 9d input from these ITV cameras 1a to 1d are respectively A / D converters 2a to 2d which constitute an interface for connecting an imaging device. Is converted into digital image data at a sampling frequency of 10 MHz and a quantization bit number of 8 bits, and then sent to line memories (FIFO memories) 3a to 3d as pre-stage storage means. On the other hand, the image capture start signal 16 shown in FIG. 2 is sent from the processor (CPU) 8 to the synchronization signal generation circuit / address counter circuit 4, and when the capture is possible, the synchronization signal generation circuit / address counter circuit 4 The effective pixel area signal 18 having a pulse width of 512 samples shown in FIG. 2 is sent to the memory R / W control circuit 5.

Here, the memory R / W control circuit 5 is configured as shown in FIG.
, An image capture signal 10 for writing image data to the line memories 3a to 3d, a line memory read signal 17 for reading image data from these line memories, and these line memories Has a function of generating a field buffer write signal for executing an operation of writing the image data read out from the memory into the field buffer storage device 6 as the subsequent storage means, and has a capture permission corresponding to each of the four ITV cameras. The processor 8 has a register, and a code for instructing the capture permission only in the capture permission register corresponding to the ITV camera on which the image processing is to be executed is stored by the processor 8 in advance. In addition,
In the operation of this embodiment, as described later,
A permission code is stored in the capture permission register so that image processing is executed only for cameras other than the V camera 1c.

When the effective pixel area signal 18 is input from the synchronization signal generation circuit / address counter circuit 4 to the memory R / W control circuit 5, the line memory (FI)
FO) 3a to 3d, only to the line memory corresponding to the capture permission register in which the capture permission code is stored, over the effective pixel area period, the image capture signal 10 shown in FIG.
To execute writing.

When the writing of the first line is completed and the period of the second line is started, not only the writing operation to the line memory but also the image data written to the line memory during the first line period is read and the field buffer is read. Storage device 6
The operation of writing to is also performed.

Here, image data is read from each line memory, as shown by the line memory read signal 17 in FIG. 2, first, one line of image data (image 1) is read from the line memory 3a. When this read operation is completed, next, one line of image data (image 2) is read from the line memory 3b, and finally, one line of image data is read from the line memory 3d.
The reading of the image data (image 4) for the line is executed.

In this embodiment, an NTSC ITV camera is assumed, and one line of the NTSC system is 6 lines.
The effective pixel area is set to 10
Line memory 3 when 512 sampling is performed at MHz
If the clock frequency of the line memory read signal 17 for reading image data from a to 3d is set to 33 MHz as shown in the enlarged view of FIG. 2, the time required to read one line of image data is 15.36μ
s, and 61.5 μs, that is, N
Reading can be completed within one line period of the TSC system. That is, the image data for one line of all cameras can always be transferred to the field buffer storage device 6 with a delay of one line.

As shown in FIG. 1, the processor 8 has a data bus width of 64 bits, and the field buffer storage device 6 has a field buffer memory (FIFO memory) having eight output bits of 8 bits. # 1 to #
8. Then, the image data transferred to the storage device 6 is written as follows.

That is, the field buffer memories # 1 to #
8, a field buffer write signal 12 is supplied from the memory R / W control circuit 5 as shown in FIG. 1, and these signals have the same clock cycle (the same clock) as the line memory read signal 17 described above. 3) for sequentially supplying a write clock to the field buffer memories # 1 to # 8 as shown in FIG.
It consists of S8.

The data sequentially transferred from the line memories (FIFO memories) 3a, 3b, and 3d by these write signals S1 to S8 are as follows. The second pixel is sequentially written to the field buffer memory # 2, the third pixel is sequentially written to the field buffer memory # 3, and the eighth pixel is written to the field buffer memory # 8. After the writing, the ninth pixel returns to the field buffer memory # 1 again to perform writing. 512 for one line from the line memory 3a
After writing the transfer data of the pixel, the next line memory 3b
From the line memory 3d.
This write operation is continued until the transfer data of the last line from is written.

In the case of this writing operation, similarly to the case of writing to the line memories 3a to 3d by the image fetching signal 10, the contents of the pre-set fetch permission register for each camera are set by the processor 8. Based on memory R / W
The control circuit 5 is controlled to transfer only the data of the designated line memory. That is, the operation of reading out the image data (image 3) from the line memory 3c for which the capture is not specified and writing it into the field buffer storage device 6 is not executed (the line memory readout signal 17 in FIG. 2).
Shows this.) As a result, the number of unnecessary data accesses performed by the processor 8 to the field buffer storage device 6 is reduced.

On the other hand, the processor 8 monitors the processing line number signal 13 from the memory R / W control circuit 5 and, depending on the fetching state, reads out the respective lines from the field buffer memories # 1 to # 8 of the field buffer storage device 6. Data for one pixel is taken out at the same time, that is, data for 64 bits / 8 pixels is taken out by one access, and an internal operation is performed.
5 to work memory and program memory 7
A enables high-speed transfer. In addition, by employing a FIFO memory that can be accessed asynchronously, unnecessary waiting time of a processor caused by executing data transfer simultaneously with image capture is eliminated, and higher-speed image processing is realized.

For reference, four of the ITV cameras 1a to 1d
FIG. 4 shows an output format from the field buffer storage device 6 when the image processing is executed for all the image signals. As shown in this figure, the captured data for 8 pixels is always a continuous data configuration from the same camera, so that it is not necessary to rearrange the captured data, and the camera number and line The address corresponding to the number is switched and supplied to the address bus 14 so that the DMA
By transferring, the configuration can be the same as the configuration of the conventional image memory. Further, which area of the work memory and the program memory 7 is transferred can be flexibly changed by software, so that only necessary parts can be stored in the memory.

As in the prior art, the number of pixels in one memory access is small, or even if a plurality of pixels can be simultaneously captured in one memory access, the data of another camera image is included in the data. In this case, the access frequency is increased and the processing speed is reduced. However, in the present embodiment, the processor 8 and the work memory and the The number of transfers between the program memories 7 is reduced, and high-speed image processing can be realized.

According to this embodiment, the following effects can be obtained.

(1) The line memories (FIFO memories) 3a to 3d as the pre-stage storage means are provided in each ITV camera 1a.
1d are continuously taken in, and at the same time, a fixed amount of data is output intermittently. Further, the output frequency is made higher than the capture frequency, and control is performed so that the output periods of the line memories at the preceding stages do not overlap, so that the field buffer memories (FIFO memories) # 1 to # 8 as the succeeding stage storing means can all be output. Image data from an ITV camera.

(2) The data sent from the preceding line memory in pixel units is transferred to a plurality of subsequent field buffer memories # 1 to # 8 (8 bits × 8) corresponding to the bus width (64 bits) of the processor 8. (64 bits), the processor can access the subsequent field buffer memories # 1 to # 8 in units of a plurality of pixels that match the data width, thereby enabling high-speed access.

(3) By employing a FIFO memory which can be accessed asynchronously as the pre-stage and post-stage storage means, data transfer is performed simultaneously with image capture, and unnecessary waiting time of the processor 8 associated with these is eliminated. , Realizing faster image processing.

(4) Data to be written into each FIFO memory provided in the field buffer storage device 6 as a post-stage storage means is written in the output format as shown in FIG. In the access operation, a plurality of pixel data obtained by one access is set so as to be composed of only pixel data from only one imaging device, so that it is not necessary to rearrange the captured data. .

In the above embodiment, a plurality of I
Although the high-speed image processing device is configured to simultaneously capture images from the TV camera, only one ITV camera can be connected, and the image processing device is configured to process image data from the connected ITV camera. In the case of a configuration, a configuration may be adopted in which data obtained by AD-converting the image signal from the ITV camera is directly supplied to the field buffer storage device without passing through a line memory. At this time, a clock having the same cycle as the clock for AD conversion can be used as a clock for writing to the field buffer storage device, and the image data written to each field buffer memory of the field buffer storage device is expanded by the processor. It is possible to perform high-speed image processing by accessing with the set bus width.

In the above-described embodiment, an ITV camera is used as an imaging device. However, it is needless to say that the high-speed image processing device of the present invention can be applied to other imaging devices. It is possible to apply the high-speed image processing apparatus of the present invention to imaging devices of various television systems other than the above by appropriately changing the pulse width and the period of each pulse signal shown in FIGS. it can.

The high-speed image processing apparatus of the present invention
Even an imaging device that simultaneously outputs the image signals of the D field and the EVEN field and an imaging device that uses an interlaced scanning or a non-interlaced scanning as a scanning method can be easily connected by setting switching of software.

Although the embodiments of the present invention have been described above, it is obvious to those skilled in the art that the present invention is not limited to the embodiments and various modifications and changes can be made within the scope of the claims. There will be.

[0042]

As described in detail above, according to the present invention,
Data can be taken simultaneously or individually from one or more imaging devices. The image processing can be executed in parallel with the fetching, and the number of data accesses of the processor is reduced, thereby realizing high-speed image processing. Further, since the increase in the number of components due to the expansion of the data bus is suppressed as much as possible, a high-speed high-speed image processing apparatus can be configured at low cost.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an embodiment of a high-speed image processing method and apparatus according to the present invention.

FIG. 2 is a time chart showing waveforms of an image capture start signal, a horizontal synchronization signal, an image signal, an effective pixel area signal, an image capture signal, and a line memory read signal in the embodiment.

FIG. 3 shows a line memory read signal according to the embodiment;
5 is a time chart illustrating a field buffer write signal and an operation of a processor.

FIG. 4 is an explanatory diagram of an example of an output format from a field buffer storage device according to the embodiment;

FIG. 5 is a block circuit diagram of a conventional image processing apparatus.

[Explanation of symbols]

 1a-1d, 20 ITV camera 2a-2d, 21 A / D converter 3a-3d Line memory (FIFO memory) 4,22 Synchronous signal generation / address counter circuit 5 Memory R / W control circuit 6 Field buffer storage device 7 Work memory And program memory 8,24 processor 14,32,33 address bus 15,34,35 data bus 23 address switch 25a-25n image memory unit 26,27 bidirectional 3-state buffer 28 image memory

Claims (7)

[Claims] 1. An image pickup apparatus, comprising: a storage unit connected to the image pickup apparatus via an interface; and a processor, wherein the processor accesses the storage unit and outputs bits corresponding to a bus width of the processor. When the image data from the image pickup device is taken in, the storage means collectively reads the read data by the number of the plurality of pieces of pixel data obtained by one access in the collective access operation of the storage means by the processor. A high-speed image processing method characterized in that the setting is made up of only pixel data from only one imaging device. 2. A storage capable of taking in and storing image data from the image pickup device via an interface connecting the processor and the image pickup device and reading out data in parallel with the number of output bits corresponding to the bus width of the processor. Means, wherein the processor accesses the storage means and collectively reads in read data with the number of output bits corresponding to the bus width of the processor. 3. A processor, an interface for connecting a plurality of image pickup devices, and an image pickup device provided corresponding to each of the image pickup devices connected to the interface, for temporarily storing image data from the corresponding image pickup device. A plurality of pre-stage storage means, and a post-stage storage means provided at a subsequent stage of the plurality of pre-stage storage means and capable of outputting read data in parallel with an output bit number corresponding to a bus width of the processor. The image data stored in the plurality of pre-stage storage means,
A predetermined amount of data is sequentially read out for each individual pre-stage storage unit at a higher speed than at the time of accumulation, transferred to the post-stage storage unit and written, and the processor accesses the post-stage storage unit and corresponds to the bus width of the processor. A high-speed image processing apparatus characterized in that read data is fetched collectively by the number of output bits. 4. The high-speed image processing apparatus according to claim 3, wherein each of the plurality of preceding storage units is an asynchronous FIFO memory. 5. The high-speed image according to claim 3, wherein said second-stage storage means includes a plurality of asynchronous FIFO memories, and a total sum of output bits of each FIFO memory corresponds to a bus width of said processor. Processing equipment. 6. The write data to each FIFO memory provided in the post-stage storage means is stored in each FIFO memory by the processor.
6. The high-speed image processing according to claim 5, wherein in the collective access operation of the O memory, a plurality of pixel data obtained by one access is set to be constituted only by pixel data from only one imaging device. apparatus. 7. A system according to claim 3, further comprising a selection unit configured to select and capture only image data from a desired imaging device among a plurality of imaging devices connected to the interface. , 5 or 6.