JP2003259220A - Image data processor, imaging system, image data processing method, computer program and computer readable storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct the defect of data outputted from an image sensor in real time without needing a conventionally required frame memory. <P>SOLUTION: The address of a particular pixel on an image sensor 101 is stored in a memory part 106, a counter 108 indicates the current address of data outputted from the image sensor 101, an address decoding part 109 detects a coincidence between the address of the particular pixel stored in the memory part 106 and the current address indicated by the counter 106, and an image correcting part 103 corrects pixel data corresponding to the current address and outputted from the image sensor 101, so that the defect of the data from the image sensor 101 can be corrected, thereby eliminating the need for the conventionally required frame memory. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing device, an imaging system, an image data processing method, a computer program, and a computer-readable storage medium, and in particular, it is used for correcting data from an image sensor. It is suitable.

[0002]

2. Description of the Related Art Image sensors have a certain probability of having pixel point defects. Conventionally, the point defect has been corrected by the following method. 1) The address of the point defect of the pixel is stored in the memory in advance. 2) Store the data from the image sensor in the frame memory. 3) Of each pixel data of the data stored in the frame memory, the pixel data corresponding to the address stored in the memory is interpolated by the calculation using the peripheral pixel data.

[0003]

However, in this method,
A frame memory that supports all screens is required, which leads to an increase in cost, and the number of frame outputs per unit time is reduced by the defect correction process because the calculation is performed after one image data is taken. There were problems such as being lost.

Further, when this system is adopted, in order to complete the processing within a time period that can withstand actual use, the processing IC needs to operate at a clock faster than the processing operation of the image sensor. In such a case, there is a drawback that the noise generated by the IC is transmitted to the image sensor and the image quality is deteriorated.

The present invention has been made in view of the above-mentioned problems, and makes it possible to perform defect correction of data output from an image sensor in real time without requiring a frame memory which has been conventionally required. The purpose is to

[0006]

An image data processing device of the present invention is an image data processing device connected to an image sensor for sequentially outputting pixel data, and stores an address of a specific pixel on the image sensor. A storage unit, a correction unit that performs a correction process on pixel data input from the image sensor when a correction instruction is given, and pixel data corresponding to an address of the specific pixel is input from the image sensor to the correction unit. And a correction instruction output means for outputting the correction instruction to the correction means in synchronism therewith.

Another feature of the image data processing device of the present invention is that the image data processing device is configured to be connectable to the output terminal of the image sensor,
Address data is read from a memory that stores an address of a specific pixel on the image sensor, a shift register is set based on the address data, and the shift register is operated in synchronization with the data from the image sensor to operate the image. It is characterized in that the pixel correction for the data from the sensor is controlled.

Another feature of the image data processing device of the present invention is that in an image data processing device configured to be connectable to an output terminal of an image sensor, an address of a specific pixel on the image sensor is set. Address data is read from a memory to be stored, and one of a plurality of shift registers is set based on the address data, and at the same time, another shift register is operated in synchronization with the data from the image sensor to control pixel correction. It is characterized by being configured.

The image pickup system of the present invention comprises at least an optical system for forming a subject image, an image sensor for outputting the subject image formed by the optical system as an image signal, the image data processing device, and Signal processing means for processing an output signal from the image data processing device.

An image data processing method of the present invention is an image data processing method for processing pixel data sequentially output from an image sensor, wherein the pixel data input from the image sensor when a correction instruction is given. And a correction instruction output procedure for outputting the correction instruction in synchronization with pixel data corresponding to an address of a specific pixel being input from the image sensor. Is.

Another feature of the image data processing method of the present invention is an image data processing method for processing data from an image sensor, the memory storing an address of a specific pixel on the image sensor. Reading address data from the image sensor, setting a shift register based on the address data, and operating the shift register in synchronization with the data from the image sensor to control pixel correction for the data from the image sensor. It is what

Another feature of the image data processing method of the present invention is an image data processing method for processing data from an image sensor, which stores an address of a specific pixel on the image sensor. Read address data from the memory, set one of a plurality of shift registers based on the address data, and simultaneously operate another shift register in synchronization with the data from the image sensor to control pixel correction. It is characterized by.

A computer program of the present invention is a computer program for causing a computer to execute processing of pixel data sequentially output from an image sensor, wherein the pixel data input from the image sensor when a correction instruction is given. And a correction instruction output process for outputting the correction instruction in synchronization with the pixel data corresponding to the address of the specific pixel input from the image sensor. Is.

Another feature of the computer program of the present invention is a computer program for causing a computer to execute processing of pixel data sequentially output from an image sensor, which is an address of a specific pixel on the image sensor. Read address data from a memory storing the data, set a shift register based on the address data, and operate the shift register in synchronization with the data from the image sensor to control pixel correction for the data from the image sensor. It is characterized by causing a computer to execute the processing.

Another feature of the computer program of the present invention is a computer program for causing a computer to execute processing of pixel data sequentially output from the image sensor, the specific pixel on the image sensor. The address data is read from the memory that stores the address, and one of the plurality of shift registers is set based on the address data. At the same time, another shift register is operated in synchronization with the data from the image sensor to perform pixel correction. It is characterized by causing a computer to execute a process for controlling.

A computer-readable storage medium according to the present invention is characterized by storing the above computer program.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an image data processing device, an image pickup system, an image data processing method, a computer program, and a computer-readable storage medium according to the present invention will be described below with reference to the accompanying drawings.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a functional block diagram of the image data processing device 113 according to this embodiment. An image sensor 101 is a data generation source and is connected to the image data processing device 113.

In the image data processing device 113,
Reference numeral 102 is an input terminal of the image data processing device 113. An image correction unit 103 performs a pixel correction process, and outputs an input terminal 104 to which data from the image sensor 101 is input, an input terminal 105 to which a pixel correction instruction signal from the shift register 110 is input, and a pixel correction result. It has an output terminal 112.

An address holding memory unit 106 holds the address data to be corrected, and the data is stored in an arbitrary format. A memory fetch unit 107 fetches the memory data held in the address holding memory unit 106 in units of a predetermined correction target address. Reference numeral 108 is a row counter.

Reference numeral 109 is an address decoder to which the information of the row counter 108 and the information of the correction target address from the memory fetch unit 107 are input. 110 is a 1-bit serial shift register,
9, the pixel correction instruction signal is sent from the final stage 111 to the input terminal 10 of the image correction unit 103.
Output to 5.

Next, the operation of this functional block will be described. In the present embodiment, it is assumed that the addresses of the correction target pixels are sorted in ascending order of the row numbers as an array of addresses in the address holding memory unit 106.

First, the shift register 110 is completely initialized. Here, the initial state is "0" and the correction instruction signal is "1". During the initialization processing period of the shift register 110, the address data is read from the address holding memory unit 106 to the memory fetch unit 107. This address data has information indicating the row and column of the correction target pixel.

On the other hand, the row counter 108 holds the current row number to be corrected.

In the address decoder 109, the two line numbers of the line number contained in the address data of the memory fetch unit 107 and the line number held in the line counter 108 are compared. A decode signal is sent to the shift register 110 on the assumption that the column number fetched by the memory fetch unit 107 indicates a pixel to be corrected. For example, the memory fetch unit 10
If the column number fetched in 7 is number 10, “1” is written in the 10th position of the shift register 110.

After that, the next address data is fetched,
Address decoding and shift register 11 similar to the above
Initialization processing of 0 is performed. Also, this operation is temporarily stopped when the line numbers do not match.

Next, the pixel correction period (shift register 11
0 operation period). First, the image sensor 1
Shift register 110 at the same rate as the data from 01
To operate. For example, if the data in the 10th column of a certain row is a pixel to be corrected, while the 10 pixel data from the image sensor 101 arrive at the input terminal 104,
The pixel correction instruction signal of the shift register 110 is just shifted to the instruction signal input terminal 105 during the initialization processing,
A pixel correction instruction signal is input to the image correction unit 103 at the same time when the pixel data of the tenth column is input to the image correction unit 103.

The image correction unit 103 receives the pixel correction instruction signal from the shift register 110, performs some predetermined image correction processing, and outputs the result to the output terminal 11.
Output from 2.

Here, the shift register 110 cannot perform its initialization processing and correction processing (shift processing for outputting a pixel correction signal) at the same time, so scheduling is required. The concept will be described with reference to FIG. FIG. 2 shows a shift register 1 focusing on a predetermined row.
It is a figure showing the initialization processing of No. 10, and the flow of amendment.

Reference numeral 201 shows the processing operation of the image sensor 101 with respect to the flow of time, and reference numeral 202 shows the processing operation of the shift register 110 (correction circuit) corresponding thereto. Since the image sensor 101 has a horizontal blanking period during which the pixel data is not output while the row changes, for example, in the horizontal blanking period of the n-th row, decoding and correction data of the n-th row are performed. The shift register 110 is initialized. After the initialization processing, the shift register 110 is operated in synchronization with the pixel data from the image sensor 101, and predetermined pixel data is corrected.

Here, regarding the image sensor 101,
For example, CMOS sensors, CCDs, other devices, etc. can be considered. In the present invention, the image sensor 1
It is applicable regardless of the type of 01.

In the present embodiment, the image sensor 1
01 is a direct correction device (image data processing device 113)
It is connected to the. Whether the data format in the meantime is analog data / digital data is not limited here. For example, the analog data from the image sensor 101 is directly corrected (image data processing device 1
It may be processed in 13), or the data once AD-converted may be processed.

As a concept of memory fetch / address decoding, it is assumed that rows are sorted in ascending order, and when the rows match, the position of the column fetched by the memory is decoded. The shift register 110 is set, the processing is repeated until the rows do not match, and the memory fetch is stopped there.

However, the algorithm is not limited to this, and any method may be used as long as the address to be corrected can be searched from the scratch address group. For example, each time one line is advanced, the memory in which the address is stored may be scanned from the beginning to the end to find the address. in this case,
It takes a lot of time to make the decision because it needs to scan the entire memory, but it removes the premise that the addresses must be sorted.

Although the content of the image correction processing in the image correction unit 103 is not mentioned here, any effect can be obtained as long as the correction is performed according to the pixel correction instruction from the shift register 110. Can be played. For example, the image correction unit 103 may include a delay element, and the value of one pixel or a plurality of pixels before may be output as the corrected pixel output. Alternatively, for example, the image correction unit 103 may have a delay element and a delay output function, and may output a value after one pixel or a plurality of pixels as a corrected pixel output.

Further, in the above two methods, the pixel correction can be performed only by using the data of the same row, and the correlation between the correction result of the pixel and the upper and lower peripheral pixels becomes irrelevant. Since the correlation with the upper and lower peripheral pixels is not irrelevant, for example, the correction circuit may have a line memory for several rows, a calculation function, and a delay output function, and may output the correction result of adjacent addition.
In this case, the output is delayed by one line or several lines from the input.

The line counter 108 uses the word line, but is not limited to this. When pixels are divided into groups, the concept of rows is only introduced here for the purpose of identifying the groups, and may be called, for example, a group counter.

Further, the number of columns and the number of stages of the shift register 110 must correspond in this embodiment. For example, when the number of columns of the image sensor 101 is 3000, the number of stages of the shift register 110 is also required to be 3000. Note that, for example, when it is desired to correct only the first n pixels, the circuit scale can be reduced by limiting the number of stages of the shift register 110 to n stages.

Further, in the circuit manufacturing process, the circuit scale can be reduced by forming the shift register 110, the image correction section 103 and the like on the same semiconductor chip.

Further, before the pixel reading is started, it is necessary to initialize the correction data of a predetermined row in the determined horizontal blanking period. As a method of responding to this request, 1) the specification is made such that the number of pixels to be corrected per row that does not allow the initialization processing during the horizontal blanking period is allowed, and 2) the pixel number of the pixels is changed as soon as the initialization processing is completed. It is conceivable to devise timing generation so as to start reading. Both are design items and do not limit the effects of the present invention.

In order to minimize the noise generated by the processing IC, the frequency of the clock used for the memory fetch at the time of the initialization processing should be as low as possible. In such a case, it is necessary to optimize the usable clock speed and the number of pixels to be corrected, but these are also design items.

In the present embodiment, the instruction signal is given to the 10th register in order to correct the pixels in the 10th column. However, for example, the instruction signal is shifted once in order to correct the pixels in the 1st column (head). If is not required, an instruction signal may be given to the ninth register. When it is necessary to perform dummy shifts several times to correct the leading pixel, the instruction signal may be set at a register position in anticipation thereof.

As described above, with the configuration of this embodiment, the pixel data corresponding to the address of the pixel to be corrected is transferred from the image sensor 101 to the image correction unit 10.
Since the pixel correction instruction signal is output from the shift register 110 to the image correction unit 103 in synchronization with the input to the image correction unit 3, the defect correction of the data output from the image sensor 101 can be performed in real time. It is possible to eliminate the conventionally required frame memory. As a result, the circuit scale can be made smaller than that of the conventional correction circuit, and by adopting a circuit that can be driven at a low clock frequency, it is possible to realize image data processing with less superimposed noise.

Further, by synchronizing the pixel correction instruction signal from the shift register 110 and the pixel data fetched from the image sensor 101, the pixel to be corrected can be processed accurately.

Further, the shift register 110 is used by utilizing the period in which the pixel data is not output from the image sensor 101.
By performing the initialization process of, the time required for the initialization process can be effectively reduced to zero. This makes it possible to realize a higher frame rate.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. 3, 4 and 5. FIG. 3 is a functional block diagram of the image data processing device in this embodiment. The constituent elements described in the first embodiment are designated by the same reference numerals, and the differences from the first embodiment will be mainly described below.

In this embodiment, the address decoder 109
Sets a plurality of shift registers. In this embodiment, the case where the first shift register 110 and the second shift register 301 have two shift registers will be described.

As shown in FIG. 3, the shift register 11
Reference numerals 0 and 301 respectively have initialization enable terminals 303 and 304, and accept an instruction from the address decoder 109 only when an initialization enable instruction is received. On the contrary, the shift register that has not received the instruction for the initialization process performs the shift process for outputting the pixel correction instruction signal.

First and second shift registers 101, 3
The final stages 111 and 302 of 01 are connected to the instruction signal input terminal 105 of the image correction unit 103 via the selector 305. Further, the row counter 108 of the first embodiment is renamed here as a group counter 306.

Next, the operation of this functional block will be described.
Basically, the same operation as that of the first embodiment is performed. The difference is that the first and second shift registers 1 configured in parallel are
This is an operation related to 10, 301 and the selector 305.
For example, when the first shift register 110 is being initialized, the selector 305 sets the final stage 302 of the second shift register to the instruction signal input terminal 1 of the image correction unit 103.
05, and the second shift register 301 sends a pixel correction instruction signal to the image correction unit 103. When the second shift register 301 is initialized, the reverse processing operation is performed.

Next, the schedule of the initialization processing and the correction processing (shift processing for outputting the pixel correction signal) of the image data processing apparatus of this embodiment will be described with reference to FIG. Here, reference numeral 401 schematically shows the processing operation of the image sensor 101 with respect to the time axis. For example, for access to the n-th row, the horizontal blanking period 4
02 and a pixel reading period 403. Here, the n-th row reading period 403 is divided into four, and the first group reading period 404, the second group reading period 405,
Third group readout period 406, fourth group readout period 407
It is composed of. Also, 408 is the previous row n
It is the fourth group readout period of the -1st row.

In the first shift register 110,
During the fourth group reading of the (n-1) th row, the image sensor 1
The pixel correction processing operation is performed in synchronization with the pixel data from 01 (409). Further, in the second shift register 301, the initialization processing of the first group data of the nth row to be read next is performed (410). In this way, each shift register performs the operation of repeating the initialization process and the correction process alternately.

Next, the effect of this embodiment will be described. In the first embodiment, since the initialization processing of the correction data of the nth row is performed only in the horizontal blank period, it is necessary to set the column for the nth row in that period. For example, if the image sensor 101 has 3000 columns, 3000 shift registers are required.

On the other hand, in the present embodiment, for example, 3000 columns are divided into 4 groups of 750 columns, and 750 columns are divided into 4 groups.
The number of shift registers required can be reduced by preparing two shift registers in parallel. Furthermore, for example, if it is divided into 300 groups instead of 4 groups, it is sufficient to have two shift registers of 10 stages in parallel, which can drastically reduce the circuit scale required for the shift register.

Here, there may be a case in which there are a large number of pixels to be corrected and the initialization processing time as shown in FIG. The image sensor 101, which has become unusable due to insufficient initialization processing time, becomes a defective product, which causes a reduction in yield. To increase the initialization processing time, the memory fetch unit 10
7, the number of address decoder units 109 and the number of shift registers arranged in parallel may be increased.

FIG. 5 is a schedule diagram when the memory fetch unit 107 and the address decoder unit 109 are increased by one and the shift register is further increased by two in the image data processing device shown in FIG. As shown in FIG. 5, the first shift register 501 and the second shift register 502 are in charge of the correction processing of the even group, and the new third shift controlled by the expanded memory fetch unit and address decoder unit. By configuring the register 503 and the fourth shift register 504 so as to be in charge of the correction processing of the odd group, the double data initialization processing period can be secured. Furthermore, if it is desired to increase the initialization processing period, a memory fetch unit, an address decoder unit, and a shift register may be added.

As described above, with the configuration of this embodiment, a faster frame rate can be realized even in an image sensor having a large number of pixels per row. Further, pixel data corresponding to the address of the pixel to be corrected is transferred from the image sensor 101 to the image correction unit 1.
Shift register 110, in synchronization with the input to 03.
Since the pixel correction instruction signal is output to the image correction unit 103 from any one of 301, it is possible to eliminate the conventionally required frame memory. As a result, the circuit scale can be made smaller than that of the conventional correction circuit, and by adopting a circuit that can be driven at a low clock frequency, an image data processing device with less superimposed noise can be realized. .

Further, even in an image sensor having a larger number of pixels per row, the pixel correction instruction signal from the shift register 110 and the pixel data fetched from the image sensor 101 are synchronized to accurately process the pixel to be corrected. be able to.

Further, by having a plurality of shift registers and sequentially initializing the other shift registers while one shift register is performing the correction operation, the time required for the initialization process is effectively made. Can be zero.
This makes it possible to realize a higher frame rate.

(Third Embodiment) Next, the image data processing apparatus according to the present invention is used as an image pickup apparatus (digital camera).
An embodiment when applied to is described.

FIG. 6 is a block diagram showing an example in which the image data processing device according to the present invention is applied to an image pickup device.

In FIG. 6, reference numeral 11 is a barrier which also serves as a main switch for protecting the lens 12, a lens 12 for forming an optical image of a subject on the image sensor 14, and a diaphragm 13 for varying the amount of light passing through the lens 12. Reference numeral 14 denotes an image sensor for taking in a subject image formed by the lens 12 as an image signal. Reference numeral 15 denotes an image data processing device according to the present invention, which is an image for correcting a defect of an image signal output from the image sensor 14. It has a correction unit 18. Reference numeral 16 denotes an A / D converter that performs analog-digital conversion of the image signal output from the image data processing device 15, and 17 performs various corrections on the image data output from the A / D converter 16, or converts the data. A signal processing unit for compression. Here, the image data processing device 15
Image sensor 14, A / D converter 16, image correction unit 1
8 and a drive circuit that supplies a timing signal to the signal processing unit 17 and the like, and the image correction unit 18 and the drive circuit are formed on the same semiconductor chip. Further, the image sensor processing device 15 may be at a stage subsequent to the A / D converter 16.

Reference numeral 19 is an overall control / arithmetic unit for controlling various calculations and the entire image pickup apparatus, 20 is an image data memory unit for temporarily storing image data, and 21 is for recording or reading on a storage medium. Is a removable storage medium such as a semiconductor memory for recording or reading image data, and 23 is an external interface for connecting to an external computer or the like.

Next, the operation of the image pickup apparatus having the above-mentioned structure at the time of shooting will be described. First, when the barrier 11 is opened, the main power source is turned on, then the control system power source is turned on, and then the image pickup system circuit such as the A / D converter 16 is turned on.

Next, the signal output from the image sensor 14 is corrected by the image correction unit 18 if there is a defective pixel signal in the image sensor processing device 15, and the A / D converter 1
6 is output to the A / D converter 16, converted by the A / D converter 16, and then input to the signal processing unit 17.

Then, the signal processing unit 17 performs predetermined processing, and the output image data is processed by the overall control / calculation unit 19
Is written in the image data memory unit 20 by. Next, the data accumulated in the image data memory unit 20 is recorded in the storage medium 22 via the storage medium control interface unit 21 under the control of the overall control / arithmetic unit 19. Further, the image data may be processed by directly inputting it to a computer or the like through the external interface unit 23.

With the configuration of this embodiment, the defect of the image signal output from the image sensor 14 can be corrected, and an image pickup device with high image quality can be realized.

(Other Embodiments of the Present Invention) The present invention may be applied to a system including a plurality of devices or an apparatus including a single device.

In the above embodiment, the address holding memory unit 106, the memory fetch unit 107, the row counter 1
Although the 08, the group counter 306, the address decoder 109, etc. are composed of functional blocks, a general-purpose control device,
For example, even if those functions are realized by software by some CPU, the same effect can be obtained. That is,
Various devices are operated so as to realize the functions of the above-described embodiments, and the above-described embodiment is performed on a computer in an apparatus or system connected to the various devices from a storage medium or via a transmission medium such as the Internet. Of the present invention, by supplying the program code of software for realizing the function of the above form and operating the above various devices according to the program stored in the computer (CPU or MPU) of the system or apparatus. Included in the category.

In this case, the program code itself of the software realizes the functions of the above-described embodiments, and the program code itself and means for supplying the program code to the computer, for example, such program. The storage medium storing the code constitutes the present invention. A storage medium for storing the program code is, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-R.
An OM, a magnetic tape, a non-volatile memory card, a ROM or the like can be used.

Further, the computer executes the supplied program code so that not only the functions described in the above embodiments are realized, but also the OS (operating system) in which the program code is operating in the computer. Alternatively, the program code is also included in the embodiments of the present invention when the functions described in the above embodiments are implemented jointly by other application software or the like.

Further, after the supplied program code is stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the function expansion board or function expansion unit is instructed based on the instruction of the program code. The present invention also includes a case where the CPU or the like included in the above performs a part or all of the actual processing and the processing realizes the functions of the above-described embodiments.

[0073]

According to the present invention, the correction instruction can be output in synchronization with the pixel data corresponding to the address of the specific pixel, for example, the pixel to be corrected, input from the image sensor. The defect correction of the data output from can be performed in real time, and the conventionally required frame memory can be eliminated. As a result, the circuit scale can be made smaller than that of the conventional correction circuit, and by adopting a circuit that can be driven at a low clock frequency, it is possible to realize image data processing with less superimposed noise. Also, since it is no longer necessary to load the frame memory once,
It becomes possible to realize a higher frame rate.

Further, by synchronizing the pixel correction instruction signal and the pixel data fetched from the image sensor, the pixel to be corrected can be processed accurately.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an image data processing device according to a first embodiment.

FIG. 2 is a diagram showing a flow of initialization processing and correction processing of the image data processing apparatus according to the first embodiment.

FIG. 3 is a functional block diagram of an image data processing device according to a second embodiment.

FIG. 4 is a diagram showing a flow of initialization processing and correction processing of the image data processing device according to the second embodiment.

FIG. 5 is a diagram showing a flow of initialization processing and correction processing of the image data processing device according to the second embodiment.

FIG. 6 is a block diagram showing an example in which the image data processing device according to the present invention is applied to an imaging device.

[Explanation of symbols]

101 image sensor 102 input terminals 103 image correction unit 104 input terminals 105 Instruction signal input terminal 106 address holding memory unit 107 memory fetch unit 108 line counter 109 address decoder 110 shift register 111 Final stage of shift register 112 output terminals 113 Image data processing device

Claims (18)

[Claims] 1. An image data processing device connected to an image sensor for sequentially outputting pixel data, comprising: storage means for storing an address of a specific pixel on the image sensor; and the image when a correction instruction is given. A correction unit that performs a correction process on pixel data input from a sensor, and a correction instruction to the correction unit in synchronization with pixel data corresponding to the address of the specific pixel being input from the image sensor to the correction unit. An image data processing device, comprising: a correction instruction output means for outputting 2. An image data processing device configured to be connectable to an output terminal of an image sensor that outputs image data by dividing it into pixel data groups, the address of one or more specific pixels on the image sensor. A memory unit for storing a memory, a group counter for indicating a current pixel data group output from the image sensor, a memory data fetch unit for reading the address of the specific pixel from the memory unit, and a memory data fetch unit for reading. An address decoding unit that determines whether or not the pixel data group to which the address of the issued specific pixel belongs and the pixel data group designated by the group counter are matched, and according to the determination result by the address decoding unit. A shift register for generating a correction instruction signal; And an image correction unit that corrects the pixel data output from the image sensor based on the correction instruction signal generated by the image data processing apparatus. 3. The image according to claim 2, wherein the shift register shifts in synchronization with pixel data appearing at an output terminal of the image sensor to output the correction instruction signal to the image correction unit. Data processing device. 4. A pixel data group and a next pixel data group continuously appear at a predetermined interval at an output terminal of the image sensor, and the shift register is initialized during a period of the predetermined interval. The image data processing apparatus according to claim 2 or 3, wherein 5. An image data processing device configured to be connectable to an output terminal of an image sensor for outputting image data by dividing it into pixel data groups, the address of one or more specific pixels on the image sensor. A memory section that stores a memory cell, a group counter that indicates a group that divides the current pixel data group output from the image sensor into predetermined sections, and a memory data fetch that reads the address of the specific pixel stored in the memory section. A unit, an address decoding unit that determines whether the group to which the address of the specific pixel read by the memory data fetch unit belongs and the group indicated by the group counter match, and the address decoding unit A plurality of shift registers that generate a correction instruction signal according to the determination result of An image data processing device, comprising: an image correction unit that corrects pixel data output from the image sensor based on a correction instruction signal from a shift register connected through a selector. 6. The plurality of shift registers shifts alternately in synchronization with pixel data appearing at an output terminal of the image sensor and outputs the correction instruction signal to the image correction unit, every time the group changes. The image data processing device according to claim 5, wherein 7. The plurality of shift registers are such that while one shift register is outputting the correction instruction signal to the image correction section, the other shift registers are initialized. The image data processing device according to claim 5 or 6. 8. The image data processing device according to claim 2, wherein the shift register and the image correction unit are formed on the same semiconductor chip. 9. An image data processing device configured to be connectable to an output terminal of an image sensor, wherein address data is read from a memory that stores an address of a specific pixel on the image sensor, and shifts based on the address data. An image data processing device, characterized in that a register is set and the shift register is operated in synchronization with the data from the image sensor to control pixel correction for the data from the image sensor. 10. An image data processing device configured to be connectable to an output terminal of an image sensor, wherein address data is read from a memory storing an address of a specific pixel on the image sensor, and a plurality of address data are read based on the address data. 2. An image data processing apparatus, characterized in that any one of the shift registers is set, and at the same time, another shift register is operated in synchronization with data from the image sensor to control pixel correction. 11. At least an optical system for forming a subject image, an image sensor for outputting the subject image formed by the optical system as an image signal, and the image sensor according to claim 1. 2. An image pickup system, comprising: the image data processing device according to claim 1; and signal processing means for processing an output signal from the image data processing device. 12. An image data processing method for processing pixel data sequentially output from an image sensor, the correction procedure performing a correction process on pixel data input from the image sensor when a correction instruction is given. And a correction instruction output procedure for outputting the correction instruction in synchronization with pixel data corresponding to an address of a specific pixel from the image sensor. 13. An image data processing method for processing data from an image sensor, comprising: reading address data from a memory storing an address of a specific pixel on the image sensor; and a shift register based on the address data. Is set, and the shift register is operated in synchronization with the data from the image sensor to control the pixel correction for the data from the image sensor. 14. An image data processing method for processing data from an image sensor, comprising: reading address data from a memory storing an address of a specific pixel on the image sensor; An image data processing method, wherein any one of the shift registers is set, and at the same time, another shift register is operated in synchronization with data from the image sensor to control pixel correction. 15. A computer program for causing a computer to execute processing of pixel data sequentially output from an image sensor, wherein the pixel data input from the image sensor is corrected when a correction instruction is given. A computer program that executes a process and a correction instruction output process that outputs the correction instruction in synchronization with pixel data corresponding to an address of a specific pixel from the image sensor. 16. A computer program for causing a computer to execute processing of pixel data sequentially output from an image sensor, the address data being read from a memory storing an address of a specific pixel on the image sensor, A shift register is set based on the data, and the computer is caused to perform a process of controlling the pixel correction for the data from the image sensor by operating the shift register in synchronization with the data from the image sensor. Computer program. 17. A computer program for causing a computer to execute processing of pixel data sequentially output from an image sensor, the address data being read from a memory storing an address of a specific pixel on the image sensor, One of the plurality of shift registers is set based on the data, and at the same time, the computer is caused to execute a process of controlling another pixel correction by operating another shift register in synchronization with the data from the image sensor. Computer program. 18. A computer-readable storage medium on which the computer program according to claim 15 is stored.