JPS60235274A - Picture signal processing device - Google Patents

Abstract

PURPOSE:To make the real time processing of a picture signal possible by constituting picture data memories in parallel and performing parallel processing of address arithmetic and picture arithmetic. CONSTITUTION:A digital video signal which is subjected to A/D conversion and should be processed is inputted from a terminal 9 and is divided into three by a multiplexer 2-1 and is divided into nine finally by multiplexers 2-2-2-4, and divided data are distributed and stored in memory blocks 1-1-1-9 respectively. The address calculated by a block 5 consisting of an ALU, a multiplier, etc. is sent to address decoders 3-1-3-6 of memories 1-1-1-9, and data of the picture element in the designated address and data of 8 picture elements around it are read out simultaneously. In this parallel read, the address is allowed to pass circuits 4-1-4-4 which increase or reduce address data because these data cannot be read by the same address. Contents of memories are stored in a local memory 6 in parallel, and data of interpolation or the like obtained from address arithmetic is written in a memory 7, and contents of memories 6 and 7 are processed in a picture data arithmetic part 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal processing device that can perform image processing involving address calculation at high speed.

The configuration of the conventional example and its problems
Compact, high-speed processors and memories are used for various signal processing using rated circuit technology.

Especially for advanced processing, DSP (digi
A processor called a talsignal processor is used. This is A L U (a
It has a dedicated multiplier etc. in addition to the lithometric logic unit, and can process data at high speed. At present, signals in the audio band can be processed in real time using these tools.

The average instruction cycle of a DSP is about 250 nS. If audio sampling is 20 KHz, one sampling time is 50 μs, so the number of commands that can be processed within this time is 200. If this number of commands is possible, a large amount of processing is possible, and real-time processing such as voice recognition and synthesis, and various band compressions for digital transmission is possible.

On the other hand, consider the case of image processing such as medical use and pattern recognition. For audio signals, the sampling is at most 50K[z, and for image signals, the sampling is 10 to 20M.
High as IIz. Therefore, when image processing is executed in real time, a processing speed of two orders of magnitude or more is required compared to processing of audio signals. For example, if a video signal is sampled at 10M1lz, in the case of an audio signal, even if the number of processing is small, it will be sampled at 10M1lz within this sampling time.
Processing of 00 instructions or more is required. In other words, real-time processing cannot be performed unless the instruction cycle time is 1 ns or less.

One possible way to achieve this is to improve the performance of the device. The current ll5P is MO3 type LSI
Since this DSP is composed of bipolar type I,
If you use SI, you can increase the speed. However, with current technology, it is only possible to speed up the difference by about one order of magnitude.

On the other hand, parallel processing has been considered as a system-based method, and a completely parallel processing method has been proposed in which ALUs and multipliers for pixels are arranged in an array. However, the system becomes extremely large, the wiring connecting the ALUs and multipliers becomes complicated, and a main processor is required to control each of the ALUs, resulting in a very large system.

By the way, the amount of data of a video signal is extremely large, and it is said that 4 Mb1t8 times is required as a memory for one frame. Although MOS type memory is suitable for large-capacity memories, it takes time to write and read data, and it is impossible to input and output data in real time. Although bipolar memory is fast, its memory capacity is small, making it unsuitable for storing image data.

As stated above, it is difficult to process image signals in real time with current devices. In view of these conventional shortcomings,
The present invention provides an image signal processing device that enables real-time processing by using a parallel configuration of one image data memory and parallel processing of address calculations and image data calculations.

Components of the Invention Means for dividing an image memory into a plurality of parts and storing image data therein; and arithmetic means for exclusively calculating an address;
This is a means to set each address of the divided memory to the calculated address.

This image signal processing device includes image data calculation means that performs image processing on local image data centered around a calculated address read out from a memory based on the data of the address calculation means.

DESCRIPTION OF THE EMBODIMENTS Image processing may involve arithmetic processing, such as edge detection, using pixel data of approximately 3×3 or 5×5, centering around the pixel to be processed.

? 2. Intervention 1: All you have to do is read the pixel data into the 1r-th In, and the processing speed can be increased. On the other hand, other image processing uses a small number of pixels, such as image rotation, enlargement, or reduction, but it may not be possible to predict in advance which pixels will be used. Moreover, it takes a lot of time to calculate the address of the memory containing that pixel. In this case, random reading of the memory and high-speed calculations are difficult.

The present invention is suitable for such image processing, and will be explained below based on the embodiment shown in FIG. (1-1) to (1-9) are image data memories that divide one frame into nine pieces. (2-1) to (2-4) are multiplexers for distributing pixel data to each memory, (3-1) to (3-6)
are memory address decoders, (4-1) to (4-4)
is a counter that increments or decrements the address data, and 5 is the person L U (arlthmetlc
lo@1cun4t) and a multiplier, 6 is a local memory that stores part of the pixel data, 7 is a memory that stores the content to be processed based on the address calculation result, and 8 is a memory that stores new pixel data from the pixel data. AL for calculation
This is a pixel data calculation unit including U and a multiplier. 9 is an image data input terminal.

Next, the operation of this embodiment will be explained. First A/
The D-converted digital video signal to be processed is sent to terminal 9.
The signal is input from , is divided into three by the multiplexer (2-1), and divided into nine by the multiplexer (2-2) to (2-4). This divided data is distributed and stored in one memory block.

FIG. 2 shows how image data is divided and stored in memory. 21 represents the position of pixel data of the input image data, and (1-1) to (1-9) represent the positions in which the pixel data is stored in the divided memory of FIG. 1. Unedited image data 1 goes to memory (1-1), data 2
is stored in the memory (1-2), and data 3 is stored in the memory (1-3). Next, data 4 is stored again in the memory (1-1), data 5td- is stored in the memory (1-2), and data 6 is stored in the memo IJ (1-3) next to the previous data.

The following data is stored repeatedly in sequence.

Next, consider vertical storage. The data on the second row is stored in memory blocks (1-4) to (1-6). That is, data 7 is stored in memory (1-4), data 8 is similarly stored in memory (1-complete), and data 9 is stored again in the second row of memory (1-1). Similarly, data 10 is stored in memory (1-4) and data 11 is stored in memory (1-7).

Next, address calculation will be explained. In the case of rotation processing of input image data, in addition to rotation, the position of a pixel in a newly generated image is calculated, and the position of a pixel in the original image corresponds to that position. Since the calculation is performed in accordance with the sweep order of the generated images, the data in the memory is not read out sequentially but at random.

The addresses calculated by the block composed of 5 ALUs, multipliers, etc. are sent to address decoders (3-1) to (3-6) in each memory (1-1) to (1-9). As a result, the data of eight pixels around the designated address are simultaneously read out. Depending on the image processing such as image enlargement, it is necessary to use two pieces of data and interpolate between them, and reading out each image one by one would be too time consuming, so parallel reading is used. In the case of this parallel readout, it may not be possible to read out 3x3 local pixels simply by using the same address, so the address data shown in (4-1) to (4-4) is incremented or decremented. It is necessary to pass the circuit.

This situation will be explained based on FIG. This diagram is the same as the diagram 21 showing the position of pixel data of the input image data in Figure 2, and a part of it is enlarged. The data of the address decoders (3-+) to (3-3) in the X direction will now be explained. Let ■ be the center value of the address data calculated by the address operation. In this case, the data in frame 31 is output.

Therefore, as is clear from FIG. 2, since pixels 1, 2, and 3 are stored at the same address, no address manipulation is necessary. If the calculated address is .largecircle., the pixel data shown in the frame 32 is read out.

As shown in FIG. 2, pixel 4 is stored at the next address, so the address of the memory (1-1) containing this data needs to be incremented by one. If the calculated address is ◎, the pixel data shown in the box 33 is read out. As shown in FIG. 2, pixel 3 is set to the previous address, so the address of the memory (1-3) containing this data needs to be decremented by one.

If the calculated address is ■, the process is the same as the case ■, and the process is repeated in the same way. Address calculation and value setting in the Y direction are also similar to those in the X direction.

With the above operations, the contents of the memory are stored in the local memory 6 in parallel. On the other hand, data such as interpolation generated by address calculation is written to the memory. According to this content, the image data in the local memory is taken into the image data calculation unit 8, and the average value and the like are calculated and output. This output data is output in order in the sweep direction of the generated image.

If this series of operations is pipelined, the calculation speed can be further increased. FIG. 4 shows the timing for pipeline calculation. Operation d is executed according to the timing pulse. First, address calculation is performed and the address is set at the primary timing. Furthermore, reading from the memory and writing to the local memory are performed at the next timing. Calculations are executed in the image data calculation section at the next timing, and data of the generated image is output at the next timing. This pipeline processing is just one example, and it goes without saying that portions where the processing speed is high may be executed within one timing, while portions where the processing speed cannot keep up can be further divided into pipeline processing.

In addition to the effects of the invention, the following effects can be expected from the image processing apparatus of the invention.

(1) Divide and write image data to multiple memories,
Because it is a method in which pixel data in the vicinity of one address is read out in parallel, processing time can be significantly reduced despite the calculation of random readout from memory.

(2) Since a dedicated address calculation section and increment and decrement functions for setting memory addresses are combined, it is easy to set addresses for a plurality of memories.

(3) Since the image data calculation unit is provided separately from the address calculation, the two calculations can be executed separately, the processing capacity can be improved by pipelining, and the calculation unit can be configured to be suitable for each process.

In the embodiment of the present invention, a 3×3 memory configuration using surrounding pixels has been described, but a similar configuration can be applied to a 6×6 or 9×9 memory configuration that also uses pixels located further away.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the image processing device of the present invention, FIG. 2 is a diagram for explaining memory writing in the image processing device of the present invention, and FIG. 3 is a memory of the image processing device of the present invention. FIG. 4, which is a diagram for explaining readout, is a timing diagram for explaining the operation of the image processing apparatus of the present invention. (1-1) to (1-9)... Image data memory, 13.11. 5...Address calculation unit, 8...Image data calculation unit.

Claims (3)

[Claims] (1) A memory composed of a plurality of memory blocks, a means for dividing and storing input data in the memory, a calculation means for calculating the address of a pixel to be processed, and a calculation means for calculating the address of the plurality of memory blocks. and image data calculation means for performing image processing on data read out from the plurality of memories based on the data of the address calculation means. . (2) In the means for setting the addresses of a plurality of memories to the calculated address data, a part of the addresses is incremented or decremented to set the addresses so that the local image data can be simultaneously output. An image signal processing device according to claim 1. (3) Image data around the calculated address is read out at once, and image processing is performed at high speed using these image data. The image signal processing device described.