JPH0719117B2 - Sequencer bit operation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bit operation circuit of a sequencer for processing instructions by hardware.

[Background Art] START, START NOT, AND, AND NOT, OR, OR NO for sequencer
In the case of processing instructions such as T, AND STK, OR STK, and OUT, it was done by software in the past.

By the way, in order to execute the sequence program, the steps of analyzing the sequence command and calculating the contact data are performed. Normally, the contact data is stored as 1-byte data in units of 8 contacts, and the ON / OFF of the OUT command is decided by the processing of 1 bit in the calculation of the contact data, but the detection of the condition of 1 contact and the calculation of preprocessing When performing a logical operation with the result,
Which contact among eight contact units should be processed must be processed by using, for example, 3-bit information stored in the command unit in advance.

When this processing is performed by software using a microcomputer that performs parallel processing in units of 1 byte, the time required for detecting 1-bit information and storing 1-bit information is required for logical operation (AND, OR) There is a problem that it takes longer than the time and the execution time of the entire sequencer is affected.

If the number of steps in the sequence program exceeds 2K steps, the input / output response of the sequencer will be lengthened due to the effect of the execution processing time due to cyclic calculation, and with the aim of expanding the application field, the application instructions will be enhanced and peripheral devices Even if the expansion is performed, the scope of the description may be restricted.

Therefore, in a sequencer that has several hundred I / O points or more, it is required to shorten the execution time. Therefore, the above-mentioned 3-bit information is used to automatically detect and set bits, and to operate at the same time. If the hardware capable of executing the processing instructions is configured, the time required for software is shortened and the efficiency of program execution is improved.

[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a bit operation circuit of a sequencer in which the execution time of instruction processing is shortened by using hardware. .

DISCLOSURE OF THE INVENTION FIG. 1 is a block diagram showing the input / output relationship of the bit arithmetic circuit A of this embodiment. The bit arithmetic circuit A serves as an I / O port for a microcomputer (not shown) of a sequencer. The data bus transfers data D0 to D7, and the address bus sends port addresses PA0 to PA6, and the control bus sends write signal WR, read signal RD, and chip enable signal CE0. It comes to wear. FIG. 2 shows a specific circuit of the bit operation circuit A, which is a 1-byte register 1 for chip-enable 1-byte 8-contact data sent via the data bus 7 and storing it when the write signal WR is input. When,
When the A12 terminal is "L", the data of 8 contacts input to the A0 to A7 terminals is output from the D0 to D7 terminals as it is, and the A12 terminal is "H".
At this time, A8 is used to specify which of the 8 contacts
~ EPROM2 for outputting data selected by 3-bit information input to the A10 terminal, data selectors 3 and 4 for executing storage and logical operation of one contact extracted by 3-bit information, and D-type flip-flop 5 , A shift register 6, a demultiplexer 8 and a logic gate.

More specifically, EPROM2 consists of 8K bytes, and AROM
When 2 terminals are "L" (OUT instruction), 8-bit data of A0 to A7 terminals are output from D0 to D7 terminals as they are, and when A12 terminal is "H" (arithmetic instruction), A0 to A7 terminals Of the input,
3-bit information from the A8 to A10 pins that specifies which bit is set, and the input data from the A11 pin is set to the specified position. D0 to D7
FIG. 5 is a diagram for explaining the internal data of the EPROM2, which is output from the terminal. FIG. 5A shows the case where the A12 terminal is “H” (arithmetic instruction), and FIG. Indicates that the A12 terminal is "L" (OUT instruction), and the A12 terminal is "H"
At this time, the input of the A11 terminal is set to the predetermined terminal D by the 3-bit information of the A8 to A10 terminals. Where EPROM2 A12
The port address PA3 is input to, and the port addresses PA0 to PA2 are input to A8 to A10. The Q output of the flip-flop 5 is input to A11. 6 (a) (b) (c)
The data registration state of the EPROM2 is shown. In FIG. 9A, the data input to the A0 to A7 terminals is written as it is at each address of the lower 4 Kbytes. The figure (b) shows the registered data of 2K bytes of 1000 to 17FF in the upper 4K.
In this registration data, "0" is written in the bit selected by 3 bits of A8 to A10. The same figure (c) shows the remaining 2K bytes (1800-1FFF) of registration data.
In this registration data, "1" is written in the bit selected by 3 bits of A8 to A10.

FIGS. 7 to 9 are flowcharts of the data registration method for the EPROM 2 in FIGS. 6A to 6C, respectively, where K is the EPROM2 address, j is the counter value, and FIG.
i is data, l and m are bits, CALL (i, l), CALL (i,
m) is "0" or "1" for the 1st or mth bit of data i, respectively.
Shows a subroutine for.

Therefore, it is handled as a part of I / O port and a chip enable signal is used as a port selection signal from the microcomputer.
CE0 is set to "L" to enable each circuit element, and then the data of 8 contacts of 1 byte is sent to the bit arithmetic circuit A together with the WR signal and the data is stored in the register 1. Next, when the instruction used for the sequencer is set to the port address and the RD signal is sent, 1 byte of data will be output. Where the command OR NOT, AND NOT, OR ,, AND, ST
ART NOT, START, OR SKT, AND STK, OUT and port address PA
The relationship between 0 and PA6 is set in the embodiment as shown in FIG. The instruction data of these 9 instructions are composed of 3 byte instructions as shown in FIG. 4, and the instruction part is composed of a 4 bit port address forming the instruction code and a 3 bit port address forming the bit select information. Become.

When executing the OUT instruction, the port address PA3 is "H".
Therefore, the CE1 signal is not generated and the demultiplexer 8
Since the data selectors 3 and 4 are not enabled and the flip-flop 5 is in the set state, the output Q of the flip-flop 5 is input to the A11 terminal of the EPROM 2 and the three bits A8 to A10 corresponding to the output Q are input. The data selected by the information (port address PA0 to PA2) is read from the EPROM 2 and sent through the data bus 7.

On the other hand, when the logical operation (including the START instruction) is executed, the port address PA3 is "L", and therefore the chip enable signal CE1 is input to the data selectors 3 and 4 to be enabled.
Further, from the EPROM 2, the data of 8 contacts input to the terminals A0 to A7 are sent as they are through the data bus 7.
Further, the data is input to the data selector 3 and 1 bit selected by the 3-bit information of the port address PA0 to PA2, that is, ON / OFF information of the 1-contact a contact and b-contact is output from the Y and Y terminals of the data select 3. To be done. These outputs are input to AND gates 9 and 10 and OR gates 11 and 12, respectively, and are also input to D4 and D5 of the data selector 4, respectively. The input signals respectively inputted to the AND gates 9 and 10 and the OR gates 11 and 12 are subjected to logical operation of AND, AND NOT, OR and OR NOT by the Q output of the flip-flop 5 and the result is obtained from the data selector 4. Input to D3 to D0 pins. Then, based on the above 3-bit information of the instruction part, OR NOT, AND N
The outputs of the D0 to D5 terminals are selected by the data selector 4 in accordance with the OT, OR, AND, START NOT, and START instructions and set in the flip-flop 5.

Here, when the START instruction and the START NOT instruction are executed, after the contact data is set in the flip-flop 5, Q
The output is input to the shift register 6 and left-shifted.

The outputs of the shift registers QA and QB are AND gate 13 and OR gate 14.
To the D7 and D6 terminals of the data selector 4 and set to the flip-flop 5 for AND STK instruction and OR STK instruction, respectively. It is supposed to be done. And output QB after data set to flip-flop 5
Is right-shifted in the direction of QA.

When the START command continues, for example, the START command-AND / OR command continues, and the START command-AND / OR again without the OUT command.
When the instruction continues, the operation result after the START instruction is registered in the shift register 6 as a stack, and AND STK, OR STK
In the case of an instruction, it has a so-called FASTIN-LASTOUT structure by shifting to the right after the operation is completed.

〔The invention's effect〕

Since the present invention is configured as described above, the instruction processing can be logically operated only by transferring the contact data and the instruction code and the select information signal as the port address. Compared with the case where the processing is performed by software, the time can be greatly reduced, and the sequencer can be expanded. In particular, the EPROM itself will have arithmetic functions, and by combining small-scale logic circuits
A high-speed arithmetic circuit can be configured without developing an LSI, which has the great economic effect.

[Brief description of drawings]

FIG. 1 is an overall schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the same as above, FIG. 3 is an explanatory diagram of a relation between an instruction and a port address of the same as above, and FIG. 4 is a sequencer instruction code of the same as above. Configuration diagram, Fig. 5 (a) and (b) are the same EP
FIG. 6A to FIG. 6C are explanatory diagrams of the internal data of the ROM, FIG. 6A to FIG. 6C are explanatory diagrams of the registered data of the EPROM of the same, and FIGS. 7 to 9 are flowcharts of the writing method of the registered data of the EPROM of the same. Yes, A is a bit arithmetic circuit, PA0 to PA6 are port addresses, 1 is a register, 2 is EPROM, 3 and 4 are data selectors,
5 is a flip-flop, 6 is a shift register, and 9, 10, 13 are A
ND gates, 11, 12, and 14 are OR gates.

Claims (1)

[Claims] 1. A register for storing contact data composed of a plurality of bits in which information of one contact corresponds to one bit, and a state of each contact is registered in advance to specify a bit of the contact data and a specific one of the contact data. An EPROM that reads registered data based on a predetermined number of select information bits that specify a contact point, an identification bit that identifies the OUT instruction of the sequencer, and a bit that inputs the operation result, and the above except when the OUT instruction is input. EPRO
From the first data selector that inputs the 1-contact information of the bit designated by the select information bit of the registration data read from M to the logic circuit, and the operation result of the logic circuit and the first data selector. And a flip-flop for storing the signal selected by the second data selector and outputting it as an operation result to the EPROM. Is AND, AND
The logical operation of NOT, OR, OR NOT is performed by the output of the flip-flop and the output of the first data selector, and the instruction of the sequencer including the OUT instruction and the select information bit are composed of a port address of a plurality of bits. When the identification bit of the EPROM stands as an OUT instruction, the operation result is output from the EPROM by replacing the input contact data with the contact data previously registered as the data of one contact designated by the select information bit. A bit arithmetic circuit of a sequencer, wherein registered data having the same content as the input contact data is output from the EPROM when the above does not occur.