JPS5930105A - Output controlling system of process input/output control device - Google Patents

Abstract

PURPOSE:To execute an on-and-off control of an optional controlled system without storing the process control information, by storing in advance a logical operation command for turning on and off a controlled system, together with a channel address data for selecting an output device. CONSTITUTION:An address CHA of an output device 4, which is sent through a bus D from a processing device which is not shown in the figure, and a control signal SET or CLR which turns on or off a controlled system are accumulated in a register 1. A decoder 2 selects the output device 4 by the CHA, and sends out an output data in an output data register 41 to a logical circuit 3 through a gate 42. The logical circuit 3 operates logically said output data and a control data whose only bit corresponding to a controlled system to be varied to an on or off-state, which is sent from the processing device continuously through the bus D is ''1'', at every one bit in accordance with said control signal, an its result is set as an output data to the data register 41. This output data controls the controlled system to on or off through a signal matching circuit 43.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output control method for a process input/output control device 4.

When a processing device such as a microcomputer is used to turn on or off a control object on the process side such as a motor contactor, solenoid valve, or lamp, the above-mentioned Place, i
, 111 device 1°'L
The process control information generated by the processing device is output to the output device (1) connected to the process input/output side M11 device via this process input/output control device, and Process side fQl i-r'i
In addition to recording the information, a process control signal may be sent to the process side via the signal matching circuit, and this communication is performed by a single process side for each word, which is the 71st processing position of the processing unit. Since it is economically disadvantageous to divide 11 signals, each process side 7+ for each bit of each word.
It is common to divide the III information so that one word can handle multiple pieces of process control information.
The f-report is generated as one piece of data and outputted to each output device to turn on and off the control target 11. Therefore, any control (if(
l It is necessary to perform a so-called focusing operation to turn on and off only the target, and in this case, the conventional method (e. A process fill lit information storage area is provided to store data consisting of several pieces of process control information that are exactly the same. , the process side 1All (i'I) of the control target that is to be turned on and off in the processing device is stored in the process control information record 1. (6 degrees outside the χ area,
nil Writes or clears the specified process control information (Mll information, executes a logic i7 calculation that does not change other process control (?f information, and stores the result in the process control IR? information). In addition to re-storing the area,
The focus operation was realized by outputting an output connected to the process input/output open side 1 device ID:.

However, according to this conventional method, it is necessary to prepare in advance a process control f, ηl information storage area in the storage device for storing process control information for each control target to be turned on or off, and Each time a controlled object is turned on or off, the processing device must read data from the process control information storage area, perform a logical operation, and store the result back in the process control information storage area. There were drawbacks such as the complexity involved.

The present invention aims to solve the above-mentioned problems, and it is possible to turn on and off only an arbitrary controlled object connected to the output device 1T, without having to provide an information storage area in the process side body 11. This invention realizes an output control system for a process input/output control device, and the content of the present invention will be explained in detail below based on one embodiment with reference to the drawings.

The drawing is a block diagram showing an embodiment of a process input/output control system (output control system) according to the present invention.

The channel address register 1 contains channel address data Cl-1 for selecting the output device 4 connected to the process input/output control device, and logical operation command Sr' for specifying the logical operation for the output device 1-4. ;i' and CLvL, and receives channel address data CIIA, logic operation commands SET-O and CLIL, and all-memory retention 411 command input from the processing device (not shown) through the processing device data bus l). signal CllAl,
According to IC, note 1 and ζf1 are left blank.

The channel address decoder 2 sends the selection signal CH to each output device i, t to the channel address data CII stored and held in the channel address register l.
This is for decoding to O, CI-II, . . . CII+n.

The logic operation circuit 3 inputs the logic 6' (rF command IT and CLT) stored in the channel address register l.
Based on L, a logical OR operation is performed between the data held by the output device (the data on the ID and the data on the processor data bus I), the logical f/(the result of the operation and the data on the processor data bus I) ) Output the data of J2 to the respective output devices (optical input data path OI). In the figure, the circuit shown inside the logic operation circuit 3 is a circuit for one bit in order to explain the function of the logic operation circuit 3.
OGn is output device held data/(any 1 bit i of bus ID (I 11 and processing unit 1'L data bus J)) rln's logic value II' (1[logic to perform calculation fft+ gate, 8011 is an arbitrary pin of the output device ijj holding data bus TD) idn and the processing device 1'1
Any 1 bit of data bus I) dn's negation [1i] AND gate %U1n is an arbitrary 1 bit of Gouyannel address register l) 3-man power logic 7 which outputs dn The product gate 02n is a logical product gate that outputs the logical product n result of the logical sum gate 00 only when the logic of the logical operation command SET stored in the channel address register 1 is "1". i3n is an AND gate that outputs the logic operation result of the AND gate AGn only when the logic of the logic addition command CLIL stored in the channel address register 1 is "1"; 0411 is 1) 11 logic; rtt gate Gln +
This is a three-way OR gate that outputs the outputs of 0211 and G3n to any one pin of the input data bus OT) and 0 (Ill).

The input/output control device rt for this embodiment 111 is composed of two channel address registers 1, a digital channel address decoder 2, and an AND circuit 3.

The output devices 1 and 4 shown in the figure are the process input/output control devices.
The selection signal CI is traced at the back of the connected output device.
Since the output/device selected by IQ is t), 711 (of which 40 is an AND gate of the 41 output signal Cll0 and the output holding command signal OUi' from the processing device, 4
1 is determined by the output of the AND gate 40.
At the I edge, write the data on the output device input data bus OD. 1 holds 1'='? 42 is an output data input gate for outputting the time keeping data of the output data register 41 to the output device holding data bus II when the logic Jlj of No. 3 C110 is rlJ; Process the data held in register 41
This is a signal matching circuit for sending signals to other controlled objects.

In the device constructed as described above, first, the output device i! A case will be described in which one arbitrary control object among the control objects connected to L4 is turned on.

Input the channel address data C) which should select the output device 4 into the processing device (takes the address Cll0) and the logic r11 (data which sets the logic of the calculation command SET to I'll). The i+! input into the channel address register l at iL, and store t'<holding command signal CI
When stored and retained by TAL, channel address data CIIA is decoded by channel address data 2, the logic of selection signal 0110 for selecting output device 1 and 4 is set to "1", and the retained data input gate of output device 4 is 42 and outputs the data held in the output data register 41 to the output color (currently held data bus II). On the other hand, logical product 3'? 'The logic, I, and command I'll' input to the circuit 3 act to open the AND gate (12) of each pit.Next, the processing device 1' attempts to turn on. Generates data that sets the logic of the process control information of the controlled object to rlJ and sets the logic of the process control information of the controlled object that does not change the output state to "0", and sends this data through the processing device quasi-data bus D to the logical operation circuit. 3, the logic of each pit of the logic operation circuit 3 is input to the logic 311 gate) QG, and the logic of each pit is input between the data of the output inkstone 11°C [1t data bus II) and the data of the processing unit data bus I). Wahama~1 is executed and the logical rl is sent on the processor data bus I)
Lun J-ri (11 gate 0), a pit that is 1' above J
The output of (,) is the logic rlJ, the processing unit;
11 gate (output device 1゛η holding data bus H whose output corresponds to this pit) pit logic J A and 1 Tsuji - 11 □ 1 u (conari, respectively logic gate (]2)
Ethics, 111 gate (4) is output on the output device input data bus OD.At this time, when output holding command signal OU'l' is outputted to the processing device, the logic of the output device 4 is output. (the output of the gate 40 becomes the logic riJ, =, and at its leading edge the data of the output i% li'c input data bus 01) is written on the output data l/disk 41 1, (
) is held and this held data is transmitted to the controlled object on the process side through the signal matching circuit 43, so that the process control information can be controlled without changing the output state of the controlled object that has set the logic of the process control information to rOJ in the processing device. till
111 object whose l information logic is set to "1" is set to logic "1"
” In other words, it can be turned on.

Next, among the control objects connected to the output device 4, any λ:
(Meat the controlled object l, l) Combine 1 and ii! −
f, lJ'l.

Channel address data C [IA and logical operation command CI
, It generates data that sets the logic of It to "1", inputs this data to the channel address register l through the processing device (data bus I), and outputs the memory retention command signal CIIA.
When the C memory is held by L, the channel address data CIIA is decoded by the channel address decoder 2 and a selection signal CI for selecting the output device 4 is generated.
The logic of IQ is set to rlJ, the held data input card 42 of the output device 44 is opened, and the held data of the output data register 41 is outputted to the output device time holding data bus ID. On the other hand, the logic operation command CL inputted to the logic operation circuit 3 opens the AND gate G3 of each bit (
This is working. Next, data is generated in which the logic of the process control i11 li'r information of the controlled object to be turned off by the processing device F is rlJ, and the logic of the process control information of the controlled object whose output state does not change is rOJ. , this data is input to the logic operation circuit 3 through the processing device data bus
? An AND operation of each pitch Hσ is performed between the data on the data bus II) and the data on the processing device i'L data bus D. At this time, since the input terminal on the processing device data bus D side of each bit of logic O/(game) AU is in negative logic, the logic is "1" on the processing device i' (data bus D).
(logical product game of the bits whose output is logical)
0'', the output of the bit C) whose logic becomes rOJ on the processing device data bus D becomes the same logic as the logic of the output device holding data bus II) corresponding to this bit, and each Logic J/(Game) 03 and Logic Sokuwa Game) (Output 94 from J4 ifi input data bus O
It is output on D. At this time, when the processing device outputs the output holding command signal OUT, the logic of the output device 4, bI
] The output of the gate 40 becomes logic "1", and in the preceding row, the data on the data bus OD for 40 output devices is stored and held in the output data register 41, and the held data is sent to the control TI target on the process side through the matching circuit 43. Since the data is sent to the processing device f, the process controller rIj
The logic of the process control information is set to "1" without changing the output state of the control object whose logic is set to "0".
” The logic of the control object + is set to “0” and the logic is turned off.
can be turned on.

As explained in detail below, according to the output side (Illll system) of the process output control device according to the present invention, it is possible to select the output device without providing a process control information storage area in the storage device. Logical operation 3' of whether to turn on or off the controlled object along with the channel address data
Y, store the command in the channel address register and output device P? , by simply inputting the data whose process control information logic is rlJ for the controlled object that you want to turn on or off, you can switch any controlled object connected to any output device of λ1 to any other controlled object. It can be turned on and off without affecting the output state of the device.

[Brief explanation of the drawing]

The drawing shows a process input/output control device 1ffi according to the present invention.
FIG. 2 is a block diagram showing an example of an actual hfli method of the output side p111 method of FIG. 1...Channel address register, 2...
・Channel address decoder, 3...Logic operation circuit, 4...Output device r(s 41...
...Output data register, 42...Holding data input gate, 43...Signal matching circuit, 518T,
CI, IL... Logical operation ζ1. Command, CII Person°・°°Channel Address Data, C1ap, 0
111~C11 mouth...selection (i(-number, D...
...Processing device data bus, 11) ...Output device i/1 holding data bus, OD...Output device 19. Input data bus〇Patent applicant Toyoden 1-Iku Seizo Co., Ltd. Representative Atsushi Doi

Claims (1)

[Claims] Channel address data for selecting the output device and logic for commanding whether to turn it on or off! T! a channel address register that stores and holds data consisting of operation commands through a processing device data bus; a channel address decoder that decodes the channel address data into an output device selection signal; and an output device ξ held data based on the logical operation commands. An input/output control device i, which is equipped with a logical operation circuit for performing a logical OR operation or a logical f^ operation for each bit between the data on the bus and the data on the processing device data bus, and an output data register. ,
A plurality of signal matching circuits for transmitting signals from the output data register to a process control target; and a held data input gate for outputting held data in the output data register to an output device held data bus in response to the output device selection signal. The output device causes the processing device to input the processing device data bus to store in the channel address register the logical operation command to turn on or turn off the controlled object together with the channel address data that first selects the output device 19°. , Next, data that sets the logic of the process control information of the process control target to be turned on and off to "1" is input to the logic illusion 1 circuit, and the data of the output device holding data bus and the data of the output device holding data bus are input based on the logic operation command. By performing a logical operation on each bit between and storing the result in the output data register through the output device's next input data bus, any controlled object connected to any output device can be connected to any other output device. /l'! It is possible to turn on and off without affecting the output state of the controlled object. Y m is the output side fItII method of the process input/output control device rt.