JPS6221122B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output control device for a process input/output control device.

With processing equipment such as microcomputers,
When trying to turn on and off control objects on the process side, such as motor contactors, solenoid valves, or lamps, and especially when there are many control objects, connect a process input/output control device to the processing device, The process control information generated in the processing device is output to the output device connected to the process input/output control device via this process input/output control device, and the process control information is recorded and held in the output device, and signal matching is performed. Process control signals may be transmitted to the process side via a circuit. It is common practice to allocate each piece of process control information to each bit of a word so that one word can handle multiple pieces of process control information. The control target is turned on and off by generating one piece of data and outputting it to each output device. For this reason, it is necessary to perform so-called bit operation to turn on or off only a desired controlled object without affecting the output status of other controlled objects connected to the same output device. The method is to provide a process control information storage area in a storage device for each address of the storage device to store data consisting of a plurality of pieces of process control information that are exactly the same when stored and retained by each output device. When turning on or off a specific controlled object, data containing process control information of the controlled object to be turned on or off in the processing device is read from the process control information storage area, and the process control of the specific controlled object is read out from the process control information storage area. Setting or clearing information, performing logical operations that do not change other process control information, restoring the results to the process control information storage area, and outputting the results connected to the process input/output control device. This allowed bit manipulation to be realized.

However, according to this conventional method, it is necessary to prepare in advance a process control information storage area in the storage device to store process control information for each control target to be turned on or off.
In addition, each time a control target is turned on or off, data must be read from the process control information storage area, a logical operation is performed, and the result must be stored again in the process control information storage area. There were drawbacks such as the complexity of programming the device.

The present invention aims to solve the above-mentioned problems,
This is an output control device for a process input/output control device that can turn on and off any control target connected to an output device without having to provide a process control information storage area. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The content of the present invention will be explained in detail based on one embodiment with reference to the drawings.

The drawing is a block diagram showing an embodiment of an output control device of a process input/output control device according to the present invention.

The channel address register 1 holds channel address data CHA for selecting the output device 4 connected to the process input/output control device, and logical operation commands SET and CLR for specifying logical operations for the output device 4. , channel address data CHA and logical operation commands SET and CLR inputted from a processing device (not shown) through a processing device data bus D are stored and held by a storage holding command signal CHAL.

The channel address decoder 2 is for decoding the channel address data CHA stored and held in the channel address register 1 into selection signals CH0, CH1, . . . CHm for each output device.

The logic operation circuit 3 outputs the data bus held by the output device based on the logic operation commands SET and CLR stored in the channel address register 1.
The results of the logical sum and logical AND operations between the data on the ID and the data on the processing device data bus D and the data on the processing device data bus D are output to the output device input data bus OD, respectively. In the figure, the circuit shown inside the logic operation circuit 3 is a circuit for one bit in order to explain the function of the logic operation circuit 3, and OGn is an arbitrary 1 bit idn of the output device holding data bus ID. An OR gate that performs a logical sum operation on any 1 bit dn of the processing device data bus D, and AGn is a negative logic of any 1 bit idn of the output device holding data bus ID and any 1 bit dn of the processing device data bus D. G1n is an AND gate that performs an AND operation with dn of the processing unit data bus D only when the logic operation commands SET and CLR stored in the channel address register 1 are both logic "0". G2n is an AND gate that outputs the logical operation result of the above-mentioned OR gate OGn only when the logic of the logical operation command SET stored in the channel address register 1 is "1". The gate G3n operates as the AND gate only when the logic of the logic operation command CLR stored in the channel address register 1 is "1".
AND gate that outputs the logical operation result of AGn,
G4n is a three-input OR gate that outputs the outputs of the AND gates G1n, G2n and G3n to any one bit Odn of the output device input data bus 0D.

The input/output control device in this embodiment is composed of the above-mentioned channel address register 1, channel address decoder 2, and logic operation circuit 3.

The output device 4 shown in the figure is one of the output devices connected to the process input/output control device that receives a selection signal CH0.
40 is an AND gate of the selection signal CH0 and the output holding command signal OUT from the processing device, and 41 is an output device selected by the output of the AND gate 40. An output data register 42 that stores and holds the data of the output device input data bus OD at the leading edge outputs the data held in the output data register 41 to the output device holding data bus ID when the logic of the selection signal CH0 is "1". holding data input gate, 4
3 is a signal matching circuit for transmitting the data held in the output data register 41 to a control target on the process side.

In the device configured as above, first,
A case will be described in which an arbitrary controlled object among the controlled objects connected to the output device 4 is turned on.

The processing device generates channel address data CHA to select the output device 4 (in this case CH0 is the address) and data to set the logic of the logic operation command SET to "1", and sends this data through the processing device data bus D. When the channel address data CHA is input to the channel address register 1 and stored by the memory retention command signal CHAL, the channel address data CHA is decoded by the channel address decoder 2 and the logic of the selection signal CH0 for selecting the output device 4 is determined. It is set to "1", opens the held data input gate 42 of the output device 4, and acts to output the held data of the output data register 41 to the output device held data bus ID. On the other hand, the logic operation command SET input to the logic operation circuit 3 acts to open the AND gate G2 of each bit. Next, the processing device generates data that sets the logic of the process control information of the controlled object that is to be turned on to "1" and sets the logic of the process control information of the controlled object that does not change the output state to "0". When input to the logic operation circuit 3 through the processing device data bus D, each bit is inputted between the data of the output device holding data bus ID and the data of the processing device data bus D at the OR gate OG of each bit of the logic operation circuit 3. Each logical OR operation is executed, and the output of the OR gate OG of the bit that is a logic "1" on the processor data bus D becomes a logic "1" and becomes a logic "0" on the processor data bus D.
The output of the OR gate OG of the bit that is
The logic is the same as that of the ID bits, and is output onto the output device input data bus OD through the AND gate G2 and the OR gate G4, respectively. At this time, the processing device outputs the output hold command signal OUT.
, the output of the AND gate 40 of the output device 4 becomes logic "1", and at its leading edge, the data on the output device input data bus OD is stored and held in the output data register 41, and this held data is sent to the signal matching circuit. 43 to the controlled object on the process side, control that sets the logic of the process control information to "1" without changing the output state of the controlled object that has set the logic of the process control information to "0" in the processing device. The object can be placed in a logic "1" or on state.

Next, a case will be described in which a desired control object among the control objects connected to the output device 4 is turned off.

The processing device generates channel address data CHA to select the output device 4 and data that sets the logic of the logic operation command CLR to “1”, and inputs this data to the channel address register 1 through the processing device data bus D. Memory retention command signal
When the channel address data CHA is stored and retained by CHAL, the channel address data CHA is decoded by the channel address decoder 2, and the logic of the selection signal CH0 for selecting the output device 4 is set to "1", and the retained data input card of the output device 4 is 42 and outputs the data held in the output data register 41 to the output device holding data bus ID. On the other hand, the logic operation command input to the logic operation circuit 3
CLR acts to open the AND gate G3 of each bit. Next, the processor generates data that sets the logic of the process control information of the control target to be turned off to "1" and the logic of the process control information of the control target that does not change the output state to "0", and this data Processing device data bus D
When the data is input to the logic operation circuit 3 through executed. At this time, since the input terminal on the processor data bus D side of the AND gate AG of each bit is in negative logic, the AND gate of the bits whose logic is "1" on the processor data bus D The output of the AND gate AG of the bit whose logic is "0" on the processing device data bus D is the same as the logic of the output device holding data bus ID corresponding to this bit. , and are output onto the output device input data bus OD through the AND gate G3 and the OR gate G4, respectively. At this time, when the processing device outputs the output holding command signal OUT, the output of the AND gate 40 of the output device 4 becomes logic "1", and at its leading edge, the data on the output device input data bus OD is transferred to the output data register 41. The held data is stored and transmitted to the controlled object on the process side through the signal matching circuit 43, so that the process control information can be controlled without changing the output state of the controlled object whose logic is set to "0" in the processing device. It is possible to set the logic of the control object to "0", that is, turn off, by setting the logic of the control information to "1".

As explained in detail above, according to the output control device of the process input/output control device according to the present invention,
Even if a process control information storage area is not provided in the storage device, the channel address register can be used to store and hold logical operation commands for turning on or off the controlled object along with channel address data for selecting the output device. Simply write data that sets the logic of the process control information of the controlled object you want to turn on or off to "1" for the output device, and you can switch any controlled object connected to any output device to any other controlled object. It is possible to turn it on and off without affecting the output state.

[Brief explanation of the drawing]

The drawing is a block diagram showing an embodiment of an output control device of a process input/output control device according to the present invention. 1... Channel address register, 2... Channel address decoder, 3... Logical operation circuit, 4... Output device, 41... Output data register, 42... Holding data input gate, 43... Signal matching circuit, SET , CLR...Logic operation command,
CHA...Channel address data, CH0,
CH1~CHm...selection signal, D...processing device data bus, ID...output device holding data bus, OD...
...Output device input data bus.

Claims (1)

[Claims] 1 First, data consisting of channel address data for selecting an output device input by the processing device through the processing device data bus and a logical operation command for instructing whether to turn on or turn off the controlled object is stored as a memory retention command from the processing device. a channel address register configured to store and hold data according to a signal; a channel address decoder connected to the channel address register for decoding the channel address data into an output device selection signal; and a channel address decoder connected to the channel address register for decoding the channel address data into an output device selection signal; Between the data of the output device holding data bus based on the calculation command and the data consisting of one or more process control information specifying the process control target to be turned on or off, which is then input by the processing device through the processing device data bus an input/output control device comprising a logic operation circuit configured to perform an OR operation or an AND operation for each bit and output the operation result data to an output device input data bus;
an output data register connected to the output device input data bus and configured to store and hold the calculation result data by an AND signal of the output device selection signal and an output holding command signal from the processing device; and the output data a signal matching circuit for sending a signal from the register to the process control target; and a held data connected to the output data register so as to output the data held in the output data register to the output device holding data bus in response to the output selection signal. 1. An output control device for a process input/output control device, comprising a plurality of output devices each having an input gate.