JPH0452732A - Fuzzy inference mechanism - Google Patents

Abstract

PURPOSE:To change the data in a short time without discontinuing an inference operation by selecting plural data storage parts to a fuzzy inference part with the use of an external selective signal. CONSTITUTION:A fuzzy inference part 6 is connected to a rule membership function memory 1 via an internal data bus 7, and a buffer 8 is provided between the part 6 and the memory 1. Thus the part 6 carries out a fuzzy inference while referring to the data on the memory 1 and based on the input value given to an antecedent part. In this case, if the number of data storage parts (f) and (r) is two, only one of the data storage parts is selected by a selective and connected for reference to the data. Simultaneously, the data stored in the other data storage part are changed. Thus the data stored in both parts (f) and (r) can be changed in a short time while a fuzzy inference operation is carried on.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a fuzzy inference mechanism that performs fuzzy inference based on data input to an antecedent part.

(Prior Art) Conventional fuzzy inference mechanisms include the following. That is, there is one that is roughly configured with a fuzzy inference section that performs fuzzy inference based on input data, and a single data storage section that stores data of rules and membership functions referred to for fuzzy inference.

(Problem to be Solved by the Invention) However, in such a conventional fuzzy inference mechanism, the single data storage section stores only the rules and membership functions that are referenced during inference. There is. Therefore, in order to change data in the data storage unit, the inference operation must be stopped, and the time required to change the data also depends on the amount of data.

The problem is that the length increases depending on the

The present invention has been made by focusing on such conventional problems, and solves the above problems by providing a plurality of data storage sections and making it possible to select and switch between the plurality of data storage sections. The purpose of this invention is to provide a fuzzy inference mechanism that allows data to be changed in a short time without stopping inference.

(Means for Solving the Problems) In order to achieve the above objects, the present invention includes a fuzzy inference section that performs fuzzy inference based on input data to the antecedent section; A plurality of pig storage sections are provided in which data of rules and membership functions are stored, and the plurality of data storage sections can be switched and selected by an external selection signal to the fuzzy inference section.

(Function) Therefore, in the present invention, since the plurality of data storage units storing data such as rules can be switched to the fuzzy inference unit by a selection signal, changing data such as Lulu is required during fuzzy inference. It is possible to change data in a data storage unit that is not referenced. For example, if there are two data storage units, the selection signal selectively connects only one data storage unit to the fuzzy inference unit for data reference, and the other data storage unit is connected to the fuzzy inference unit for data reference. Make changes. Thereby, the data in the pig storage unit can be changed in a short time while the fuzzy inference operation continues.

(Example) An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of a fuzzy inference mechanism according to an embodiment of the present invention. In this figure, numeral 1 denotes a memory in which data such as rules and membership functions are stored, and has two data storage sections, one before and one after the register. Connected to this memory 1 are an address bus 2 for specifying memory addresses, a data bus 3 for exchanging commands and data, and a control bus 4 for exchanging timing information for reading and writing data. The operation of these is controlled by the host CPU 5 which includes a selection signal generating section and the like.

Reference numeral 6 denotes a fuzzy inference section, which is connected to the memory 1 by an internal data bus 7, and a buffer 8 is provided between the memory 1 and the fuzzy inference section 6. This fuzzy inference unit 6 is
While referring to the data in memory 1, fuzzy inference is performed based on the input value to the antecedent part. That is, when data is input to the antecedent section of the fuzzy inference section, fuzzy inference is executed by referring to the data in the data storage section set by the selection signal.

Here, to change data in memory 1,
For data stores that are not referenced during fuzzy inference,
It is designed to allow new data to be written.

FIG. 2 is a detailed diagram of the memory 1 arranged to allow data to be modified during fuzzy inference. The memory 1 has a built-in address decoder 9 that inputs an address signal and a chip select signal.
Registers (data storage units) 0 to N consisting of the following are connected.

The register select signal and the rule change signal are respectively input to the first stage f and the second stage r of the registers 0 to N.

That is, in FIG. 2, when an address signal is input to the address decoder 9, the address bus 9 outputs a corresponding register select signal to the previous stage f of the register. Then, registers 0 to N are designated, and changed data is written to the previous stage f. Thereafter, by inputting a rule change signal to the rear stage r, data is written from the front stage f of the registers θ to N to the rear stage r.

FIG. 3 is an explanatory diagram showing the relationship between each register 0 to N and a signal path. As shown in the figure, registers 0 to N are constituted by twice the number of D-latches corresponding to the width dimension W of the data bus 3. A data bus signal and a register select signal can be input to the input pins D and T in the front stage f of each register 0 to N, respectively, and the input pin D in the rear stage r.

The output signal of the previous stage f and the rule change signal can be input to T.

Therefore, as mentioned above, when the register select signal is manually input to the first stage f, data is written to each register 0 to N, and by asserting the rule change signal to the second stage r, all registers 0 to N are written. The rules and membership functions stored in the first stage f are moved to the second stage r all at once.

In this way, in this embodiment, the subsequent stage r of registers 0 to N is
By asserting the rule change signal, the stored data is transferred from the registers in the first stage f to the registers in the second stage r.

Next, this operation process will be explained using register 0 as an example. It is assumed that each bit of register 0 is constituted by a D-latch, as shown in FIG.

The rule change signal RC is externally applied as an active low signal to the register 0 in the subsequent stage r, and its operation timing is as shown in FIG.

Now, assuming that the initial state is that the output of the front stage f is N7~NO-○○ and the specific output of the rear stage Q7~QO=01, when the register select signal SO changes from "L" to "H", The values of data D7 to DO are taken into register 0 of the previous stage f. Then, the register select signal SO is “L”
Then, since the register 0 of the front stage f is a D-latch, the values of the pigs D7 to DO are in a state of being out of line with the outputs N7 to NO of the front stage f.

Next, when the rule change signal RC changes from "L" to "H", the values of the outputs N7 to NO are taken into register 0 in the subsequent stage r. After this, the rule change signal RC is “L”
'', the register 0 of the front stage f is also a D-latch, so the values of the outputs N7 to NO are in a state of being transparent to the outputs Q7 to QO of the rear stage r, and the data is changed.

Note that the timing chart in FIG. 5 is based on data D7 to D.
This figure shows the operation until O=11 or the register 0 in the subsequent stage r takes in the data.

The membership function of the antecedent part in the register which is the data storage part of this example is an S-type function circuit, a Z-type function circuit, and an M
It is created as an IN circuit. By storing data regarding the slope and position for the S-type function circuit and the Z-type function circuit in a register, the shape of the membership function of the antecedent part can be determined.

The membership function of the consequent part uses a singleton type here, and eight labels are selected according to the data in the register.

Next, we will explain the meanings of the data stored in the registers depending on their shape, with reference to Figure 6. In this figure, the number of rules is four. An example of the configuration is shown.

Register 0 and register 1 are used as data registers for the antecedent part X of rule 1 that is referenced in fuzzy inference. Of these, the lower 3 bits of register 0 (DO-
The slope of the S-type function is stored in the upper 5 bits (corresponding to D3-D7), and the position of the S-type function is stored in the upper 5 bits (corresponding to D3-D7).

Also, the lower 3 bits of register 1 (corresponding to DO-D2)
The slope of the Z-type number is stored in , and the upper 5 bits (D3-D
7) stores the position of the Z type number.

The above also applies to the antecedent parts Y and Z, in which data of the S-type function and the Z-type number are stored.

On the other hand, as a data register for the consequent part of rule 1,
Register 6 is used. This is an 8-bit register, and the lower 3 bits (corresponding to DO-D2) contain 8 bits.
Label data is stored.

Hereinafter, data is stored for the antecedent and consequent parts of Rules 2 to 4 in the same manner as for Rule 1, and the structure of the rule memory is summarized in Table 1.

In addition, the slope 1 position of the S-type function and the Z-type number and the position of the singleton-type membership function are determined by the data DO~D
7 as shown in Tables 2, 3 and 4, respectively.

In Table 2, the slope of the S-type function and the Z-type number indicates that the smaller the number, the gentler the slope.

Table 3 = Position of S function and Z function Table 2 = Slope of S function and 2 functions Table 3: Position of S function and Z function Table 4 = Position of conclusion part membership function Note that the singleton type members in the conclusion part mentioned above The elements of the ship function correspond to the positions shown in Table 4, or from Ql to Q
Each output from 1 corresponds to the position from NL to PL in the graph shown in Fig. 7, and when all the data DO to D2 are "H", that is, in the case of NG, the lulu is invalid. Become.

(Effects of the Invention) As explained above, according to the present invention, a plurality of data storage units storing Luluya membership functions can be selected by the fuzzy inference unit by a selection signal.
Even during inference, change data for rules and membership functions can be written without stopping inference. In this case, the switching of rules and membership functions in the data storage section can be done quickly by simply asserting the selection signal of the data storage section, so even when the amount of pigs is large, switching of the data can be done in an extremely short time. The effect is that it can be processed in a number of ways.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a fuzzy inference mechanism according to an embodiment of the present invention, Fig. 2 is a detailed block diagram of the memory shown in Fig. 1, and Fig. 3 shows the relationship between each register of the memory and information signals. A block diagram, FIG. 4 is a block diagram showing the internal configuration of register 0, FIG. 5 is a timing chart explaining the generation timing of the rule change signal, FIG. 6 is an explanatory diagram showing the correspondence between each register and Lulu, FIG. 7 is an explanatory diagram showing the corresponding positions of membership functions in the conclusion section. 1...Memory 6...Fuzzy inference unit RC...Rule change signal (selection signal) f...Previous stage of register (data storage part) r...Later stage of register (lt)

Claims (1)

[Claims] 1. A fuzzy inference section that performs fuzzy inference based on input data to the antecedent section; and a plurality of data storage sections that store data of rules and membership functions referenced by the fuzzy inference section; A fuzzy inference mechanism characterized in that the storage section can be switched and selected by an external selection signal for the fuzzy inference section.