JPS58201146A - Microprogram controlling system - Google Patents

Abstract

PURPOSE:To access an instruction on the basis of a less branch condition selecting field and a less address field selected on the basis of the contents of the branch condition selecting field, by performing access to a memory according to an (n)-bit condition signal and the contents of the address field. CONSTITUTION:The condition selecting circuit 351 of a multiple branch address selecting circuit 35 selects an (n)-bit branch condition which is referred to during multiple branch among numbers of external conditions according to the contents of a microfield (b) for selecting the branch condition. This branch condition and an address field (a) for indicating which multiple branch refers to the branch condition is regarded as an address to access the memory 352 stored with a branch destination address, obtaining a corresponding branch address MBA. Then, the address MBA is set in an address register 32 through an address sepecifying circuit 33 to access a control memory 31, reading and executing a desired microinstruction.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to microprogram controllers, and more particularly to address sequencing in multiple branch microinstructions.

[Technical background of the invention and its problems]

Microprogram technology, which can be executed in one machine cycle and is programmed in so-called machine processing units to execute software instructions, is often used.

Microprograms are usually stored in a read-only memory called a control memory, and are sequentially read out and executed by a microprogram sequencer. When a branch is required, a branch is sent to a certain microaddress with bt entries. ), it is now possible to perform so-called conditional branching, which examines the conditions to be executed and branches according to those conditions.

That is, the microprogram control device is capable of executing multiple branch microinstructions that determine branch destinations depending on the processing result conditions at that time. Traditionally, this multiple branch microinstruction includes a field in which NEXT address information and multiple branch target selection information are set, and the system is configured based on this selection information and the branch conditions processed up to that point. Selecting one of the branch destinations &.

FIGS. 1 and 2 show the concept of operation according to the conventional system. 1st
In the system shown in the figure, one of the 2n branch instructions Dl to Dn consecutively written with the branch destination start address Branch O as the start address is selected by the multiple branch microinstruction at the memory address N as the selection information be. Select and branch based on external conditions, etc. The branch destination, for example, the instruction D2 is read, and the read branch destination address Bra
The process branches to Branch 2, and the job is executed based on the instructions written in Branch 2. Therefore, in such a multiple branching method, it is necessary to read and execute the instruction D2 midway in order to execute the actually required job according to the conditions at that time.

Therefore, in the case of data processing with a short number of processing steps, this command D! This step has the disadvantage that it takes up a significant portion of the data processing efficiency.

In the system shown in FIG. 2, a multiple branch microinstruction is a branch microinstruction that indicates the upper address of the branch destination start address.
field, n-bit multiple branch destination selection information bo field, and Branch indicating the lower order of the branch destination start address.
It has 1 field. In this case, the actual starting address for multiple branching is the address indicated by the address field with the bo field set to "O". Selection information. A set of n-bit external signals selected by K replaces the bo field to generate the actual branch destination address.

With this method, it is possible to branch directly to the job that is actually required, and there is no reduction in processing efficiency as in the conventional method shown in FIG. However, in this method, processing programs are randomly assigned, and similar processing programs must be assigned to conditions that require the same processing.
The disadvantage is that the required memory capacity is large.

Furthermore, in order to execute multiple branch instructions in both of the above two methods, a selection information field bo and a microfield indicating the branch destination start address are required.If the capacity of the microprogram storage memory is large, the required microfield is large. However, there is a drawback that the field of control commands that can be executed simultaneously becomes smaller.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and provides a microprogram control system configured such that a required instruction can be accessed directly using fewer address fields and branch condition selection fields in multiple branch microinstructions. The purpose is to

[Summary of the invention]

The present invention selects a branch condition supplied from an external source in a multiple branch microinstruction based on the contents of a micro field (branch condition selection field) via a branch condition selection circuit, and The memory is accessed according to the contents of the output n-bit condition signal address field, and this memory output is supplied to the addressing circuit as the corresponding branch destination address.

In addition, microfields can be reduced and redundant branches can be avoided, so efficient sequence control can be realized.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using FIG. 3.

FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, 31 is a control memory in which a microprogram is stored. This control memory 31 is accessed by the microphone date address set in the address register 32.

An address designation circuit 33 (which designates the next address to be executed) is present in the preceding stage of the address register 32, and the address designation circuit 33 includes an address update (+1) circuit 3.
4 output UA, the branch address BA indicated by the micro 6 field, and the multiple branch address MBA which is the output of the multiple branch destination address selection circuit 35 added according to the present invention are supplied, and the function designation part f of the micro field is supplied. One of the addresses is selected and output by the control signal SEL issued through the control signal SEL.

The multiple branch address selection circuit 35 includes a condition selection circuit 351 and a memory 352. The condition selection circuit 351 is supplied with the contents of a microfield (branch condition selection field b) for selecting a branch condition and a large number of external branch conditions. A set of condition signals consisting of n bits selected based on the contents of the branch condition field b is supplied to the memory 35 as a lower address. The memory 352 is also supplied with the contents of a microfield (address field a) for selecting one of a large number of multiple branches using the above set of condition signals as an upper address δ. The memory 352 is accessed by both of the above addresses, and stores branch destination addresses corresponding to the above conditions. This memory 3
The branch destination address obtained from 52 is the address specification circuit 3.
3.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail using FIG. The microinstructions stored in the control memory 31 are normally read out and executed sequentially under the address indicated by the address register 32.

By the way, when the microinstruction specified by the address register 32 is a multiple branch instruction, the address designation circuit 33
selects the multiple branch address MBA'i and supplies it to the address register 32. Multiple branch address MBA at this time
is output as follows.

First, an n-bit branch condition □ to be referred to in multiple branching is selected from a large number of external conditions based on a branch condition selection signal (contents of microfield b for selecting a branch condition). This is condition selection circuit 3
51. Using this branch condition and the contents of address field a (indicating which multiple branch refers to this branch condition) as an address, the memory 352 in which the branch destination address is stored is accessed to obtain the corresponding branch address MBA. Then, this address MBA is set in the address register 32 via the address designation circuit 33,
The control memory 3 is accessed to read a desired microinstruction and execute it.

〔Effect of the invention〕

As described above, according to the present invention, redundant branching can be avoided with a small number of microfields, efficient multiple branching can be realized, and the present invention has the following effects.

(1) Reduction of the multiple branch instruction field and increase of parallel operating instructions due to the reduction of the multiple branch instruction field.

(2) Necessary jobs can be executed without intermediately executing branch instructions that reduce data processing efficiency.

(3) It provides a degree of freedom in program address allocation without increasing the capacity of the microinstruction storage memory.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams showing the operational concept of conventional address sequence control in multiple branch microinstructions, and FIG. 3 is a block diagram showing an embodiment of a microglomodular control device in which the present invention is implemented. 31... Control memory, 32... Address register,
33...Address designation circuit, 34...Address update circuit, 35...Multiple branch destination address selection circuit, 351
...Condition selection circuit, 352...Memory. Applicant's representative Patent attorney Takehiko Suzue Figure 2;

Claims (1)

[Claims] In an information processing device that has a control memory that stores a microprogram and a microprogram addressing circuit, and executes software instructions using a microprogram, the contents of the microfield that selects the branch condition of the microaddress as well as the external a selection circuit that selects one set of condition signals according to supplied branch conditions;
One set of condition signals output by this selection circuit and its first
It has a memory that is accessed by a large number of multiple branches using a set of condition signals (the contents of a micro field that selects one of D) and outputs a branch destination address corresponding to the accessed condition. , a microprogram control system characterized in that this memory output is used as a corresponding branch destination address and is supplied to the addressing circuit.