JPS62191931A - Microprogram control method - Google Patents

Abstract

PURPOSE:To remarkably reduce the capacity of a microprogram required for executing all microinstructions by permitting plural microinstructions to call the microprogram necessary for executing the microprograms in common as a subroutine. CONSTITUTION:Plural microinstructions call and use the microprogram for executing microinstructions as a subroutine in common. When the microinstruction is stored in an instruction storage part 10, the instruction code of the microinstruction becomes a signal 10a and is inputted to the 1st address generator circuit 11. It outputs a microprogram address obtained by synthesizing the contents of the signal 10a and page information specified by a signal 14b as a signal 11a to a microprogram address register 13. A signal 11b denoting that an effective address lies in the signal 11a becomes active. At that time, the microprogram address register 13 stores the signal 11a as an effective microprogram address, and outputs the contents as a signal 13a to a microprogram memory 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control method equipped with a microprogram subroutine, and particularly to a microprogram control method suitable for controlling branching to a subroutine and returning from a subroutine. Regarding the method.

[Conventional technology]

In recent years, MOS (Metal Oxide Sem1c
BACKGROUND ART Due to remarkable progress in onductor technology, high Q product ratios of integrated circuits have progressed, and as a result, high performance and highly functional microcomputers have appeared. Under these circumstances, as logic becomes more complex with higher integration, methods of realizing integrated circuits using logic circuits with a regular structure are becoming mainstream. One of them is a microprogram control method.

In general, in microcomputers that employ a microprogram control system, when deriving a corresponding series of microinstructions from a macroinstruction, a method is adopted in which the address of the first microinstruction in the microinstruction group is obtained using an instruction decoder. .

However, the method using an instruction decoder requires a two-step operation: (1) decoding the instruction to obtain a microprogram address; and (2) obtaining a corresponding microinstruction from the microprogram address. The time it takes to decode an instruction and obtain the microprogram address varies depending on the size of the instruction decoder, but the time it takes to apply the microprogram address and read the microinstruction (
This time is usually approximately equal to one microcycle (hereinafter referred to as one microcycle). That is, it requires two or more microcycles from obtaining a macroinstruction to reading out a microinstruction, and thus lacks quick solubility.

On the other hand, as the models of microcomputers have improved from 4 bits to 98 bits, 16 bits, and 32 bits, their instruction sets have also been functionally enhanced. That is.

■The number of types of calculations increases.

■Instructions are added to improve system reliability.

■Instructions to facilitate debugging, etc. are added.

■Addressing that specifies operands increases.

Therefore, the instructions become more complex, and the instruction decoder that decodes them also becomes more complex and larger in scale.

One of the microprogram control methods that solves these problems is the direct mapping method, which uses the code of a macro instruction as an address in a microprogram memory. Related methods of this type include, for example, Japanese Patent Publication No. 5G-8011 or Japanese Patent Application Laid-Open No. 57-2031.
For example, Publication No. 41 may be mentioned.

Particularly in the latter case, the process from obtaining a microinstruction to obtaining the corresponding microinstruction can be realized in one microcycle, thereby realizing a microprogram control device with excellent quick solubility.

However, although microprogram storage devices employing the direct mapping method generally do not require an instruction decoder and are simpler to control, they have the disadvantage of increasing the memory capacity for storing microprograms. for example,
In Japanese Patent Publication No. 58-8'011, when reading out a series of microinstructions corresponding to a macroinstruction, a microprogram counter (hereinafter abbreviated as μPC) is used to sequentially read out a series of microinstructions, except for the first microinstruction. Therefore, even if there are microinstructions that perform common processing among several macroinstructions, these microinstructions cannot be shared by different macroinstructions, and there may be multiple microinstructions with the same processing content. Therefore, an increase in the capacity of microprogram memory is inevitable.

On the other hand, in Japanese Unexamined Patent Publication No. 57-203141, a page register is provided to store page information that can be divided into several pages, and this is used to branch to a common routine or return to the main routine while microprocessing is performed. Efforts are being made to standardize instructions. According to this method, when branching from the main routine to a common routine and returning to the main routine again after executing a series of common processes, the instruction code and page information of the macro instruction are used as the return address, so macro instructions with different instruction codes are processed. Even if the microinstructions to which the microinstructions return after executing different common routines have the same processing content, they cannot be made common. In other words, there are multiple microinstructions with the same processing content,
An increase in the capacity of microprogram memory is inevitable.

[Problem to be Solved by the Invention 3] As mentioned above, the above-mentioned prior art adopts the direct mapping method, ■ Eliminates the instruction decoder, and ■ Speeds up the time from obtaining a macro instruction to obtaining a micro instruction. Although this has been achieved, sufficient consideration has not been given to reducing the microprogram capacity, resulting in an increase in the capacity of the microprogram memory, which inevitably increases the cost of the microcomputer.

An object of the present invention is to provide a microprogram storage device that can reduce the capacity of a microprogram, reduce the memory capacity required to store the microprogram, and reduce costs when applied to an integrated circuit. be.

[Means for solving problems]

In order to achieve the above object, the present invention provides a means for specifying a branch address so that a microprogram with the same processing content can be called as a subroutine in a microprogram for executing a macro instruction, and further provides a means for specifying a branch address in a microprogram for executing a macro instruction. is configured with a means to specify a return address so that it can branch to a microprogram at an arbitrary address after execution is completed, and the microprogram for executing macro instructions can be shared between different macro instructions as necessary. is controlled.

[Effect]

According to the present invention, a microprogram for executing macro instructions can be commonly called and used as a subroutine among multiple macro instructions, so the capacity of the microprogram required for executing all macro instructions can be greatly reduced. The effect is that it can be reduced.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 13.

FIG. 1 shows one embodiment of the present invention.

■ An instruction storage section 10 that temporarily stores macro instructions read from the main memory in synchronization with a timing signal 10c given from a source other than the main memory; and ■ Indicates whether the instruction storage section 10 stores an instruction to be executed. According to the signal 10b and the output signal 14b of the microprogram memory 14, either the signal 10a or the signal 14a is selected as necessary, and the page information included in the signal 14b is combined with the selected signal. A first address generation circuit 11 that generates a branch address lla and generates a signal 11b indicating that the branch address lla is valid; ■ A return destination address when returning to the main routine after executing a microprogram subroutine; a second address generation circuit 12 that stores information necessary to generate the address 7 and generates a return destination address 12a upon return based on the stored contents and signals 24a, 14b, and 14c; Output 11 of generation circuit 11. a, or the output 12a of the second address generation circuit 12, as appropriate according to the signal 14b, and temporarily stores the selected one.
and (2) A microprogram memory 14 stores microprograms for executing macro instructions and sequentially stores microprograms in accordance with the output 13a of the microprogram address register 13.

Now, when a macro instruction is stored in the instruction storage section 10, the instruction code of the macro instruction becomes a signal 10a and is input to the first address generation circuit 1. At the same time, a signal 1 indicating whether or not an instruction to be executed is stored in the instruction storage unit 10. This is the first logic level indicating that Ob stores an instruction to be executed. In response to this, the first address generation unit 11 generates the page information specified by the signal 14b and the signal 1.
The microprogram address obtained by synthesizing the contents of 0a is output to the microprogram address register 13 as a signal 1],a. Further, a signal 11b indicating that a valid address exists in the signal 11a becomes active.

At this time, in the microprogram address register 13,
The 6 microprogram memory stores the signal 11a as a valid microprogram address and outputs the contents as the signal 13a to the microprogram memory 14, which outputs a microinstruction 14M specifying the first process according to the contents of the signal 13a. The second and subsequent microinstructions are read out according to the contents of the next addressing information 14a, 14b, and 14c included in the microinstruction 14M.

FIG. 2 shows the instruction format of a macro instruction read from the main memory (not shown) and stored in the instruction information section. The command format is roughly divided into the following three types.

(1) 0-address instructions (instructions that do not require an effective address specifier) Branch destination location (branch destination address) and operand (
Instructions that do not require an effective address specifier because the operation code implicitly includes means for specifying the storage location of operands (NOP, RTS) ,
BRA, TRAP instructions, etc. (2) 1-address instructions (instructions that require only one effective address specifier) Instructions that require only one branch destination location or operand storage location - JMP, NEG, CLR .

NOT, JSR instructions, etc. (3) Two-address instructions (instructions that require two effective address specifiers) There are two operands to be operated on, and two effective address specifiers are used to indicate the storage location of each operand. -A
DD, AND, MOV, B ITD.

5FTD, MULS instruction, etc. FIG. 3 shows an operation code table.

The operation code is constructed based on a byte (8 bits) unit, and FIG. 3 particularly shows the relationship between the operation code of the first byte and an instruction (expressed in a 21 monic).

An extended byte operation code for the second byte or higher is provided as necessary depending on the instruction, but it is omitted in FIG.

FIG. 4 shows the code and contents of the effective address specifier. The effective address specifier is configured based on byte units, and an extended byte effective address specifier is added as necessary. For example, in the register indirect addressing mode with scaling shown in Nα7, the displacement having the specified size (byte (8 bits, word (16 bits), long word (32 bits)) is expanded. The contents of each effective address specifier of the address instruction and the two-address instruction are all the same.

Here, the operation of the microprogram control method and apparatus of this embodiment will be explained in more detail by taking the ADD instruction (addition instruction), which is one of the macro instructions, as an example.

The ADD instruction is an instruction that adds two operands derived by two effective address specifiers (sometimes called operand specifiers) and stores the operation result in the storage location indicated by the second effective address specifier. . Now assume that the first effective address specifier indicates immediate byte addressing mode and the second effective address specifier indicates register indirect addressing mode. In this embodiment, the number of general-purpose registers is set to 16, and a code of 4 pins 1- is used as a register number to designate one of the general-purpose registers. Therefore, the instruction code of the ADD instruction is as shown in FIG.

That is, the ADD instruction in this case has an operation code of 1 byte, a first effective address specifier of 1 byte, and a first effective address specifier of 1 byte.
The immediate operand guided by the effective address specifier is 1 byte, the second effective address specifier is 1 byte, and the instruction code is composed of a total of 4 bytes.

In Figure 5, the 8-bit immediate value is (011
01101) 2, and the 4-bit register number is "
0101. ” (No. 5), the registers and memory model before executing the ADD instruction and the registers and memory model before executing the ADD instruction are as shown in Figure 6.
1, which is the operand specified by the effective address specifier of
With the byte immediate value (6D) ze as the first operand, the contents of register No. 5 (R5) specified by the second effective address specifier (00263111H2) t
The contents of the memory with address e (54) le as the second operand, and the result of adding both operands (C2) 1(l) is shown to be transferred to the memory at address zθ (002638E2) It is.

In order to execute this ADD instruction, the first operand (6D) 1B must be specified in the program, and the second operand (54) 1e must be specified (002638E2) in advance before the ADD instruction is executed. It is necessary to assign it to the memory at address 18.

FIG. 7 shows a microprogram for executing the ADD instruction, which stores microinstructions to be executed sequentially for each step.

The main contents are as follows.

1. ADD-B (1) Declare that the operand size is bytes.
) Increment the program counter (3) Declare that microinstruction A D 0.1 will be executed after returning from the subroutine, and set the code "0111000" in the first byte of page 1101 II and the first effective address specifier.
Call the subroutine to obtain the first operand using the code concatenated with "1" as the branch address 2, EADB (1) Increment the program counter (2) The first
Check whether it was called as a subroutine to obtain an operand. If the former, jump to EADB 13; if the latter, jump to IEADB 12, EADB 13. Transfer operand (8-bit immediate) to register DI3R (3) Unconditional jump to EADBII 4, EADBII (1) Sign extension of data stored in register DBR (2) Return to main routine (ADDI) 5, AD
I)L (1) Transfer the contents of register DBR (first operand) to register TRO (2) Set flip-flop TIF (3) Declare that microinstruction ADDll will be executed after returning from the subroutine, and page 1101 II and the code of the first byte of the second effective address specifier “00000101
6.Call the subroutine to obtain the second operand using the code concatenated with `` as the branch address6, EARI (1) General-purpose register R specified by the effective address specifier
Read the contents of the IS (this contents will be transferred to the DBR) (2) Increment the program counter 1 to (3) E
Unconditional jump to ARIOI 7.1': ARIOI (1) Transfer the contents of register DBR to registers DFP and TRI (2) Unconditional jump to EARX21 8, EARX21 (1) Memory where the second operand is stored (This content is transferred to DBR) (2) Declare that the destination to write is memory (not a register) (3) Return to main routine (ADDII) 9, A
DDll (1) Adds the contents of register DRR (second operand) and the contents of register TRO (first operand) and transfers the result to register DBW (2) Status (carry, sign) of the addition result.

Transfer (cello, overflow, etc.) to the condition code register (3) Unconditionally jump to WRITE, WRI T E (+) Write the contents of register DBW as the destination operand (in this case, if the destination is memory in HARX21) (2) Initialization of each flip-flop (3) Interrupt check (4) Page “o o” and the 8-bit code of the first byte of the operation code of the next instruction fetched into the instruction storage unit 10 (The code shown in Figure 3) is used as a branch address to unconditionally jump to the first microinstruction for instruction execution. Figure 8 shows the assignment of microinstructions to addresses in the microprogram memory 14. It is.

The physical address of the microprogram memory 14 is 10 bits, and the maximum capacity of the memory is 1024 words (one word is 45 bits). The upper two bits of the address are the page, and the page divides the 1024 word memory into four, so the memory is 256 words.
This is equivalent to having four pages of word memory. The method of specifying the lower 8 bits of the address differs from page to page, and is as follows.

(1) Method of specifying the address of the lower 8 bits of the "00" page: The code of the first byte of the operation code must be used directly.

(2) Method of specifying the address of the lower 8 bits of the "01" page: The code of the first byte of each of the first effective address specifier or the second effective address specifier is used.

(3) Method of specifying the address of the lower 8 bits of page "10" or 111111: A part (8 bits) of the contents of the branch control field specified by the microinstruction is used.

That is, taking the microinstructions for executing the ADD instruction shown in FIG. 7 as an example, the microinstructions implemented in each page are as shown in FIG. The usage of the 256 word memory area for each page is also classified as follows.

(1) Usage of the memory area of the "00" page En1-Re-microinstruction (microinstruction read first when executing a macroinstruction) storage area for macro instruction execution (2) Usage of the memory area of the 11Q1u page Effective address Microinstruction storage area for calculation subroutines (3) Usage of memory area of "10" or "11" page Work microinstruction storage area The microinstructions in this example consist of 1 word of 45 bits, and are mainly An operation control field (32 bits) that controls operations for executing macro instructions, and a branch control field (32 bits) that controls the address of the next micro instruction to be executed.
(13 bits).

FIG. 9 shows the microinstruction format, particularly the contents of the branch control field in detail.

This branch control field and the signals 14a and 14b in FIG.
, 24a are as shown in the figure. Branch control fields are broadly classified as follows.

(1) Jump: Unconditionally jumps to an arbitrary microinstruction with bits 9.8 as page information and bits 1-7-0 as the lower 8-bit address.

(2) RTN: This is a microinstruction that indicates the end of a subroutine.The contents of the microprogram address stack are used as the return address, and the lower two bits 1. O(
A-1, A-0).

(3) PC+1: Jump unconditionally to the microinstruction whose address is the value obtained by incrementing the contents of the microprogram address register.

(4) Ca1l: Calls a microinstruction at an arbitrary address in the work area. A value obtained by incrementing the address of the called microinstruction is stored in the microprogram address stack as the address of the microinstruction after returning.

(5) EA: Calls a microinstruction in the memory area of page "01" whose lower 8-bit address is the code of the first byte of the first effective address specifier. Bits 9 and 8 are used as page information, and bits 7 to 0 are stored in the microprogram address stack as the lower 8 pins 1-address so that it can be returned to the microinstruction at any address.

(6)○PJ: 1st. Unconditionally jumps to the microinstruction in the memory area of page "'o o" whose operation code is the lower 8-bit address.

(7) EAJ: Unconditionally jump to the microinstruction in the memory area of page II OI I+ whose lower 8-bit address is the code of the first byte of the first execution address specifier.

(8) EA\A; Calls the microinstruction in the memory area of page "01" whose lower 8-bit address is the code of the first byte of the second effective address specifier. Bits 9 and 8 are used as page information and bits 7 to 0 are used as a lower 8-bit address to be stored in the microprogram address stack so that it can be returned to the microinstruction at any address.

(9) EA-A: Calls a microinstruction in the memory area of page "01" whose lower 8-bit address is the code of the first byte of the second effective address specifier. The value obtained by incrementing the contents of the microprogram address register is stored in the microprogram stack as a return address.

FIG. 10 shows a second address generation circuit that provides a return address, and includes (1) a microprogram address stack 21 that temporarily stores a return address when a subroutine is called; and (2) the microprogram address stack 21. and (3) a multiplexer that appropriately selects either the signal L3b that updates the microprogram address register as the return address or the signal 14a specified by the field in microinstruction branch control. 26, (4) a flip-flop 23 controlled based on the signal 14c, (5) a multiplexer 24 that selects either the signal 24a or the signal 21a according to the output 23a of the flip-flop 23, and (6) the multiplexer. 24 output 24b and signal 21
It consists of a coupling circuit 25 for coupling b.

In FIG. 11, when returning from the subroutine to the main routine, the flip-flop 23 receives the signal 21a, which is the lower two bits of the return address stored in the microprogram address stack 21, and the microinstruction that specified the return to the main routine. It is controlled with a multiplexer 24 that selects one of the signals 24a that are part of the branch control field. That is, when the signal 23a is at the first logic level, the multiplexer 24 selects the signal 21a, and when the signal 23a is at the second logic level, the multiplexer 24 selects the signal 24a. Therefore, by specifying the flip-flop 23 at the second logic level in the main routine, branching to the subroutine, and then returning to the main routine, it is possible to return to microinstructions at four different addresses.

In this embodiment, the lower 8 pits 1 to 1 when making a subroutine call
Since the code of the effective address specifier of the macro instruction is used as the address, a maximum of 256 multi-branches are possible. Furthermore, by controlling the flip-flop 23 as necessary, the main routine to which the program returns after execution of the subroutine for calculating the effective address can be divided into several groups according to the effective address specifier.

FIG. 11 shows the effective address modes and instruction processing procedures allowed by the JMP instruction, which is one of the macro instructions. The return address specified in the main routine has the same value when calling all subroutines for effective address calculation, but when returning, part of the return address can be specified in the last microinstruction of the subroutine. As shown in the figure, if there is a mode that is not permitted as an effective address mode, it is possible to easily branch to another processing routine even if it becomes necessary to perform special processing as an undefined instruction (or an illegal instruction). be. Therefore, there is no need for a special instruction decoder for decoding undefined instructions.6 FIG. 12 shows the configuration of the microprogram memory 14. In this example, read-only memory (
ROM) is shown.

FIG. 13 shows a timing chart of each signal of the microprogram memory 14.

It can be seen that one microcycle (equivalent to one cycle of the basic clock) is required from the time the microprogram address 13a is obtained until the microinstruction 14M is output.

〔Effect of the invention〕

As described above, according to the present invention, a microprogram for executing a macro instruction can be commonly called and used as a subroutine among multiple macro instructions. capacity can be significantly reduced.

[Brief explanation of drawings]

Figure 1 shows the microprogram storage device, Figure 2 shows the format of the macro instruction, Figure 3 shows the operation code of the macro instruction, and Figure 4 shows the addressing mode and contents of the effective address specifier. Figures 5 to 7 are diagrams explaining the processing contents of the ADD instruction, Figure 8 is a diagram showing the usage of each area of microprogram memory, and Figure 9 is a diagram showing the microinstruction format. 10 is a diagram showing details of the second address generation circuit, FIG. 11 is a diagram showing an example of the JMP instruction, FIG. 12 is a diagram showing the configuration of the microprogram memory, and FIG. 13 is a diagram showing the microprogram memory. The figure which shows the operation timing chart of. DESCRIPTION OF SYMBOLS 11...First address generation circuit, 12...Second address generation circuit, 21...Microprogram address stack, 13...Microprogram address 1
Kunimori 2 Sen (1) θ Atoshisu Reiigata 2 no (Z) 17 do Umata 4 Shinryo 2 no (3) Muadre Suki Ya Yu 4th (Yuno No. 4 'J C1-) 4th (C ) 5th (2) 4-32 Bi-Jiugin 4-3 Pit-Satoru (0
Illustration procedure amendment (voluntary)

Claims (1)

[Scope of Claims] 1. In a computer system that additionally includes a main memory for storing instructions and operands, when a microprogram address for branching to a microprogram subroutine is given, it is possible to branch to the microprogram subroutine. A microprogram control device comprising: a. an instruction storage section for storing instructions read from the main memory; and b. storing a microprogram including a microinstruction for branching a microprogram main routine to a microprogram subroutine. c. a microprogram address register connectable to the microprogram storage means and temporarily storing an address indicating a storage location of a microinstruction stored in the microprogram storage means; d. a first means connectable to the microprogram storage means and the instruction storage section for providing a branch address for branching to a microprogram subroutine to a microprogram address register; e. the microprogram storage means and the microprogram; a second means connectable to an address register for providing a return address indicating a storage location of a microinstruction of a main routine to be returned from the microprogram subroutine; the first means for providing a branch address; the second means for appropriately switching and selecting one of the content and the content of the address field of the microinstruction for branching to the subroutine according to the microinstruction as an address to be provided to the microprogram address register, and providing a return address; So,
information necessary to generate a return address for returning from the subroutine to the main routine the contents of an address field having a microinstruction to branch to the subroutine when the contents of the instruction storage section are selected by the first means; 1. A microprogram control method, characterized in that the information is temporarily stored as a subroutine, and when a microinstruction indicating the end of a subroutine is given, control is performed so as to return to the main routine according to the temporarily stored information.