JPS6265143A - Fault signal generating system - Google Patents

Abstract

PURPOSE:To attain the effective diagnosis, check, etc. of a fault of a logical device by writing a prescribed data to a RAM and producing a fault signal after receiving a fault allocating request or the actual fault generation state of a logic circuit. CONSTITUTION:A service processor 1 delivers a fault signal allocating request and an interruption address is delivered to the head address A of a program of a ROM 16 designated under the control of an interruption control circuit 10. Thus the prescribed n-bit address of a RAM 23 is replaced and the fault generation data is written. Then a fault generation state is set when an instruction is executed to give an access to the address storing the fault generating signal. Thus the fault is processed by a program stored in the ROM 16. When an error actually occurs within a logic circuit, the fault is designated from a fault display register 25. An interruption address is designated under the control of the circuit 10 that received said fault designation. Thus the head address B is designated with the fault processing of the ROM 16. Then a fault processing program is executed by the RAM 23.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a fault signal generation method, and is aimed at efficiently generating fault signals necessary for diagnosing and inspecting faults in logic devices operated under the 4I microprogramming method. This paper relates to a fault signal generation method. [Prior Art] Conventionally, diagnosis or testing of logical devices has been limited to the range that can be tested by normal programs, that is, adding artificial fixed faults to nodeware, or exceptional processing or processing of non-standard data prepared programmatically. The content is limited to evaluation processing for the functions that have been provided. [Problems to be Solved by the Invention] However, as described above, the processing content of conventional fault signal generation methods of this type is extremely limited and standard, and therefore it is difficult to evaluate asynchronous faults in logic devices. The drawback is that it takes a lot of man-hours and can only be implemented in a limited number of cases.
Another object of the present invention is to provide a fault signal generation method that can evaluate faults in many examples while eliminating the above-mentioned drawbacks and greatly reducing the number of man-hours. [Means for Solving the Problems] The method of the present invention is a fault signal generation method for generating fault signals for diagnosing and inspecting faults in logic devices operated under a microprogramming method. RAM (Random Acc
ess Memory) and a fault detection circuit that outputs a fault occurrence signal based on an actual fault in the logic device, an interrupt operation for the microsequence circuit of the logic device is activated. The interrupt control means interrupts operation instructions of microinstructions to be executed under the control of an interrupt control means and a program RAM that stores information specified in the RAM based on instructions from outside the microcoupled circuit. and a fault signal generating means for generating a fault signal during the read operation. [Example] Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The configuration of the embodiment shown in FIG. 1 is as follows: service processor 11 interrupt control circuit 10. Incrementer】1゜Address register 12. Address stack 13° adder 14. -rrutip L//su15. ROM (Read Only Me
mory)16. RAM17. -j Lunaplexa 18
．． Instruction register】9. Data register 20° decoder 2
1. Multiplexer 22. RAM23°OR circuit 24.
Fault display register 25. Fault detection circuit 26. The circuit includes an arithmetic circuit 30, of which a portion from interrupt control circuit 0 to decoder 21 shown by a dashed line constitutes a microsequence circuit. The operation sequence of the microsequence circuit is controlled by the microprogram, and the arithmetic circuit 30 is connected to the data bus 100. Addresses and data are transferred via the address bus 200 to achieve a predetermined operational purpose. The ROM 16 stores a microprogram to store information specified in the RAM 17 as well as RA 23 (to be described later) according to instructions from the outside, a diagnostic microprogram, and a microprogram for controlling the microsequence circuit. This is memory for storing data. The outputs of these ROM 16 and RAM 17 are supplied to a multiplexer 18. RAM] 7 also transfers data to and from the arithmetic circuit 30 via the human power line 171 and the data bus 100. The multiplexer 18 selectively outputs either the output of the ROM 16 or the RAM 17 in response to the selected output of the multiplexer 15 received via the input line 181, and supplies it to either the instruction register 19 or the data register 20. The output of the command register 19 is supplied to a decoder 21, decoded, and supplied as a command signal to each part of the microsequence circuit, and the output of the data register is supplied to the arithmetic circuit 30 via the data bus 100. Now, each time a microprogram instruction is processed under the control of the ROM 16, the instruction code is converted to the starting address of the microroutine that processes it, and the address number is incremented by one via the incrementer 11, and then the next address is transferred. is supplied to the address register 12 while specifying the address. When the instruction code is based on normal sequential execution, the address register 12 sends it to the multiplexer 15 as a normal instruction address. Also, the instruction code may be a jump instruction due to subroutine execution, etc.

[7〈 is for interrupt processing, K is the corresponding jump, the address of the normal instruction being executed is temporarily saved in the address stack 13 in order until the interrupt processing is completed, the return address to be returned to is secured by the return command, and the output is returned. It is supplied to multiplexer 15 as an address. When a jump instruction is issued from the instruction register 19, in the case of a direct jump, the address is directly sent to the multiplexer 15, and in the case of a conditional jump, a ± operation is performed by the adder 14 to determine the address to be changed depending on the condition. , an address number obtained by performing ten operations on the normal instruction address supplied from the address register 12 is supplied to the multiplexer 15. The multiplexer 18 is also provided with an update address corresponding to an address update instruction generated in conjunction with the execution of a microinstruction via the address bus 200, and one of these various addresses is selected in response to the microinstruction and is then sent to the ROM 16. Or input/output line 15 to RAM 17
Provided via 1. Normally, diagnosis or inspection of a logic device operating in this way involves detecting fixed faults in the hardware that makes up the microsequence circuit, exception handling for non-standard data prepared programmatically, or As mentioned above, this method is limited to a limited range of things that can be inspected by a program, such as processing for certain functions, and has the disadvantage that automatic processing is basically difficult, and the number of failure cases that need to be handled is also limited. As I said. Therefore, in this embodiment, this problem is solved as follows. A plurality of predetermined addresses are secured in the RAM 23 for writing fault signal generation data as predetermined binary information for generating a fault signal. Failure occurrence data received from the main memory etc. is written. This write processing program is stored in the ROM 16, and as will be described later, the write processing of the FROM 16 is activated under the control of a write command microprogram internal to the service processor 1, and writing to the RAM 23 is executed in accordance with the microinstruction. In addition to the above-mentioned microinstruction code, the multiplexer 22 is also provided with an update address for updating a plurality of addresses reserved in the RAM 23 via the memory address bus. As mentioned above, the microprogram for writing failure data into the designated area of the RAM 23 is built into the ROM 16, and by specifying the start address of this microprogram and starting it, writing is executed by the service processor's write command microprogram. executed by Nervous process again? 11 RAM23 like this
On the other hand, a microprogram for writing predetermined fault occurrence data to a predetermined address from outside the logic device is built in, and a fault signal is generated by interrupt processing while the logic device is executing the microprogram. In this way, the RAM 23 is used as a RAM exclusively for faulty data, and a fault occurrence signal indicating that a fault has occurred is output to the OR circuit 24 each time the address where the faulty data is written is read. This fault occurrence signal is based on an artificial fault based on the fault occurrence data written to the RAM 23. Now, the fault detection circuit 26 outputs a fault occurrence signal and supplies it to the OR circuit 24 each time it receives an error signal sent based on an actual fault occurring at a predetermined detection site within the logic device. In this way, when the OR circuit 24 receives at least one of the two fault occurrence signals, a fault occurrence signal based on an actual fault and a fault occurrence signal based on an artificial fault, it outputs either of the fault occurrence signals as an OR output signal 7. , and outputs this to the fault display register 25. When the fault display register 25 receives the output of the OR circuit 24, it temporarily stores it, reads it out, and supplies it to the data bus 100 and the interrupt control circuit 10 as a fault display command. The fault display command supplied to the data bus 100K is provided to the arithmetic circuit 30, and the fault display command supplied to the interrupt control circuit 10 causes the microsequence circuit to start an interrupt operation. Interrupt control circuit O receives commands, interrupts in the execution of microinstructions, and fault display commands, controls the execution sequence of these commands, and generates interrupt addresses for the microsequence circuit. Different interrupt addresses are set for each input to the interrupt control circuit 10, and different addresses in the ROM 16 are designated, and these designated addresses become the starting addresses of the respective interrupt programs. The generation of the interrupt address will be explained in more detail as follows. The service processor 1 self-recommends a microprogram for issuing a command to write fault occurrence data in a predetermined format in a predetermined area of the RAM 23, as well as a microprogram for diagnosing the response function when a fault occurs in the logical device. The service-dedicated processor supplies the interrupt control circuit 10 with a fault signal generation command for generating a fault signal to artificially put the inside of the logic device into a fault state as desired. By the way, the following two basic processes are taken in response to the occurrence of a failure. The first process is to artificially create a failure state, in which the service processor 1 issues a failure signal planting request in advance, and under the control of the interrupt control circuit 10, the specified ROM 16 is sent via the multiplexer 15. Outputs the interrupt address for interrupting address A. This personal address is the starting address of a program for writing specified fault occurrence data to a specified address in the RAM 23. When this program is started, the specified address in the RAM 23 is updated and the specified data is written. Information regarding these addresses and data is normally read from a mailbox or the like in the main memory via a pass line. For this purpose, a predetermined n bits are secured at a plurality of predetermined addresses in the RAM 23, which is updated under the control of the write processing program in the ROM 16, and the above-mentioned fault occurrence data is written therein. Thereafter, when an instruction to access the address where the fault signal is stored is executed, the fault occurs and the fault processing program built into the ROM 16 is run to execute predetermined fault processing. The second step is processing to be performed when an error actually occurs within the logical device. In this case, as will be described later, a fault display command is issued from the fault display register 25, and under the control of the trap control circuit 10 that receives this command, an interrupt address B different from the above entry is specified, and the interrupt address B of the ROM 16 is Interrupt the address. Address B is the starting address of the program that activates the fault handling that should be performed when an error occurs).
By specifying this, the fault handling program runs and predetermined processing is performed. Furthermore, trap control is performed so that interrupt addresses specifying different addresses are output in response to command and interrupt inputs, and these interrupt addresses cause an interrupt to be placed at a specified address in the ROM 16 and a predetermined control microprogram is activated. Ru. In this way, predetermined fault occurrence data is written into the n-bit area secured by the RAM 23 by an external command from the service processor IK, and the written data is processed by executing an interrupt command to access this data. A fault signal is generated and processed, and the results are reported to the service processor 1. The service processor 1 performs judgment processing on the data thus reported. In this way, the occurrence of a fault signal and the processing corresponding to the fault signal are automatically and efficiently performed, and after the interrupt processing is completed, the return address is returned to the address stack 13 and the normal instruction routine is resumed. . [Effects of the Invention] As explained above, according to the present invention, fault processing is carried out by providing a means for generating a fault signal by writing predetermined data into a RAM provided for fault signal generation according to an external instruction. By doing so, it is possible to realize a fault signal generation method that can automatically process the evaluation of asynchronous faults in a logical device and can be implemented for a large number of cases with a significant reduction in man-hours.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Service processor, 10...
Interrupt control circuit, 11...Incrementer, 1
2...Address register, 13...Address stack, 14...Adder, 15...
...Multiplexer, 16...ROM, 17
...RAM, 18...Multiplexer, ]9...Instruction register, 20...Data register, 21...Decoder, 22...・
...Multiplexer, 23...RAM, 24
...OR circuit, 25...fault display register, 26...fault detection circuit, 30...
...Arithmetic circuit. Agent Patent Attorney Susumu Uchihara''-Kumi, -1

Claims (1)

[Claims] A RAM that outputs a fault occurrence signal based on an artificial fault accessed by a microinstruction in a fault signal generation method that generates a fault signal for diagnosing and inspecting a fault in a logic device operated under a microprogramming method. (Random Access Memo
ry) and a fault detection circuit that outputs a fault occurrence signal based on an actual fault in the logic device, which causes an interrupt operation to be activated for the microsequence circuit of the logic device when the output is obtained. the RA based on a control means and an instruction from outside the microsequence circuit;
fault signal generating means for generating a fault signal by instructing the operation of a microinstruction to be executed under the control of a program storing information designated by M at the time of an interrupt operation by the interrupt control means; A fault signal generation method characterized by: