JPS6320635A - Trouble signal generating system - Google Patents

Abstract

PURPOSE:To automatically evaluate countermeasure operation of the trouble of a logical device with a considerably reduced man-hour reading out a trouble signal, which is preliminarily set and stored, during execution of a microprogram to bring about the state where trouble occurs. CONSTITUTION:In case of artificial setting of the trouble occurrence state, a request with a trouble signal value is preliminarily issued from a service processor 50, and a designated address a of a ROM 1 is interrupted through a multiplexer 7 by the control of a trap control circuit 12. When this program is started, designate data is written in a designated address of a RAM 2. Information related to these addresses and data is read out by the started program, and the designated address of the RAM 2 is supplied through an address bus 200 and write data is supplied through a data bus 100 to update contents of the RAM 2. If the program in the ROM 1 in the same address as the address where trouble occurrence data of the RAM 2 is stored is executed, the trouble occurrence state is set.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a fault signal generation method, and in particular to a method for diagnosing and inspecting faults in a logic device operated under control of a microprogram in a microprogramming method. This invention relates to a fault signal generation method for generating fault signals necessary for

[Conventional technology]

Conventionally, diagnosis or testing of logical devices has been limited to the range that can be tested by a normal program, such as whether or not there are artificial fixed faults in the hardware, exceptional processing for non-standard data prepared programmatically, or evaluation processing for specified functions. The content was limited to topics such as:

[Problem that the invention seeks to solve]

However, the processing content of conventional fault signal generation methods is extremely limited and fixed as described above, so it takes a lot of effort to evaluate asynchronous faults in logic devices. The drawback is that it can only be implemented in a limited number of cases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a fault signal generation method that eliminates the above-mentioned drawbacks and can evaluate faults in a large number of cases while significantly reducing the number of man-hours.

[Means for solving problems]

The fault signal generation method of the present invention is a fault signal generation method that generates a fault signal for diagnosing and inspecting a fault in a logic device that operates according to a microprogramming method. means for writing an arbitrary fault signal to a designated address of the memory according to an external instruction; and means for determining that a fault has occurred in the logic device when the arbitrary fault signal is read out at the same time as the microprogram is read. It is realized by having means.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a fault signal generation method according to the present invention. In the same figure, the fault signal generation method is ROM (Read Only Memory) 1
, RAM (Random Access Memory)
y) 2, incremental 3, address register 4, star.

memory 5, adder 6, multiplexer 7, instruction register 9, data register 10, decoders 11 and 13,
The configuration includes a trap control circuit 12, a fault display register 14, an arithmetic circuit 16, and a service processor 50, and further includes a data bus 100 and an address bus 200.
have.

A ROM 1, which stores a control microprogram for controlling the operation of each node forming the logic device, supplies read microinstructions to an instruction register 9. Further, the RAM 2 which stores the failure data read out along with 80Δ11 supplies it to the data register 10 and the decoder 13.

The instruction data input to the instruction register 9 is read out and decoded by the decoder 11, and then sent as a command to the stack memory 5, multiplexer 7, trap control circuit 12, arithmetic circuit 16, and other necessary 7.-
is supplied to software to control their respective operations.

The data read into the data register 10 is transferred to the data bus 1.
The signal is supplied to the arithmetic circuit 16 via 00 and used for predetermined logical operations, etc.

Arithmetic circuit 16 supplies the RAM 20 update address to multiplexer 7 via input line 701, and multiplexer 7 sends it to ROM 1 and RAM 2 based on the command to address RAM 2 when updating.

In addition to the update address mentioned above, the multiplexer 7 inputs the normal instruction address from the near address register 4, and the stack memory 5.
to the return address, and from the instruction register 9 via the input line 901 to the direct jump address in jump processing necessary for executing the microprogram, and further to the adder 6.
each receives a conditional jump address via the .

The conditional jump address is input to the adder 6, and the adder 6 performs an address change operation on the normal instruction address received from the address register 4 according to the contents specified by the condition, and sends the address to the input line 702. .

The normal instruction address, return address, direct jump address, and conditional jump address mentioned above are selected by the command.

Furthermore, the interrupt (trap) address is input to the multiplexer 7 via an input line 703 to the trap control circuit 12.
and is selectively output according to an interrupt command received from the same trap control circuit 12 via input line 704. A different interrupt address is output for each input to the trap control circuit 12.

In this way, various inputs are supplied to the multiplexer 7,
Either one under the control of a command or an interrupt command.
is selected and supplied to ROM1, RAM2, or incremental 3.

The normal operation of the logic device operates under the control of various microprograms stored in ROM 1. In this case, the first address of the microprogram routine is incremental 3.
is supplied to the address register 4, and the address is incremented one by one to specify the next address. These are normally supplied to the multiplexer 7 as addresses, and the next microinstruction address is ROM1, R, AM2 in the order of execution.
It will be provided to Further, the output of the address register 4 is output to the adder 6, and is used for an address change operation to ± specified by another input (conditional jump address) of the adder 6.

In this way, when a jump instruction or an interrupt command is input through the output line 101t while a normal instruction is being executed, the addresses of the normal instructions being executed are temporarily saved and stored in the stack memory 5, and the jump or interrupt program is executed. After processing, a return address to be returned to is secured by a return command, and RObll or 几A is sent via multiplexer 7.
M2K provided.

The above-mentioned jump command is intended for a prespecified command such as a subroutine, but the interrupt command is supplied from the trap control circuit 12. In other words, a fault signal generation command is output from the outside via the service processor 50 for diagnosing or inspecting the fault response function of the logic device, and is issued in response to an actual error occurring in the logic device, including this artificial fault. Different interrupt addresses corresponding to fault display commands or various related commands are output by interrupt commands.

The service processor 50 has a built-in microprogram for issuing a command to write fault data in a predetermined format in a predetermined area of FtANiz, as well as a microprogram for diagnosing the response function when a fault occurs in the logical device. It is a processor dedicated to the service of providing fault signal generation commands to the full trap control circuit 12, which generates all the Ia damage multiplier signals to artificially put the inside of the logic device into a fault state as desired.

Two basic actions are taken when a failure occurs:

The first process is to artificially create a failure state, in which the service processor 50 issues a failure signal planting request in advance, and under the control of the trap control circuit 12:?
An interrupt is applied to the designated address A of ROM1 via the luteplexer 7. This person@address that outputs the interrupt address indicates the starting address of the program for writing specified fault data to the specified address of RAM2. When this program is started, specified data is written to a specified address in RAM2. Information regarding these addresses and data is normally stored in a mailbox or the like of the main memory and is read by the activated program, and the designated address of RAM 2 is sent via the address bus 200, and the write data is sent via the data bus 100. AM2 is updated using the respective signals supplied through the AM2. In this way R
After R, A hi 2 is updated by the program in OMx, when the program in ROAi I at the same address as the address where the fault data in RAM 2 is stored is executed, a fault occurs.

The second step is processing to be performed when an error actually occurs within the logical device. In this case, as will be described later, a fault indication command is output from the fault display register 14, and under the control of the trap control circuit 12 that receives this command, an interrupt address B different from the above A is specified, and the interrupt address B of ROM 1 is specified. Interrupt @ ground. Address B is the starting address of the fault handling program to be executed when an error occurs, and by specifying this address, the fault handling program is executed and predetermined processing is performed.

Note that another interrupt address is specified for the command, and thus the trap control circuit 12 outputs a different address depending on the input conditions as described above.

A fault display command inputted to the trap control circuit 12 from the fault display register 14 is generated as follows. The output of the FiOR circuit 15 is supplied to the fault display register 14, but one of the two outputs of the OR circuit 15 is an error, and an error detection device (not shown) or the like is used to detect the fault that actually occurs in the logic device. If it is possible to obtain the bit width, the decoder 13 may be omitted.

As mentioned above, (RAM2) is a memory for writing failure occurrence data for artificially generating a failure signal under the control of the program in TOKIL.
Input of data No. 2 means that a fault signal is artificially generated. Therefore, even if a failure occurs due to actual or artificial causes, the failure indication register 1
4 provides the e-harm display command to the trap control circuit 12.

When a fault signal planting command is issued by a microprogram prepared in the service processor 50, an interrupt command is issued from the trap control circuit 12, and an interrupt address is provided to the ROM1. This interrupt address interrupts the microprogram being executed, and l(A
A microprogram that stores designated data at the designated address of M2 is executed, and the fault occurrence data is written to RAM2. When the update of RAM 2 is completed, the microprogram currently being executed is returned to. After that, when the microprogram in 80M1 at the same address as RAM2 where the fault occurrence data is stored is executed, the fault data written in RAM2 is stored in the fault display register 14 and the fault display command is used for trap control. provided to circuit 12; Then, the interrupt address is set to RO by the trapped 1j control circuit 12.
The error processing program is provided to M1, and as described above, an interrupt is applied to the microprogram being executed, and execution of the fault handling program is started. The processing results of the fault handling program are reported to the service processor 50 (not shown). The service processor 50Fi performs judgment processing on the data reported in this way, and thus diagnosis and inspection of failure occurrence can be carried out automatically and efficiently.

The above-mentioned evaluation of the occurrence of a failure in the logical device can be made highly flexible by considering the configuration of the microprogram prepared in the service process, and can be performed in many cases while significantly reducing man-hours. It is possible to automatically carry out evaluations targeting

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to read out a previously set and stored fault signal during the execution of a microprogram to determine the state in which a fault has occurred, thereby evaluating the fault response operation of a logic device. This has the effect of being able to carry out the process automatically and with a significant reduction in man-hours.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1...ROM, 2...RAM, 3...
...Incrementer, 4...Address register, 5...Stack memory, 6...
Adder, 7... Multiplexer, 9...
・Instruction register, 1o...Data register, 1
1.13... Decoder, 12... Trap control circuit, 14°°°゛°° fault display register,
15...OR circuit, 16...arithmetic circuit, 100...data bus, 200...
address bus. -8 Agent Patent Attorney Uchihara Hi 3. /),. 1.

Claims (1)

[Claims] A fault signal generation method for generating a fault signal for diagnosing and inspecting a fault in a logic device operated by a microprogramming method comprises: a memory that can be randomly accessed at the same time as a storage section storing a microprogram; means for writing an arbitrary fault signal to a specified address in the memory according to instructions from the memory;
A fault signal generation method characterized by comprising means for determining that a fault has occurred in the logic device when the arbitrary fault signal is read at the same time as the microprogram is read.