JPS5952444B2 - Sequence control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control device, and particularly to a sequence control device that can be programmed using a sequence circuit diagram image.

Sequence control is a method in which relay elements are combined to form a relay circuit, and this relay circuit is made to make logical decisions and to perform sequential and repetitive operations as a whole.

Early sequence control had a hard-wired configuration, but in recent years, with the development of electronic technology, the trend has been to use logical calculations to perform logical judgments that were conventionally processed by relay circuits. The mainstream of this logical calculation is digital processing, especially computer programmable methods. It is also called a programmable logic controller (PLC). The feature of this processing is that the control program can be expressed in a simple manner using command words, so that various sequence controls can be easily performed. Let us explain the relay sequence by such a PLC.

FIG. 1 is a diagram showing an example of a relay sequence. In the figure, A, B, C, D, E, and F indicate input contacts obtained from the process system. G and H indicate output relays. Such a relay sequence can be expressed in Boolean algebra as follows. G=(A+C)・B=A-B+C-B・・・・
・・・・・・(1) H=D−E+F・・・・・・・・・(2
) has a function equivalent to the above relay sequence,
A block diagram of an early digital logic circuit type PLC is shown in FIG.

In the figure, A, B, C...... are input contacts from the outside, and the input contacts A, B, C...... - Select two required input contacts and transmit the state of the input contacts to the calculation unit 10.
The calculation unit 10 performs predetermined sequence calculations. Output section 2
maintains the required output relays G and H in the on or off state according to the calculation result of the calculation section 10. The main storage section 4 stores a sequence program, which is sequentially read out and sent to the arithmetic section 10 for use in the sequence arithmetic operation. Here, a conventional example of the above calculation section is shown in FIG. In the figure, calculation unit] 0 is the OR gate 100,
ANDGATE 101. Working S tab lip flop 102 (abbreviated as WKFF), accumulator 103 (A
(abbreviated as Cc). Both WKFF and Acc have a 1-bit configuration. In the above configuration, its operation is described above (
1) Taking G shown in equation 1 as an example, it is as follows. Here, 1, 2, and 3 indicate the timing order of calculations.

That is, when the first sequence command LOADA is read out from the main memory 4 where the sequence program is stored, this command is interpreted, the state of the input contact is stored in Acc]03, and then it is read out in binary form. The symbol “O” is W
Stored in KFFlO2.

Next, when the second sequence command ANDB is read, the logical product (A
ND) is stored in register ACClO3. Next, by the third sequence command 0RC, the contents of ACclO3 and the logical sum (0R) of WKFFlO2 are converted to WKF
Stored in FlO2. Next, the state of input contact C is Acc.
Stored in lO3. Next, the fourth ANDD instruction performs the same operation as the second instruction. Then the 5th SE
The contents of register AcclO3 and WKF are executed by the instruction TG.
The logical sum (0R) of the contents of FlO2 is stored in WKFFlO2. After a further delay, the contents of WKFFlO2 are output to output relay G via output section 2. As above 1
Boolean algebraic expression A by sequence instruction from address to address 5
- Execute B+C-B=G.

A similar procedure can be used to convert Boolean algebra expressed by polynomials of AND and OR into sequential sequence instructions. Sequence commands are sequentially read out from the main memory 4 where the sequence program is stored and executed repeatedly at high speed, so the sequence control processing device shown in FIG. 2 has the same function as the relay sequence shown in FIG. accomplish By the way, in this early PLC, it was quite difficult to create a sequence control program.

In order to create a sequence program, it was necessary to understand and code the difficult PLC machine instructions. As a first step to solve this problem, the PL
It was thought that the final PLC control program could be created by coding a C program in mnemonic notation equivalent to AND and 0R assembler language, and running this on a separately installed computer. A method of creating programs using man-machine communication using a CRT display (TV display) and a keyboard has become popular. Also, if you enter a symbol corresponding to a relay circuit diagram from the keyboard, the corresponding relay circuit diagram will be displayed in C
This is a method in which the information is displayed on the RT display. This method is considered to be the most desirable method because the programmer can program without being aware of the PLC's machine language at all. Even in a PLC that performs PLC programming of the CRT man-machine communication type, the command words of the conventional processing device are in the form of Boolean algebra.

However, when trying to process using the image of a relay circuit diagram, there are various problems with Boolean algebra-type command words. For example, input contacts A, B, C, D, E, as shown in FIG.
The combination of F and G circuits cannot be completely expressed using Boolean algebraic expressions. Not only that, but there is no clear one-to-one correspondence between the circuit diagram and the Boolean algebra operation symbols. To explain using an example, although the dotted line parts in FIG. That is, the logical symbol after F is ゜")" in the illustration, and "゜))" in the illustration. Since programmers are processing these complex symbol associations in their heads, it is necessary to educate them on how to perform functional programming operations. The following PLC was developed as a second PLC to solve these difficulties.
There is LC. In FIG. 6, the same reference numerals as those in FIG. 2 indicate the same or corresponding parts, so the explanation will be omitted. Storage device 5
is newly added. This is a relay point that is connected to a branch point such as an input contact or an output relay relay contact in a sequence diagram, and the on/off state of this relay point and other relays that are passed through to turn on the relay point. It stores the level according to the number of points. FIG. 7 is a block diagram showing an example of the configuration of the arithmetic circuit 10 shown in FIG. 6, and the same reference numerals in FIG. 7 as in FIG. LRl, LR2, LR3
is a level register for indicating the level of the relay point, C
OMPl is a comparator that compares two levels and outputs the larger one; COMP2 is a comparator that compares two levels and outputs the smaller one; COM
P3 is a comparison adder that compares two levels, adds 1 to the smaller one and outputs the result, and the arrow indicates a level information gate. MAX represents the maximum number that can be stored in the level register LR3, and actually represents the maximum level value. The operation of the above configuration will now be explained using the sequence diagram shown in FIG.

In the relay sequence diagram shown in Fig. 8, input contacts X1 to X6 and ゛, relay coil y1 of the output relay
The branch points connected to each other at ~Y2 are designated as relay points P1 to P4, and the relay sequence is written in Boolean algebra as follows. P1=X1+X2.

P2+X3-P3 number l8l8O (3P2:X2+P2+
X6+P4″″-″-03 (4P3:X4+X3+Pl
+X5″P4l″−″−0″(5P4:X6+P2+X
5+P3″″1゜0゛00I (6Y1=P2...
......(7Y2=P4......(8) The on/off states of these relay points P1 to P4 can be stored in the storage device 5 in FIG. 6, making them equivalent to the input contacts. can be handled.

However, if only the ON and OFF states of the relay points P1 to P4 are stored, for example, input contact Considering the case where the relay point P1 turns off, relay point P1 turns on due to the conditions of X3 and P3, while relay point P3 turns off
It remains on under the condition of 3.P1, and the off state cannot be shown in the actual relay sequence diagram. Therefore, levels are set for the relay points P1 to P4, and initially the level is increased by one each time the relay passes through one relay point, and it is stipulated that a relay point with a higher level cannot be turned on to a relay point with a lower level. In this way, in the above example, when input contact X1 is on, offshore junction P1 is on (level 1), input contact X3 is on, relay point P3 is on (level 2), and then input contact X1 is turned off. Since the condition of X3 and P3 is level 2 at the relay point P1 (level 1), P1 is turned off, and therefore the relay point P3 is also turned off, so that correspondence can be established with the actual sequence diagram. A specific example of the above operation is the Boolean algebraic expression (3) above, that is, P1=X1+P2・X2+P3・
Taking X3 as an example, it is as follows.

Here, 123 indicates the timing order of calculations, and the levels of the input contacts Xl, X2, . . . are always "0".

In other words, the sequence command LOADxl at address 1 is
When read from the memory in the sequence program unit 4, this command is interpreted and the state of the input contact X1 is captured and stored in AcclO3.

Also, the binary code “0” is WKFFlO. 2 is stored. On the other hand, the level O of the contact X1 is stored in the level register LR1, and then transferred to and stored in the level register LR2. Further, the maximum value MAX is set in the level register LR3. Next, when the sequence command 0RX2 at address 2 is read from the memory in the sequence z program section 4, the value of Acc flip-flop and WKF
The logical sum of F is taken by the 0R gate 100 and the result is stored in WKFF again. Then, the state of the input contact X
2 is fetched and stored in Acc. One input contact
A level O of 1 is stored in the level register LRl. A
When cc is on and the level of level register LR2 is lower than the level of level register LR3, the contents of level register LR2 are output from comparator COMP2 and stored in level register LR3. The contents of level register LR1 are then transferred to level register LR2. Next, when the sequence command ANDP2 at address 3 is interpreted, the state of relay point P2 is read from the storage device 5, and the AND gate 101 performs a logical product with Acc, and the result is stored in Acc again. be done. On the other hand, storage device 5
The level of relay point P2 stored in is stored in level register LRl, and the level of level register LRl is
When greater than level register LR2, comparator COMP
The contents of level register LR1 are output from level register LR1 and stored in level register LR2. Next, the sequence command 0RX3 at address 4 is interpreted, and the contents of Acc and WKF
The logical sum of F is taken and stored in WKFF. The state of input contact X3 is then transferred to Acc. One input contact
Level 0 of 3 is stored in level register LRl, and Ac
When c is on and the level of level register LR2 is smaller than level register LR3, comparator COMP
2, the contents of level register LR2 are output and transferred to level register LR3. Next, level register L
The contents of Rl are transferred to LR3. Next, the 5th 1st AN
The state of the relay point P3 is read from the storage device 5 by the sequence command DP3, and the logical product with Acc is ANDed.
It is taken at gate 101 and stored in Acc. On the other hand, the level of relay point P3 stored in storage device 5 is read out and stored in level register LRl. When the level of level register LRl is higher than level register LR2, the contents of level register LRl are set to level register LR.
Transferred to 2. Next, by the sequence command SETPl at address 6, the logical sum of the Acc value and WKFF is WK
Transferred to FF. On the other hand, when Acc is on and the level of level register LR2 is lower than level register LR3, comparator COMP2 outputs signal from level register LR.
The contents of 2 are output and recorded in the level register LR3. Next, the level of the relay point P1 is read from the storage device 5.
This level is compared with the level of the level register LR3 in the level register COMP3, and when the level of the relay point P1 is greater than or equal to the level of the level register LR3, the contents of WKFF are changed to P of the storage device 5.
1 storage unit. Furthermore, when the level of the relay point P1 is lower than the level register LR3, the P1 storage section stores 2 bits.
The decimal code "0" is stored. Next, the level of the relay point P1 is read from the storage device 5, and compared with the level of the level register LR3 by the comparator COMP3. If the level of the relay point P1 is greater than or equal to the level of the level register LR3, the level register 1 is added to the contents of LR3 and stored in the P1 storage section of the storage device 5. Further, when the level of relay point P1 is lower than level register LR3, the P1 storage section of storage device 5 is stored at the maximum level MA.
X is memorized. As mentioned above, the sequence instructions numbered 1 to 6 are expressed by the Boolean algebraic expression P1=X1+X2P2+X3P
Execute 3. In addition, using the same procedure, the above formulas (3) to (8)
Boolean algebraic expressions can also be converted into sequential sequence programs. Since this sequence program is repeatedly executed at high speed, the sequence control device shown in FIG. 6 performs a function equivalent to the relay sequence shown in FIG. 8. In this way, the on/off state of the relay point and the level corresponding to the number of other relay points passed through to turn on the relay point are stored in the storage device, and arithmetic processing is performed according to the level. It has certainly become possible to appropriately deal with a wide variety of sequence controls. However, in order to memorize the on/off state and level of this relay point, a memory with a huge storage capacity, such as the storage device 5, is required, and it is clear that the practicality is limited. Countermeasures are necessary.

The purpose of the present invention is to eliminate the need for a large memory for storing the on/off states and levels of the relay points mentioned above, and to replace this, to store the on/off states of the relay points (branch points). Rather than having separate registers for each relay point, we allocated individual column registers for each column in one row, and used this column register in common for each row to achieve the same effect. The object of the present invention is to provide a sequence control device that is inexpensive and allows easy programming of a wide variety of sequences by using this column register, and that can be easily programmed using an expanded connection diagram image of a relay circuit. .

The gist of the present invention is to provide rows of horizontal lines and columns of vertical lines on a CRT screen, and to individually allocate column registers corresponding to each column in one row.
By storing the on/off state of branch points for one row in the column register, and using the column register for the next row when the processing of one row is completed, the relay can be used one after another. PLC machine commands are created that correspond to connection symbols between elements in a circuit development connection diagram, and these commands can be processed.

In order to represent the relay sequence, we create a grid like the one shown in Figure 9 and create a circuit diagram on top of it. In Figure 9,
The leftmost vertical line indicates the common line to which positive voltage is applied.

The rightmost vertical line indicates the ground common wire. Contacts and output coils are written between the horizontal dotted grids. Write the circuit branches on the vertical dotted grid. An example of the circuit is shown in FIG. There are nine patterns of branching in the circuit diagram, as shown in FIG. However, in the example,
To simplify the coding, it is defined that the circuit current only flows first of all from left to right and then from top to bottom. This is because this expression is used in language notation such as English, and is therefore relatively easily accepted by humans. According to this rule, two of the branch symbols "", "゜"", number l and number 9 in the branch symbol No. 0 in Figure 0, do not actually exist.The remaining seven branches It is summarized and explained in the diagram. That is, the entrance to the fork from the left side shows the on/off state connection from the left side to the fork. Next, the entrance to the fork from the upper side, the upper side. It shows the connection in on-off state from the connection.Next, the exit to the right side shows that the on and off states of the branch point are connected to the right side of the branch point.Finally, the exit to the bottom side shows the connection to the right side of the branch point. Target on,
Indicates that the off state is connected to the lower side. The nine types of branches in FIG. 10 are simply the presence or absence of combinations of connections in the four directions in FIG. 11. As shown in FIG. 9, in the sequence control device that should write this branch on the intersection of the vertical dotted line and the horizontal dotted line, there are 1 bits and 2 bits, respectively, in one-to-one correspondence with the vertical dotted line, that is, the column. The default register is prepared. That is, this branch symbol indicates that the on/off state of the branch point of the sequence is stored in a column register that corresponds one-to-one to this column. Therefore, for example, if there are eight columns, eight column registers will be provided.

Connecting the branch point to the outside is equivalent to connecting the contents of this column register to the outside. The order of execution of the sequence is from left to right and then top to bottom as shown in FIG.

Turning point on. The off state is prepared in one-to-one correspondence to each column. First, regarding the first horizontal line, ie, No. 10, start from the left common line. Next, perform the same 10th column to the right in the 1st column, then the 2nd column, and when finished, move on to the next 20th column. The 20th C starts from the left common line side and runs to the right side. Similarly, when the same row ends, the process moves to the next row. Column registers have a one-to-one correspondence with each column, so if a branch point occurs while executing the same row, the on/off state of the branch point is stored in the corresponding column register only for the column where the branch point existed. do.

When executing the next lower row, if there is a branch from above, the on/off state stored in the column register during execution of the upper row is read out and used as branch information from above.
The contents of the column register are those stored in the row above.
Once it is used in the lower row, it is no longer needed in the upper row, so it can be newly used for the lower row, and the on/off state of the branch point being executed can be stored. This means that a memory for storing the on/off state of a branch point is not required at each intersection of each row and column, but it is sufficient to have as many registers as there are for each column for the same row. It shows. That is, in the case of FIG. 12, eight column registers may be provided. 1st
Figure 3 shows the structure of the sequence according to the invention.

The figure shows main memory section 4 that stores sequence programs.
and an arithmetic control unit 10 that decodes sequence instructions and performs arithmetic operations.
It consists of a total of four parts: an input section 1 that takes in process input states, and an output section 2 that outputs output to the process.
Here, the main storage section stores a sequence program, and sequentially sends sequence instructions to the arithmetic control section 10.

The arithmetic control section 10 receives the sequence command from the main storage section 4 and performs the computation according to the instructions of the command. At this time, necessary information is received from the input section 1 and calculations are performed. The output of the calculation result is sent to the output section 2. The input unit 1 sends the input point designated by the number part of the instruction to the calculation unit]0. The output unit 2 sends the output of the calculation result to the output point designated by the number part of the instruction. Here, the number part is the part of the instruction format 140 shown in FIG. 14 excluding the OP part 141. FIG. 15 shows details of the calculation control section 10.

The sequence instructions stored in the main storage section 4 are read out one after another and sent to the arithmetic control section. The arithmetic control unit stores the received instruction in the instruction register 150. The instruction register 150 is classified into an instruction code section (0P) 141 and a number section 142. The number section 142 is connected to the input section 1, the output section 2, and the column register 151.
The input section 1 sends information on the input point designated by the number section] 42 to the AND gate 152. The output section 2 sends the output of the AND gate 153 to the output point designated by the number section 142. FIG. 16 shows a list of instruction systems used in this embodiment. Here, X is the number part 142
indicates the input point specified by . SQAC is SQ in Figure 15
It is an ACl54, 1-bit flip-flop. Y is the output point designated by the number section 142.
R is a column register specified by the number section 142. The column registers are flip-flops of 1 bit each, and as shown in FIG.
The column registers have a one-to-one correspondence and are prepared for only one row. Moreover, as shown in FIG. 12, after the execution of one row is completed, the column register is used when executing the next row. In other words, the column register is designed so that every time one row is completed, the column register is used in the next row. 7
is a logical sum symbol.

Each of the nine types of commands will be explained below using FIG. 15.
(1) Contact Instruction X-SQAC→SQAC The contact instruction read from the SQAC main storage section 4 is stored in the instruction register 150.

The 0P section is read by the decoder 155, and the gate 156 is opened.

The input point specified by the number section 142 is read from the input section 1, and the AND gate 152 performs a logical product with SQAC. The AND result passes through gate 156 and becomes 0R.
It is stored again in SQACl 54 through gate 162. (2) Output instruction 1SQAC→Y 2l→SQAC The output instruction read from the main storage section 4 is stored in the instruction register 150.

The 0P section is read by the decoder] 55, and the gate 153 is opened.

The contents of the SQAC pass through gate 153 and are sent to output 2. The output from the gate 153 is sent to the output point designated by the number section 142. Finally, a binary code "1" is stored in the SQAC. (3) Branch instruction LR
l→SQAC 0P part 14 of the instruction read out from the main memory 4 in the same way
One power bond is reread and gates 157 and 158 are opened.

Column register 151 specified by number part 142
The contents of the first flip-flop of gate 157
, passes through gate 158 and is stored in SQACl 54. ) Branch instruction R, →SQAC The same processing as branch instruction L is performed.

5) Branch instruction] 1SQAC-+Ri 2l→SQAC 0P section 141 of the instruction read from the main memory in the same way
The power bond is reread and gates 159 and 160 are opened.

The contents of the SQAC pass through gates 159 and 160 and are stored in column register 151, which is the first flipflop designated by number section 142 of instruction register 150. Finally, a binary code "1" is stored in the SQAC. 5) Branch instruction SQAC->
Ri Similarly, the branch instruction T read from the main memory 4 is
It is stored in the instruction register 150.

The 0P section 141 is read by the decoder 155, and the gates 159 and 160 are opened.

The contents of SQAC pass through gate 159 and gate 160 and are sent to column register 151. The contents of the SQAC are stored in the column register 151, which is the first flip-flop designated by the number field 142 of the instruction register 150. 1) Branch instruction HOSQAQyRl→
R, 2l-)SQAC A similarly read instruction opens gates 157, 159, and 160.

Column register 1 specified by the number part 142 of the instruction
51 passes through gate 157. The contents of SQAC also pass through gate 159 and enter 0R gate 161. 0
In the R gate 161, the contents of the column register and the SQA
The contents of C are logically ORed.

The result of the OR passes through gate 160 and is stored in column register 151 again. Finally, SQAC has 2
The decimal code "1" is stored. 3) Branch instruction. L.S.Q.A.
QyRl→R1, an instruction read in the same manner as SQAC opens gates 157 and 158, and gates 159 and 160.

Column register 1 specified by the number part 142 of the instruction
The contents of 51 are read out and passed through gate 157. At the same time, the contents of SQAC also pass through gate 159 and enter 0R gate 161. In the 0R gate 161, the contents of the column register 151 and the contents of the SQACl54 are logically summed.

The result of the OR passes through gate 158 and gate 160 and is stored in SQACl 54 and column register 151. (9) Branch instruction + SQACyRl → R1, SQA
This is the same as on the C branch instruction.

FIG. 17 shows an example of a sequence circuit diagram.

In this figure, X indicates an input contact. The subscript number indicates the number of the input point specified in the number section. Y indicates the output point. Similarly, the subscript number indicates the output point number. R at the top. -R3 indicates the position and number of the column register. For example, R. The branch instruction on the same vertical line as
Indicates that the flip-flop of the column register number is used. R3 indicates that the third flip-flop is used.

FIG. 18 shows an example in which the sequence circuit shown in FIG. 17 is programmed.

The programming order is mechanical from left to right and then top to bottom. FIG. 19 shows how the contents S of each register change when the program programmed in FIG. 18 is executed in sequence.

It is clearly seen that the column register effectively stores the on/off state of the branch point and easily derives the final output. As shown in the above embodiments, this method using column registers can be easily programmed with an image that corresponds one-to-one with the relay sequence circuit diagram, and furthermore, There is no need for a huge memory to remember states and levels.

In other words, it is only necessary to provide one register for each vertical line with five registers for one horizontal line, so the capacity of the storage device can be significantly reduced. As a result, it has become possible to provide a sequence processing device that can easily assemble a relay sequence at low cost using a sequence screen image of a CRT or the like.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a relay sequence, FIG. 2 is a diagram showing an early conventional sequence processing device, FIG. 3 is a diagram showing details of the calculation unit 10 in FIG. 2, and FIG. , a diagram showing a sequence circuit diagram that is difficult to describe using a conventional sequence processing device. FIG. 6 is a diagram showing a block diagram of another conventional sequence processing device, FIG. 7 is a diagram showing details of the calculation unit 10 in FIG. 6, and FIG. 6 is a diagram showing an example of a sequence circuit for explaining the operation of the sequence processing device; FIG. 9 is an explanatory diagram of the sequence and screen according to the present invention when a sequence circuit is created using a screen image such as a CRT;
FIG. 10 is a diagram showing the types of branches in the sequence of FIG. 9, FIG. 11 is an explanatory diagram of the operation of the branches in FIG. 10, and FIG. 12 is a diagram showing the order for processing the sequence circuit diagram. ,
FIG. 13 is a block diagram of the sequence processing device in this embodiment, FIG. 14 is a diagram showing the format of machine instructions in this embodiment, and FIG. 15 shows details of the arithmetic control unit 10 in FIG. 16 is a diagram showing the instruction system in this embodiment, FIG. 17 is a diagram showing an example of a sequence circuit, and FIG. 18 is a diagram showing the result of programming the sequence circuit in FIG. 17. Figure 19 shows the first
16 is a diagram showing the transition of contents of each register when the program shown in FIG. 8 is executed by the arithmetic control unit shown in FIG. 15. FIG. 141... Instruction code section, 142...
Number part, 150...Instruction register, 151
... Column register, 154 ... Flip-flop, 155 ... Decoder.

Claims (1)

[Scope of Claims] 1. In a sequence control device that reads a desired sequence command from a sequence program section and performs sequence processing using an arithmetic circuit, a sequence circuit diagram is formed in a matrix shape consisting of vertical lines and horizontal lines, and Each of the contacts and output coil of the relay sequence is written on the horizontal line located between the above two consecutive vertical lines, and the branch point of the relay sequence is written on the intersection of the above vertical line and the horizontal line, and the electrical signal Regarding a sequence circuit diagram in which the flow is defined as first flowing from left to right and then from top to bottom, one register is provided for each vertical line in the first horizontal line of the sequence circuit diagram. The register is shared for each execution of each horizontal line, and the on/off state of the branch point is stored in the register for each execution of each horizontal line, and
The on/off state of the branch point of each register is extracted to be used as input information continuing below and to the right of the sequence circuit diagram, and based on the extracted information, the sequence program section and the arithmetic circuit A sequence control device that performs sequence calculation processing. 2. The sequence control device according to claim 1, wherein the sequence circuit diagram is displayed in a matrix on a CRT display.