JPH1185506A - Data processor having plural condition code processing function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make coordinate calculation efficient by providing 2nd and 3rd condition code registers for backup in addition to a 1st condition code register and controlling a program in accordance with their register values. SOLUTION: This device is provided with two sets of condition code registers 4 and 5 for backup in addition to a condition code register 3 that stores conditions to data of one vertex. Control signals c1 to c3 which control writing to the registers 3 to 5 and automatically switches a method that transfers data among them in accordance with the shape of a polygon group. Relating to a condition branch instruction due to the shape of, e.g. a triangular, a branch condition is inputted to a branch condition deciding part 6 through a signal line s10 for data and the value of a condition code is inputted to it through signal lines s7 to s9 for data. The part 6 decides whether or not the shape of the triangular meets a condition given through the line s10 and outputs the result to a signal line c4 for control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device having a function of processing a plurality of condition codes, and more particularly to a data processing device having a function of processing a plurality of condition codes.
The present invention relates to a data processing device suitable for three-dimensional computer graphics processing.

[0002]

2. Description of the Related Art In three-dimensional computer graphics processing, calculation of coordinate transformation from a coordinate space in which objects are placed (modeling space) to a coordinate space on a screen for displaying them is an important step. In the coordinate calculation, the surface of the object is divided into triangular polygons. At this time, adjacent polygons sharing one side of the three sides are connected to form a strip type or a figure as shown in FIG. It is often expressed as a fan-shaped polygon group as shown in FIG.

In the coordinate calculation, the coordinate data of each vertex of the triangle shown in FIG. 1 is input in the order of the numbers, and calculation for conversion is performed. In the process of this conversion, a condition determination is made as to whether or not data of one vertex is in the display screen. If the data of one vertex is not in the display screen, an operation of setting a new vertex in the display screen is performed. FIG. 10 is a diagram illustrating this operation. FIG. 10A shows a state in which the calculation is performed up to the fifth vertex, but the fourth and fifth vertices extend beyond the display screen. In such a case, FIG.
A new vertex 4 located in the display screen is set as shown in FIG. 0 (b), and control is performed so that the triangular polygon falls within the display screen.

A polygon group of any shape does not form a polygon with only the first two vertices (0 and 1) data.
Each time one or more vertex data is input, one polygon is determined. Assuming that the input vertex number is n, in the case of the strip type, n, n-1, n-
If a polygon is composed of two vertices and is a fan type,
A polygon is composed of three vertices of n, n-1, and 0.

[0005]

Considering the case where the coordinate calculation is performed by software, during the calculation, the vertices input at that time and the information of the other two vertices are added together to calculate the attribute (polygon) as a polygon. Strip type or fan type)
Is determined, and the calculation procedure must be changed based on this. Since the vertices to be referred to differ depending on the shape of the polygon group as described above, the polygon shape is determined assuming a general instruction set. The part becomes overhead.

More specifically, when a program for determining the attribute of a polygon is described using a general instruction set, the program structure has many branches as shown in FIG. 11, and the number of steps increases. In FIG. 11, after a condition code generation step S50 for the latest vertex and a step S51 for reading the condition code for the immediately preceding vertex, a step S52 for determining whether the latest vertex satisfies the condition, a immediately preceding vertex Is followed by step S54 of determining whether or not the condition is met. If both steps S52 and S53 are Yes, it is determined in step 54 whether the polygon is a strip type.

If the Boligon is a strip type, the condition code for the immediately preceding vertex is read in step S55, and it is determined in step S56 whether the immediately preceding vertex satisfies the condition. Is performed when the condition is satisfied in step S57, and when the condition is not satisfied, the process when the condition is not satisfied is performed in step S58.

Here, the processing when the condition is satisfied means the next step (for example, the calculation of the display color) following the coordinate calculation in a series of procedures of the graphics processing. The processing when the condition is not satisfied means that a part of the already generated polygon is
Since it is outside the display screen as shown in FIG. 0 (a), it means a process of setting a new vertex in the display screen as shown in FIG. 10 (b). Hereinafter, the same applies.

After the processing in steps S57 and S58, a processing for saving the immediately preceding condition code as the immediately preceding condition code is performed in step S65, and the latest condition code is saved in step S66 for the immediately preceding condition code. The process of saving as a code is performed. If it is determined in step S54 that the Boligon is a fan type, step S59
The processing of reading the condition code for vertex 0 is performed in
In step S60, it is determined whether the vertex 0 satisfies the condition. If the condition is satisfied, step S6
The process when the condition is satisfied is performed in 1 and when the condition is not satisfied, the process when the condition is not satisfied is performed in step S62. After the processing of step S61 and step S62,
In step S66, processing for saving the latest condition code as the immediately preceding condition code is performed.

If the answer is NO in step S52 for determining whether the latest vertex satisfies the condition or in step S54 for determining whether the immediately preceding vertex satisfies the condition, in step S63, Processing when the condition is not satisfied is performed. Thereafter, in step 64, it is determined whether or not the polygon is a strip type. If the polygon is a strip type, processing S65 for saving the immediately preceding condition code as the immediately preceding condition code S65, Is performed as a process S66. If it is determined in step 64 that the fan type is selected, a process S66 of saving the latest condition code as the immediately preceding condition code is performed.

The present invention pays attention to the fact that the conventional method results in a program having many branches and a large number of steps, thereby enabling a program to be described more easily, and efficient coordinate calculation. It is intended to provide a means to do so.

[0012]

According to the present invention, two sets are added to a condition code register for storing a condition for data of one vertex (for example, a condition for judging whether or not the data exists in a screen image). Means for automatically switching the method of transferring data between them according to the shape of the polygon group, and controlling the program operation according to three sets of condition code register value patterns By providing means for performing these operations and controlling them in combination, it is possible to perform processing with a small number of steps.

The first aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register holding a condition code output from the first condition code register, a third condition code register holding a condition code output from the second condition code register, and an instruction decoder. , And a branch condition determination unit that outputs a branch condition determination signal.

Further, a condition code setting instruction instructing to set a condition code in the first condition code register, an operation of transferring the value of the first condition code register to the second condition code register, and a second operation A first condition code transfer instruction instructing to simultaneously execute an operation of transferring the value of the condition code register to the third condition code register, and transferring the value of the first condition code register to the second condition code register A second condition code transfer instruction for instructing execution of an operation to cause the branch condition determination unit to generate and output a branch condition determination signal in accordance with the values of the first to third condition code registers. The instruction has a conditional branch instruction.

The second aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register holding a condition code output from the first condition code register, a third condition code register holding a condition code output from the second condition code register, and an instruction decoder. , And a branch condition determination unit that outputs a branch condition determination signal.

Further, the operation of setting a condition code in the first condition code register is instructed, the operation of transferring the value of the first condition code register to the second condition code register, and the operation of setting the second condition code register. A first condition code setting / transfer instruction for instructing to simultaneously execute an operation of transferring a value to a third condition code register;
To set the condition code in the condition code register of the second condition code, and to set the value of the first condition code register in the second condition code register.
A second condition code setting / transfer instruction for instructing execution of an operation to be transferred to the condition code register of the first condition code register and a value of the first to third condition code registers are generated and output. And a conditional branch instruction for instructing the branch condition determination unit.

A third aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register holding a condition code output from the first condition code register, a third condition code register holding a condition code output from the second condition code register, and an instruction decoder. The branch condition information and the outputs of the first to third condition code registers, and a branch condition determining unit for outputting a branch condition determination signal; and flag means for indicating the state of the object being processed. .

Further, a condition code setting instruction instructing to set a condition code in the first condition code register, and when the flag takes the first value, the value of the first condition code register is changed to the second condition code. When the flag is set to the second value, the operation to transfer to the condition code register and the operation to transfer the value of the second condition code register to the third condition code register are instructed at the same time. A condition code transfer instruction instructing to execute an operation of transferring the value of the condition code register to the second condition code register;
And a conditional branch instruction for instructing the branch condition determination unit to generate and output a branch condition determination signal according to the values of the first to third condition code registers.

The fourth aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register holding a condition code output from the first condition code register, a third condition code register holding a condition code output from the second condition code register, and an instruction decoder. The branch condition information and the outputs of the first to third condition code registers, and a branch condition determining unit for outputting a branch condition determination signal; and flag means for indicating the state of the object being processed. .

Further, when the flag takes the first value,
An operation for setting a condition code in the first condition code register is instructed, an operation for transferring the value of the first condition code register to the second condition code register, and an operation for setting the value of the second condition code register to the third condition code register. When the flag takes the second value, the instruction to set the condition code in the first condition code register is issued. Condition code setting / instruction to execute an operation of transferring the register value to the second condition code register /
A transfer instruction and a conditional branch instruction instructing a branch condition determination unit to generate and output a branch condition determination signal according to the values of the first to third condition code registers are provided.

The fifth aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register holding a condition code output from the first condition code register, a third condition code register holding a condition code output from the second condition code register, and an instruction decoder. Comparison condition information and the respective outputs of the first to third condition code registers, and a comparison condition determination unit that outputs a comparison condition determination signal, and a fourth condition code that holds the output of the comparison condition determination unit It has a register.

Further, a condition code setting instruction instructing to set a condition code in the first condition code register, an operation of transferring the value of the first condition code register to the second condition code register, and a second operation A first condition code transfer instruction instructing to simultaneously execute an operation of transferring the value of the condition code register to the third condition code register, and transferring the value of the first condition code register to the second condition code register A second condition code transfer instruction for instructing execution of an operation to cause the comparison condition determination signal to be generated in accordance with the values of the first to third condition code registers;
And a condition setting instruction instructing the comparison condition judging section to be stored in the condition code register.

The sixth aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register holding a condition code output from the first condition code register, a third condition code register holding a condition code output from the second condition code register, and an instruction decoder. The comparison condition information and the respective outputs of the first to third condition code registers are input, and a comparison condition determination unit that outputs a comparison condition determination signal, and a fourth condition storage unit that holds the output of the comparison condition determination unit
Condition code register.

Further, (1) an operation of setting a condition code in the first condition code register, (2) an operation of transferring the value of the first condition code register to the second condition code register, and (3) Change the value of the second condition code register to the third
(4) First condition code register
To generate a comparison condition determination signal in accordance with the value of the third condition code register, and simultaneously instruct the comparison condition determination unit to store the comparison condition determination signal in the fourth condition code register.
(1) first condition code setting / transfer / comparison judgment command
Setting a condition code in the condition code register of
(2) an operation of transferring the value of the first condition code register to the second condition code register; and (3) generating a comparison condition determination signal in accordance with the values of the first to third condition code registers. And a second condition code setting / transfer / comparison / judgment instruction for simultaneously instructing the comparison condition judging unit to store the data in the condition code register of No. 4.

The seventh aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register for holding a condition code output from the first condition code register, a third condition code register for holding a condition code output from the second condition code register, A flag means for instructing a state of the object, a comparison condition determining unit for receiving the comparison condition information from the instruction decoder and the respective outputs of the first to third condition code registers, and outputting a comparison condition determination signal; A fourth condition code register for holding an output of the condition determining unit.

Further, a condition code setting instruction instructing to set a condition code in the first condition code register, and when the flag takes the first value, the value of the first condition code register is changed to the second condition code. When the flag is set to the second value, the operation to transfer to the condition code register and the operation to transfer the value of the second condition code register to the third condition code register are instructed at the same time. A condition code transfer instruction instructing to execute an operation of transferring the value of the condition code register to the second condition code register;
A condition setting instruction for generating a comparison condition determination signal in accordance with the values of the first to third condition code registers and instructing the comparison condition determination unit to store the signal in the fourth condition code register is provided.

An eighth aspect of the present invention has the following configuration. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a first condition code register for holding a condition code output from the condition code generator. A second condition code register for holding a condition code output from the first condition code register, a third condition code register for holding a condition code output from the second condition code register, A flag means for instructing a state of the object, a comparison condition determining unit for receiving the comparison condition information from the instruction decoder and the respective outputs of the first to third condition code registers, and outputting a comparison condition determination signal; A fourth condition code register for holding an output of the condition determining unit.

Further, (1) an operation of instructing to set a condition code in the first condition code register, and (2)
When the flag takes the first value, the operation of transferring the value of the first condition code register to the second condition code register and the operation of transferring the value of the second condition code register to the third condition code register Are executed at the same time, and when the flag takes the second value, an operation of instructing to execute an operation of transferring the value of the first condition code register to the second condition code register is provided, and (3) 3) Condition code setting / transfer that simultaneously performs operations of generating a comparison condition determination signal according to the values of the first to third condition code registers and instructing the comparison condition determination unit to store the comparison condition determination signal in the fourth condition code register. / Comparing instruction is provided.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a first embodiment of the present invention. In FIG. 1, 1 is an instruction decoder, 2 is a condition code generator, 3 is a condition code register,
4 is a first backup condition code register, 5 is a second backup condition code register, 6 is a branch condition determination unit, s1 to s10 are data signals (lines), c1 to c.
Reference numeral 4 denotes a control signal (line).

The control signals c1 to c3 are signals for controlling the writing to the condition code registers 3 to 5, and the data signals output from the condition code generator 2 when the control signal c1 is "1". The value of s4 is written to the condition code register 3. When the control signal c2 is "1", the value of the condition code register 3 is written to the condition code register 4 via the data signal line s5. Similarly,
When the control signal c3 is "1", the value of the condition code register 4 is written to the condition code register 5 via the data signal line s6.

The instruction code is input to the instruction decoder 1 through the data signal line s1. The commands constituting this embodiment are a condition code setting command, a strip condition code transfer command, a fan condition code transfer command, and a conditional branch command having a triangular shape. In the condition code setting instruction, the condition code generation unit 2 determines a condition code based on the comparison condition given from the instruction decoder 1 through the data signal line s2 and the operand data given from the data signal line s3. Output to line s4. At the same time, the instruction decoder 1 sets the control signal c1 to “1”. As a result, the condition code is set in the condition code register 3. The number of bits of the condition code is not particularly limited. This corresponds to the step of generating the latest vertex condition code in FIG.

In the strip condition code transfer instruction, the control signals c2 and c3 become "1", the value of the condition code register 3 is transferred to the condition code register 4, and the value of the condition code register 4 is transferred to the condition code register 5. Is done. This corresponds to the step of saving the latest condition code as the immediately preceding condition code and the step of saving the immediately preceding condition code as the immediately preceding condition code in FIG.

In the fan condition code transfer instruction, the control signal c 2 becomes “1”, and the value of the condition code register 3 is transferred to the condition code register 4. This corresponds to the step of saving the latest condition code as the immediately preceding condition code in FIG. In a conditional branch instruction having a triangular shape, the branch condition is transmitted through the data signal line s10, and the value of the condition code is transmitted through the data signal lines s7, s8, and s9.
Are input to the branch condition determination unit 6, and the triangular shape is changed to the data signal line s by the branch condition determination unit 6.
It is determined whether or not the condition given in 10 is satisfied, and the result is output to the control signal c4. This is because in FIG. 11, two conditions are determined as to whether the latest vertex satisfies the condition or the immediately preceding vertex satisfies the condition. Or
In the case of the fan type, the vertex 0 corresponds to a step in which the condition determination as to whether the condition is satisfied is made.

According to the present embodiment, the program in FIG. 11 can be simplified as the program in FIG. In FIG. 2, s1 is a step of generating a condition code for the latest vertex, s2 is a step of determining whether three vertices satisfy the condition, s3 is a processing step when the condition is satisfied in step s2, and s4 is Step s2 is a processing step when the condition is not satisfied. S5 is a step of determining whether or not the polygon is a strip type. S6 is a step of saving the immediately preceding condition code as the immediately preceding condition code. S7 is the latest. In this step, the condition code is saved as the immediately preceding condition code.

It is also possible to incorporate the operation of the condition code setting instruction and the operation of the condition code transfer instruction into one instruction operation. In this case, a condition code setting & transfer command for strip and a fan condition code setting & transfer command are provided. In the strip condition code setting & transfer instruction, the control signals c1 to c3 are all "1", and the condition code determined by the condition code generation unit 2 is set in the condition code register 3, and at the same time, the condition code register 3 before setting is set. Is transferred to the condition code register 4, and the value of the condition code register 4 is transferred to the condition code register 5.

In the fan condition code setting & transfer instruction,
The control signals c 1 and c 2 become “1”, and the condition code determined by the condition code generator 2 is set in the condition code register 3. At the same time, the value of the condition code register 3 before setting is transferred to the condition code register 4. .

FIG. 3 shows a program flowchart in such a case. In FIG. 3, s10 is a step for determining whether or not the polygon is a strip type, s11 is a step for generating a condition code for the latest vertex and transferring a previous condition code when the polygon is a strip type, and s12 is a step for determining whether the polygon is a fan type. In the case of the type, the step of generating a condition code for the latest vertex and transferring the previous condition code, s13 is a step of determining whether or not three vertices satisfy the condition, and s14 is a step of determining whether the condition is satisfied in step 13. The processing step, s15, is a processing step when the condition is not satisfied in step 13.

FIG. 4 shows another embodiment of the present invention. In FIG. 4, reference numerals 1 to 6, s1 to s10, and c1 to c4 are those in FIG.
Are the same as those of the same name. In the embodiment shown in FIG. 4, a flag 7 and a data signal (line) s1 are newly added.
One is added. The flag 7 is a 1-bit flag that indicates the shape of the polygon being processed and can be set by software. The value of the flag is input to the instruction decoder 1 via the data signal line s11.

In this embodiment, two types of the condition code transfer instruction for the strip and the condition code transfer instruction for the fan described in the embodiment shown in FIG. 1 can be executed by one instruction. Introduce a condition code transfer instruction. In the condition code transfer instruction corresponding to the two types, when the value of the flag 7 indicates the strip type, "1" is output to the control signal lines c2 and c3, and the value of the flag 7 indicates the fan type. Control signal line c2
By configuring the instruction decoder 1 to output "1" only to the condition decoder, it is possible to automatically transfer a condition code according to the shape of the polygon.

According to this embodiment, the program shown in FIG. 11 can be simplified as shown in FIG. In FIG.
s20 is a step of generating a condition code for the latest vertex, s21 is a step of determining whether the three vertices satisfy the condition, s22 is a processing step when the condition is satisfied in step s21, and s23 is a processing step in step s21. Is not satisfied, s24 is a step of saving the condition code.

Also, in this embodiment, the improvement described in the latter half of the description of the embodiment of FIG. 1, that is, the operation of the condition code setting instruction and the operation of the condition code transfer instruction are incorporated in one instruction operation is not performed. It is possible. In this case, there are condition code setting and transfer instructions corresponding to the two types, that is, a condition code setting and transfer instruction for a strip and a fan condition code setting and transfer instruction.

FIG. 6 shows a program flowchart at that time. In FIG. 6, s30 is a step for generating a condition code for the latest vertex and transferring the previous condition code, s31 is a step for determining whether or not three vertices satisfy the condition, and s32 is a condition for which the condition is satisfied in step s31. Step s33 is a processing step when the condition is not satisfied in Step s31.

FIG. 7 shows another embodiment of the present invention. The embodiment shown in FIG. 7 uses a condition setting instruction based on a triangular shape instead of the conditional branch instruction based on a triangular shape used in each of the above-described embodiments. In FIG. 7, reference numerals 1 to 5, s1 to s6, and c1 to c3 are the same as those having the same names in FIG. In the embodiment shown in FIG. 7, a logic circuit 8, a condition code register 9, data signals (lines) s12 to s14, and a control signal (line) c5 are newly added.
Has been added.

Here, the condition code register 9 is used by a conventional conditional branch instruction. In the condition setting instruction based on the triangular shape, the contents of the condition code registers 3 to 5 are transferred to the logic circuit 8 through the data signal lines s12 to s14, respectively.
Is output to the data signal line s16 as a 1-bit flag in accordance with the comparison condition input from the data signal line s15. At the same time, "1" is output to the control signal line c5, and the value of the data signal line s16 is stored in the condition code register 9. Condition code register 9
Is a conventional condition code register, which is processed by a conventional conditional branch instruction.

According to the present embodiment, the program in FIG. 11 is similar to the program in FIG. In the embodiment of FIG. 1, the step of “whether the triangle satisfies the condition” in FIG. 2 can be realized only by a conditional branch instruction having a triangular shape. And a conventional conditional branch instruction. Instead, there is an advantage that the implementation of the branch condition is simplified.

Also, in this embodiment, the improvement described in the latter half of the description of the embodiment of FIG. 1, that is, incorporating the operation of the condition code setting instruction and the operation of the condition code transfer instruction into one instruction operation is not possible. It is possible. In this case, in addition to the setting of the condition code register 3 and the transfer to the condition code registers 4 and 5, the setting of the condition code register 9 is realized by one instruction. According to this improvement, the program chart of FIG. 11 is similar to that of FIG.

FIG. 8 shows another embodiment of the present invention. The embodiment shown in FIG. 8 is different from the embodiment shown in FIG.
A 1-bit flag 7 that indicates the shape of the polygon being processed and can be set by software and a data signal (line) s11 are added. 8, reference numerals 1 to 5, 7 to
9, s1 to s6, s11 to s16, c1 to c3, c5
Are the same as those having the same names in FIG. 4 and FIG.

The instructions constituting this embodiment are: (1) an instruction for setting a condition code in the condition code register 2; and (2) an instruction for setting the condition code in the condition code register 3 when the value of the flag 7 indicates a strip type. Instructs that the operation of transferring the value to the condition code register 4 and the operation of transferring the value of the condition code register 4 to the condition code register 5 be performed simultaneously. When the value of the flag 7 indicates a fan type, A condition code transfer instruction instructing to execute an operation of transferring the value of the condition code register 3 to the condition code register 4; (3) generating a comparison condition signal in accordance with the values of the condition code registers 3 to 5; A condition setting instruction instructing the logic circuit (comparison condition determination circuit) 8 to store the data in the register 9. In this case, the program chart of FIG. 11 is similar to that of FIG.

Also, in this embodiment, the improvement described in the latter half of the description of the embodiment of FIG. 1, that is, the operation of the condition code setting instruction and the operation of the condition code transfer instruction are incorporated into one instruction operation, It is possible. In this case, the instructions constituting the embodiment include: a) an operation for instructing the condition code to be set in the condition code register 3; and b) a condition code register when the value of the flag 7 indicates a strip type. 3 to condition code register 4
And the operation of transferring the value of the condition code register 4 to the condition code register 5 are simultaneously executed. If the value of the flag 7 indicates the fan type, the value of the condition code register 3 is And c) a logic circuit that generates a comparison condition signal according to the values of the condition code registers 3 to 5 and stores the comparison condition signal in the condition code register 9. (Comparison condition determination circuit) This is a condition code setting / transfer / comparison / determination instruction for simultaneously performing three operations of the operation instructed to 8. According to this improvement, the program chart of FIG.
Is the same as

[0050]

According to the present invention, the polygon processing in the computer graphics processing can be executed with a small number of program steps, and a remarkable effect that the processing speed can be improved can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing program steps according to a first embodiment of the present invention.

FIG. 3 is a diagram showing another program step according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of another embodiment of the present invention.

FIG. 5 is a diagram showing program steps according to the embodiment of FIG. 5 of the present invention;

FIG. 6 is a diagram showing another program step according to the embodiment of FIG. 5 of the present invention;

FIG. 7 is a configuration diagram of another embodiment of the present invention.

FIG. 8 is a configuration diagram of another embodiment of the present invention.

FIG. 9 is a diagram illustrating the shape of a polygon.

FIG. 10 is a diagram illustrating processing for polygons.

FIG. 11 is a diagram showing a program flow for conventional polygon processing.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 instruction buffer 2 condition code generator 3 condition code register 4 first backup condition code register 5 second backup condition code register 6 branch condition determiner s1 to s10 data signals (lines) c1 to c4 control signals (line)

Claims (9)

[Claims] An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a condition code output from the condition code generator are held. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, branch condition information from the instruction decoder, and respective outputs of the first to third condition code registers.
A branch condition determination unit that outputs a branch condition determination signal; a condition code setting instruction instructing to set a condition code in the first condition code register; and a value of the first condition code register, A first condition code transfer instruction for instructing to simultaneously execute an operation of transferring to the second condition code register and an operation of transferring the value of the second condition code register to the third condition code register; A second condition code transfer instruction for instructing execution of an operation of transferring a value of a first condition code register to the second condition code register, and a value of the first to third condition code registers. And a conditional branch instruction for instructing the branch condition determination unit to generate and output a branch condition determination signal. A data processing device having a processing function. 2. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a condition code output from the condition code generator. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, branch condition information from the instruction decoder, and respective outputs of the first to third condition code registers.
A branch condition determination unit that outputs a branch condition determination signal; instructs an operation of setting a condition code in the first condition code register; and sets a value of the first condition code register to the second condition A first condition code setting / transfer instruction instructing to simultaneously execute an operation of transferring to the code register and an operation of transferring the value of the second condition code register to the third condition code register; And a second condition code setting / instruction to execute an operation of transferring a value of the first condition code register to the second condition code register. A transfer instruction; and a branch condition determining signal generated and output in accordance with the values of the first to third condition code registers. Data processing apparatus having a plurality condition code processing function, characterized in that it includes a conditional branch instruction which instructs the determination unit. 3. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a condition code output from the condition code generator. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, branch condition information from the instruction decoder, and respective outputs of the first to third condition code registers.
A branch condition determining unit that outputs a branch condition determining signal; and a flag unit that indicates a state of the object being processed, and a condition code setting that instructs a condition code to be set in the first condition code register. An instruction, when the flag takes a first value, an operation of transferring the value of the first condition code register to the second condition code register, and setting the value of the second condition code register to the third value. And the operation of transferring the value of the first condition code register to the second condition code register when the flag takes the second value. And a condition code transfer instruction instructing execution of the first and third condition code registers. The branch condition determination signal is generated and output according to the values of the first to third condition code registers. A data processing apparatus having a multiple condition code processing function, comprising a conditional branch instruction for instructing a branch condition determination unit. 4. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information provided from the instruction decoder, and a condition code output from the condition code generator. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, branch condition information from the instruction decoder, and respective outputs of the first to third condition code registers.
A branch condition determining unit that outputs a branch condition determination signal; and a flag unit that indicates a state of the object being processed. When the flag takes a first value, the first condition code register An instruction to set a condition code is given, and the value of the first condition code register is set to the second
When the flag takes the second value, it is instructed to simultaneously execute the operation of transferring the second condition code register and the operation of transferring the value of the second condition code register to the third condition code register. A condition code setting for instructing an operation of setting a condition code in the first condition code register and instructing to execute an operation of transferring a value of the first condition code register to the second condition code register. / Transfer instruction, and a conditional branch instruction instructing the branch condition determination unit to generate and output a branch condition determination signal according to the values of the first to third condition code registers. A data processing device having a multiple condition code processing function. 5. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a condition code output from the condition code generator. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, comparison condition information from the instruction decoder, and respective outputs of the first to third condition code registers.
A comparison condition determination unit that outputs a comparison condition determination signal; and a fourth condition code register that holds an output of the comparison condition determination unit, and instructs to set a condition code in the first condition code register. A condition code setting instruction, an operation of transferring the value of the first condition code register to the second condition code register, and an operation of transferring the value of the second condition code register to the third condition code register And a second condition code for instructing to execute an operation of transferring the value of the first condition code register to the second condition code register. A transfer instruction and a comparison condition determination signal are generated in accordance with the values of the first to third condition code registers, and stored in the fourth condition code register. Data processing apparatus having a plurality condition code processing function, characterized in that it includes a condition setting instruction instructing the comparison condition determining unit to. 6. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a condition code output from the condition code generator. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, comparison condition information from the instruction decoder, and respective outputs of the first to third condition code registers.
A comparison condition determination unit that outputs a comparison condition determination signal; and a fourth condition code register that holds an output of the comparison condition determination unit. (1) A condition code is set in the first condition code register. Operation; (2) an operation of transferring the value of the first condition code register to the second condition code register; and (3) an operation of transferring the value of the second condition code register to the third condition code register. (4) generating a comparison condition determination signal in accordance with the values of the first to third condition code registers, and instructing the comparison condition determination unit to store the signal in the fourth condition code register A first condition code setting / transfer / comparison / determination instruction for simultaneously performing the following operations: (1) an operation of setting a condition code in the first condition code register; and (2) an operation of setting the first condition code. (3) an operation of transferring a register value to the second condition code register; and (3) generating a comparison condition determination signal according to the values of the first to third condition code registers, and The second condition code setting / transfer /
A data processing device having a plurality of condition code processing functions, comprising a comparison determination command. 7. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a condition code output from the condition code generator. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, flag means for indicating the state of the object being processed, comparison condition information from the instruction decoder, and respective outputs of the first to third condition code registers;
A comparison condition determination unit that outputs a comparison condition determination signal; and a fourth condition code register that holds an output of the comparison condition determination unit, and instructs to set a condition code in the first condition code register. A condition code setting instruction to be executed, an operation of transferring the value of the first condition code register to the second condition code register when the flag takes a first value, and a value of the second condition code register Are simultaneously transferred to the third condition code register, and when the flag takes a second value, the value of the first condition code register is changed to the second condition code register. A condition code transfer instruction instructing execution of an operation to be transferred to the first and third condition code registers, and a comparison condition determination signal in accordance with the values of the first to third condition code registers. A data processing apparatus having a multiple condition code processing function, further comprising a condition setting instruction instructing the comparison condition determination unit to store the condition code in a fourth condition code register. 8. An instruction decoder, a condition code generator for generating a condition code based on operand data and comparison condition information given from the instruction decoder, and a condition code output from the condition code generator. A first condition code register, a second condition code register for holding a condition code output from the first condition code register, and a third condition for holding a condition code output from the second condition code register A condition code register, flag means for indicating the state of the object being processed, comparison condition information from the instruction decoder, and respective outputs of the first to third condition code registers;
A comparison condition determination unit that outputs a comparison condition determination signal; and a fourth condition code register that holds an output of the comparison condition determination unit. (1) A condition code is set in the first condition code register. (2) the flag is the first
The operation of transferring the value of the first condition code register to the second condition code register and the operation of transferring the value of the second condition code register to the third condition code register And when the flag takes a second value, an instruction to execute an operation of transferring the value of the first condition code register to the second condition code register. ,
(3) An operation of generating a comparison condition determination signal in accordance with the values of the first to third condition code registers and instructing the comparison condition determination unit to store the comparison condition determination signal in the fourth condition code register is performed simultaneously. A data processing device having a plurality of condition code processing functions, comprising a condition code setting / transfer / comparison judgment command. 9. A plurality of condition code registers for storing conditions for data of vertices constituting a polygon; means for controlling data transfer between the plurality of condition code registers; A data processing apparatus having a multiple condition code processing function, comprising: means for controlling a program operation in accordance with a value pattern.