JPS6129002B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for creating a program for a digital logic circuit-type sequence control device that reads a desired sequence program from a sequence program section and processes it in an arithmetic circuit, and particularly relates to a symbol conversion device for the same. .

FIG. 1 is an example of a sequence circuit widely used in the field of relay sequence control, which is usually called a ladder circuit. In the figure, the symbols A, C, D, etc. are normally open, and the symbol B in Figure 1A is normally closed, and the A contact and B contact, respectively.
This is called a contact point. Also, the 〓 symbol shown by E in Figure 1a and H in Figure 1b is usually called a coil symbol, and represents an element (relay, timer, motor, etc.) that is output as a result of sequence logic operations. . As you can see from this diagram, a ladder circuit generally consists of symbols that represent logic elements, such as the 〓 symbol, 〓, 〓 symbol, etc., and lines that connect the elements that define how they are combined (the logic itself). wiring function in the relay control panel). FIG. 2 shows the configuration of lines (hereinafter referred to as branch symbols) connecting these logic elements. In other words, the ladder circuit is composed of a combination of logic symbols such as 〓, 〓, 〓 (〓, 〓, 〓), the part number of the logic element (α, hereinafter referred to as the source number), and the branch symbol in Fig. 2. be done.

When creating a program for a sequence control device that uses Boolean algebraic symbols as command words based on the ladder circuit shown in Figure 1, list the program (Boolean algebraic expression) that has been converted into Boolean algebraic symbols on a coding sheet, etc. However, it is not always possible to convert symbols on a ladder circuit, especially branch symbols, into Boolean algebra symbols with a one-to-one correspondence, and when converting them, However, there were drawbacks such as the fact that programs could only be created by someone who was familiar with the logical process of converting ladder circuits into Boolean algebraic expressions.

The present invention has been made to eliminate such drawbacks, and each time a branch symbol is input, a logical function corresponding to that symbol is memorized, and the branch symbol is sequentially memorized, and the closing parenthesis of a Boolean algebraic expression is When a corresponding branching symbol is input, it is checked whether or not those branching symbols can be degenerated into any branching symbol by the combination of this symbol and a previously inputted branching symbol, and the degeneracy can be performed. By performing the degeneracy and obtaining the parenthesis information of the Boolean algebraic expression accordingly, the above ladder circuit diagram can be converted to the Boolean algebraic expression simply by inputting the logic symbol, source symbol, and branch symbol expressed in the ladder circuit. The object of the present invention is to provide a symbol conversion device that can convert symbols into .

Embodiments of the present invention will be described below with reference to the drawings.

Equations (1) and (2) are obtained by expanding the ladder circuit diagrams shown in FIGS. 1a and 1b, respectively, using Boolean algebraic expressions. Here, in order to facilitate understanding of the present invention, it is assumed that the signal flow direction (logic direction) in the ladder circuit is only left to right and top to bottom, and there is no right to left or bottom to top (the (See arrow in Figure 1). As can be seen from this formula, the branching symbols in the ladder circuit, or their combinations, allow AND in the Boolean algebraic formula.
Function "・", OR function "+", parentheses function "(,)",
The OUT function "=" can be represented.

A・(+C)・D=E...(1) (A・(B+C)・(D+E)+F)・G=H...(2) Figure 3 is a block diagram showing one embodiment of the present invention. 1 is an input signal into which a ladder circuit symbol is input, 2 is a branch symbol selection circuit that selects a branch symbol signal from input signal 1, 3 is a memory that sequentially stores branch symbols, and 4 is a memory that stores combinations of branch symbols. This is a branch degeneracy circuit that checks the branch symbol selection circuit 2.
When a predetermined branching symbol is selected in , it is checked which branching symbol those branching symbols degenerate into based on the combination of previous branching symbols including that branching symbol. 5 is an address register for the memory 3, 6 is a memory for sequentially storing the input signal 1, and 7 is an address register for the memory 6.

The basis of the present invention is that by checking a branch symbol in a ladder circuit, it is possible to know at which position and how many pieces of bracket information occur, and this is hereinafter referred to as branch symbol degeneracy.

That is, the degeneracy of branching symbols means that branching symbols are stored in memory every time they occur, and among the branching symbols, branching symbols that correspond to a closing parenthesis in a Boolean algebraic expression, i.e., ⊥, 〓, +, When a = symbol occurs, it is checked which branching symbol these symbols degenerate into by combining the previous four branching symbols including the corresponding symbol.
For example, if the 〓 symbol is selected and the three branching symbols before it are 〓, 〓, 〓, then it becomes 〓, and these four branching symbols are reduced to the 〓 symbol. Also,
Similarly, the 〓 symbol is selected, and if the three branching symbols before it are 〓, 〓, 〓, it becomes 〓, and these four branching symbols are reduced to the 〓 symbol. In addition, in the above example, when the result of degeneracy is the 〓 symbol, the same process as if the 〓 symbol was selected again is performed, that is, the three branching symbols earlier than the branching symbol used for the above degeneracy and this Degeneracy with the 〓 symbol is performed.

Regarding Boolean expressions, for example, in the expression A・(B+C)・D=E, (B+
This is the same as converting the above equation to A.Z.D=E by setting C)=Z.

The process of converting a ladder circuit into a Boolean algebraic expression will be described below using the ladder circuit shown in FIG. 4 as an example.

FIG. 5 shows the ladder circuit of FIG. 4 broken down into contact symbols and branch symbols, and it is assumed that the ladder circuit information is input to the input signal 1 of FIG. 3 in the order of the item numbers in the diagram.

(1) Now, first input signal 1 is -〓A of item number 1.
When the information is input, the corresponding information is stored at addresses 1 and 2 of the memory 6 in the format shown in FIG. 6, for example.

(2) Next, when 〓〓B of item number 2 is input to input signal 1, the corresponding information is stored in addresses 3 and 4 of memory 6, and a parenthesis count indicating the degree of overlap of the parentheses at address 3 is stored. is reset and the open parenthesis flag is set. The parenthesis count is "0" in FIG. 6, and the open parenthesis flag is indicated by "(" in the same figure. On the other hand, the branch symbol selection circuit 2 reads that the input signal 1 has a branch symbol 〓, A ? symbol is set at the beginning of the memory 3, for example at address 1, and the address register 5 becomes address 2.

(3) Next, when the 〓 of item number 3 is input, the 〓 symbol is set at address 2 in the memory 3, and the address register 5 becomes address 3. At this time, the contents of the memory 6 do not change.

(4) Next, when 〓〓C of item number 4 is input, OR and C are set at addresses 5 and 6 of memory 6 as shown in Fig. 6, and the parentheses "(" are set. The parenthesis counter is reset.Meanwhile, the branch symbol 〓 is set at address 3 in memory 3, and the address register becomes address 4.

(5) Next, when the 〓 symbol of item number 5 is input, the branch symbol 〓 is set at address 4 in the memory 3.
On the other hand, since the < symbol is a branch symbol corresponding to a closing parenthesis in a Boolean algebraic expression, when the < symbol is input, the previous branch symbol, for example, the branch symbol at address 3 in the memory 3 is referred to. In this case, the branching symbol one branch before is the 〓 symbol, so
The contents of the memory address register are decremented by 1 and 3
address (the storage address in the memory 3 where the next input branch symbol is set). Also, at this time, for example, if the previous symbol is not 〓, refer to the past three branching symbols as described above, and if those branching symbols are 〓, 〓, 〓, change to 〓 symbol, 〓 , 〓, 〓, it is degenerated to 〓 symbol,
It is set in memory 3. And in this case,
The contents of address register 5 are incremented by -3. When the result of the degeneracy is the 〓 symbol, the same processing as when the 〓 symbol is input again, that is, the processing in section (5) is performed.

Note that the contents of the memory 6 do not change in the above steps.

(6) Next, when 〓〓D of item number 6 is input, OR and D are set at addresses 7 and 8 of memory 6, and the 〓 symbol is set at address 3 of memory 3,
Address register 5 becomes address 4.

(7) Next, when 〓〓E of item number 7 is input, AND, E and the closing parenthesis flag ")" are set at addresses 9 and 10 of the memory 6, and the parenthesis counter is reset. Next, the 〓 symbol is set at address 4 of memory 3.
Since the symbol is a branching symbol that corresponds to a closing parenthesis in a Boolean algebraic expression, the past three branching symbols already stored in the memory 3, namely addresses 1 and 2
A degeneracy circuit 4 checks whether the 〓, 〓, 〓 symbol and the 〓 symbol at address 3 are degenerate. In this case, 〓 becomes, and degeneracy is possible, so the contents of the parenthesis counter at address 3 of memory 6, which stores information about the 〓 symbol, is incremented by 1, and the contents of the parenthesis counter at address 9 of memory 6, which stores information about the 〓 symbol, are incremented by 1. The contents of the parenthesis counter are incremented by 1, and 3 is subtracted from the contents of the address register 5, so that the contents of the register 5 become 1.

(8) Next, when item number 8 -〓F is input, OUT and F are set at addresses 11 and 12 of the memory 6.

In this way, when the output symbol is input, the contents of the memory 3 are checked, and if no branch symbol remains (in this embodiment, if the contents of the address register 5 is 1), the ladder circuit is This means that it has been converted (degenerated) into a Boolean algebraic expression, and if you check the contents of addresses 1 to 12 of the memory 6 at this time, they will represent the Boolean algebraic expression symbol. However, if the open parenthesis flag "(" is set like at address 3 and the parenthesis counter of the corresponding memory is not "0", then only one open parenthesis symbol "("
is generated, and only one closing parenthesis symbol ")" is generated at address 9. On the other hand, the open parenthesis flag is set at address 5, but since the parenthesis counter is "0", no parenthesis information is generated when converting into a Boolean algebraic expression.

Also, as a result of degeneracy for each input of ⊥, +, 〓 symbol,
When the branch symbol is degenerated to one of the ⊥, +, and 〓 symbols again, the degeneracy process is further performed with the past branch symbol as if the branch symbol resulting from the degeneracy had been newly input.

By degenerating the branch symbols as described above, symbols such as 〓, 〓, 〓, 〓, 〓, ⊥, and 〓 disappear from the memory 3, and the ladder circuit can be converted into a Boolean algebraic expression.

Also, when a + symbol is input, the branching symbol is divided into ⊥ and 〓 symbols, and the ⊥ symbol is first degenerated, and after a series of degeneration processes are completed, 〓
It is assumed that the processing is performed assuming that the symbol has been input.

FIG. 7a shows the degeneration process of the ladder circuit shown in FIG. 7a, and FIG. 8b shows part of the degeneration process of the ladder circuit shown in FIG. 8a. In both figures, a degeneracy check is performed when the branch symbol marked 〓 _B in the figure is entered, and an open parenthesis is placed at the position of 〓 _A.
〓 Indicates that a closing parenthesis occurs at position _B. In addition, in the case of FIG. 8b, since the result of degeneracy with 〓 _B1 is ⊥, this is an example showing that the degeneracy check proceeds again with 〓 _B2 .

Note that some circuit diagrams cannot be directly converted into a single Boolean algebraic expression, and for such circuit diagrams, the above-described branching and reduction may not be possible.
In such a case, it is sufficient to first rewrite the circuit diagram equivalently into a circuit that can be converted into a Boolean algebraic expression, and then perform branch degeneration using the operations described above.

As described above, according to the present invention, when converting a ladder circuit diagram into a Boolean algebraic expression, each time a branching symbol corresponding to the closing parenthesis of the Boolean algebraic expression is input, the branching symbol and the previously inputted branching symbol are In combination with branching symbols, it is checked whether those branching symbols can be degenerated into any branching symbol, and when it can be degenerated, the degeneration is performed, and the parenthesis information of the Boolean algebraic expression is obtained from the result. Therefore, combinations of contact symbols and branch symbols in ladder circuits can be easily converted into Boolean algebraic symbols, and even operators who do not know Boolean algebra can create programs for Boolean algebraic program controllers from ladder circuit diagrams. There is an effect that can be done.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing a conventional sequence circuit.
FIG. 2 is a block diagram showing branching symbols for connecting logic elements, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing a ladder circuit.
5 is a diagram showing the ladder circuit of FIG. 4 broken down into contact symbols and branch symbols, FIG. 6 is a diagram showing the format stored in the first memory of FIG. 3, and FIGS. FIG. 8a is a block diagram showing another ladder circuit, and FIGS. 7b and 8b are diagrams showing the degeneration process of FIGS. 7a and 8a. In the figure, 2 is a branch symbol selection circuit, 3 is a first memory, 4 is a branch degeneracy circuit, 5 and 7 are address registers, and 6 is a second memory.

Claims (1)

[Claims] 1. Contact information consisting of a contact signal and a contact number;
In a symbol conversion device that converts a ladder circuit diagram relay sequence circuit, which consists of branch information that connects each contact point and can be equivalently converted into a Boolean algebraic expression, into a Boolean algebraic expression, selects a branching symbol included in an input signal. a branch symbol selection circuit; a memory for storing a branch symbol output from the branch symbol selection circuit; and a memory for storing a branch symbol output from the branch symbol selection circuit; It checks whether those branching symbols can be degenerated into any branching symbol by combining them with the previously selected branching symbols stored in the memory, and if it can be degenerated, the degeneration is performed and the Boolean algebraic expression is A symbol conversion device comprising: a branching/reducing circuit that outputs parenthesis information.