JP2000105701A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a data processor which uses a nonvolatile memory for storing necessary programs. SOLUTION: The data processor is equipped with the nonvolatile memory (Flash EEPROM) 2 having stored programs for controlling the operation of the data processor, a RAM 3 which can store some of the programs and has smaller capacity than the EEPROM 2, a CPU 1 which reads programs out of the EEPROM 2 or RAM by specifying addresses and decodes and executes instructions, a means (CPU) 1 which transfers some programs from the nonvolatile memory 2 to the RAM 3, and a flag 5 which specifies whether the operation state of the nonvolatile memory 2 is enabled or disabled, and the flag 5 disables the operation state of the EEPROM 2 when a program stored in the RAM 3 is executed. When a low-power-consumption program in the RAM 3 is executed, the EEPROM 2 having larger power consumption than the RAM 3 is disabled to reduce the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention stores various programs in a non-volatile memory (EEPROM).
More particularly, the present invention relates to a data processing apparatus that reads out and executes a necessary program from a data processing apparatus, and particularly relates to a data processing apparatus that reduces power consumption.

[0002]

2. Description of the Related Art A conventional one-chip microcomputer has a built-in ROM in which a program for controlling the operation of itself is stored. At this time, the price,
In general, a mask ROM is used in consideration of current consumption and the like. However, in a one-chip microcomputer with a built-in mask ROM, when a program needs to be changed, it is necessary to create a new mask and redistribute it.
There is a problem that the cost is increased due to the new design and that it takes a long time to manufacture the microcomputer. Therefore, recently, a one-chip microcomputer using a nonvolatile memory such as an EEPROM capable of writing and reading data as a program memory has been proposed. The advantage of using such a non-volatile memory as a program memory is that the program of the EEPROM can be easily changed by an electrical operation, the mask does not need to be changed, and the user needs to change the storage area. Since only the program can be rewritten, a one-chip microcomputer with a different program can be quickly manufactured without relying on the IC manufacturer and at a reduced cost.

However, EE is used as a non-volatile memory.
When a PROM is used, the above-mentioned advantages are obtained, but the program code is read out from the EEPROM and the
E when operating the chip microcomputer
The current consumption of the EPROM itself is as large as several mA to several tens mA, and there is a problem that even when only a clock operation is performed using a one-chip microcomputer, the current consumption is large and a low power consumption mode cannot be realized. In particular, when used in a battery-driven type device, the drivable time of the device is shortened, which is inconvenient for the user.

In order to solve such a problem, Japanese Patent Laid-Open No.
JP-A-97249 discloses an EEPROM capable of writing and reading data, a read-only mask ROM in which another program code for controlling the operation of the microcomputer is stored as a mask, and an address specification of the EEPROM and the mask ROM. And a control circuit for controlling the program counter to access only one of the EEPROM and the mask ROM based on the result of decoding the program code read from the EEPROM and the mask ROM.
Based on the result of decoding the program code read from the OM, the program counter can access only the mask ROM, thereby realizing a low power consumption mode.

[0005]

However, in the technique disclosed in the above publication, the mask ROM is used as the program memory in the low power consumption mode. However, the mask ROM cannot rewrite the program after manufacturing as described above. For example, if a defect such as a bug is found in the program in the low power consumption mode, there is a problem that the program in the low power consumption mode cannot be executed at all. To modify and execute the program without creating a new mask,
Since the only option is to rewrite the data in the EPROM and read it out from the EEPROM for execution, the low power consumption mode cannot be realized. Furthermore, even if a new program to be processed in the low power consumption mode appears after the manufacture of the one-chip microcomputer, there is a problem that it cannot be added because it is a mask ROM. In addition, when a plurality of programs to be processed in the low power consumption mode are required, it is necessary to prepare all the programs in advance, and as the number of required programs increases, the ROM capacity for storing is required. Would increase the size of the hardware. In particular, some applications do not use some programs, such as when they are prepared to handle a plurality of applications, and the area storing the unused programs becomes useless hardware. Further, as described above, writing data to the mask ROM is performed at the stage of manufacturing a one-chip microcomputer, and it takes a long time to supply the one-chip microcomputer. By using a non-volatile memory such as an EEPROM capable of writing and reading data as a program memory, the program can be rewritten only in a storage area that needs to be changed by a user without relying on an IC manufacturer. ,
The advantage that a one-chip microcomputer with a different program can be quickly made is significantly impaired.

In the technique described in Japanese Patent Application Laid-Open No. 4-303316, in order to reduce power consumption, a memory required to store an externally input application program is required to store the program. A technique is described in which a memory size is checked and power is selectively supplied only to a minimum portion including the memory size.
However, this description is not a technique using a nonvolatile memory such as an EEPROM, so that the above-described EEPROM is not used.
This does not solve the problem of suppressing an increase in power consumption due to the OM.

An object of the present invention is to provide a data processing device using a nonvolatile memory which can reduce power consumption.

[0008]

According to the present invention, there is provided a nonvolatile memory storing a program for controlling the operation of a data processing device, and a memory having a smaller capacity than the nonvolatile memory capable of storing a part of the program. A RAM, a CPU that addresses the non-volatile memory or the RAM, reads a program stored in the non-volatile memory or the RAM, decodes and executes an instruction, and transmits the program from the non-volatile memory to the RAM. Means for transferring the program of the unit, and designation means for designating whether the operation state of the nonvolatile memory is to be enabled or disabled, and the designation means is stored in the RAM. When the program is executed, the operation state of the nonvolatile memory is designated to be disabled.

The present invention also provides a nonvolatile memory storing a program for controlling the operation of the data processing device, a RAM capable of storing another program for controlling the operation of the data processing device, In a data processing device having a CPU that addresses a memory or the RAM, reads a program stored in the nonvolatile memory or the RAM, decodes and executes a command, and an interface unit that acquires data from outside, Means for transferring a program from the outside of the data processing device to the RAM via the interface means, and designating means for designating whether the operation state of the nonvolatile memory is enabled or disabled. The designating means executes a program stored in the RAM. Configured to the operating state of the non-volatile memory specified in the disable state during that.

Here, the designation means for designating whether the operation state of the non-volatile memory is enabled or disabled is selected by a first flag accessed by the CPU. Alternatively, the designating means for designating whether the operation state of the nonvolatile memory is set to the enable state or the disable state is performed by using a part of bits of an address signal for specifying the address. . In this case, some bits of the address signal are, for example, the most significant bits.

In the data processing device according to the present invention, when a small-capacity program for performing only a clock operation is executed, a program necessary for the operation is stored in a small-capacity RAM having low current consumption. The current consumption can be reduced by disabling the large-current-consumption nonvolatile memory and executing it on a small-capacity RAM.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a data processing apparatus 10 according to the present invention.
FIG. 2 is a block diagram of the first embodiment. In the figure,
The CPU 1 decodes and executes an instruction to control each block described later in the data processing device. The CPU 1 outputs an address signal to an address bus 6 and exchanges data with the data bus 4. The flash EEPROM 2 configured as a nonvolatile memory is an electrically rewritable read-only memory (EEPROM), which receives an address signal from the address bus 6 and outputs data to the data bus 4. The flash EEPROM
2 are addresses 0000H to 7FFF in this embodiment.
H (H means hexadecimal notation). Also,
The flash EEPROM 2 is enabled when a signal CE (chip enable) for setting itself to an operation state becomes "0", and becomes disabled when it becomes "1". Flash EE
The PROM 2 is used as a program memory for executing a normal program (including an interrupt program) for controlling the operation of the data processing device.

On the other hand, the RAM 3 is a readable / writable memory, and receives an address signal from the address bus 6 and exchanges data with the data bus 4. The RAM 3 has an address 800 in this embodiment.
It exists in the space of 0H to 80FFH. The RAM 3
It is used for a data memory for storing a program code (including an interrupt program) for executing a low power consumption mode such as a clock operation and a program memory for executing the program code. The data bus 4 is an 8-bit data bus. The flag 5 is a 1-bit register for controlling the operation state of the flash EEPROM 2. The flag 5 is set with data from the CPU 1 via the data bus 4 and supplied to the CE terminal of the flash EEPROM 2. The address bus 6 is a 16-bit address bus for transmitting address signals.

Next, the operation of the data processing apparatus will be described with reference to the flowchart of FIG. It is assumed that the operation based on the program read from the flash EEPROM 2 is temporarily terminated, and the operation is desired to be performed by a low power consumption program such as a clock operation. As a premise, as shown in the memory map of FIG. 3, the code of the low power consumption program is 256 bytes, and the flash EEPROM is used.
It is stored in the space of 7F00H to 7FFFH of the OM2, and the flag 5 is “0”. First, in step S1 of FIG. 2, the CPU 1 sends the address signal 7F0 to the address bus 6 in order to transfer the low power consumption program stored in the flash EEPROM 2 to the RAM 3.
0H is output, and the first byte of the low power consumption program code is read from the flash EEPROM 2 via the data bus 4. Next, the address signal 80 is sent to the address bus 6.
00H is output and the first byte is set to R via the data bus 4.
Write to AM3 (step S2). And CPU1
Repeats the operation of reading the low power consumption program code from the flash EEPROM 2 and writing it to the RAM 3 by 256 bytes, one byte at a time (step S3). As a result, the low power consumption programs are all R
It will be transferred to AM3.

After the transfer of the low power consumption program as described above, the process branches to the start address 8000H of the low power consumption program stored in the RAM 3 (step S4). These controls are performed by the CPU 1 according to a program stored in the flash EEPROM 2. RAM3
After that, the CPU 1 operates according to the program read from the RAM 3. Here, at the beginning of the transferred low power consumption program, a program for disabling the operation of the flash EEPROM 2 is stored, and the CPU 1 sets the flag 5 via the data bus 4 to “5” according to the program at the beginning. 1 ”(step S
5). When the flag 5 becomes “1”, the flash EEPROM
“1” is applied to the CE of OM2, and the flash EE
The PROM 2 is disabled because CE becomes “1”. Thereafter, the CPU 1 executes a process (step S6) based on the low power consumption program from the RAM 3. During this time, since the flash EEPROM 2 is in the disabled state, the power consumption of the flash EEPROM 2 becomes almost zero, and the power consumption of the entire data processing device can be reduced.

Here, in the first embodiment,
The flag 5 can be omitted. FIG. 4 shows a second embodiment as an example. Note that parts equivalent to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, the flag 5 of the first embodiment does not exist, and instead, the flash EEPROM 2
Are connected to the most significant bit A15 of the address bus 6.

The operation of the second embodiment is shown in the flowchart of FIG. In FIG. 5, the flash EEPRO
The low power consumption program code stored in M2 is stored in RAM
3 and the operation from step S1 to S4 until branching to the start address 8000H of the low power consumption program stored in the RAM 3 is the same as the operation in FIG. Here, in order to branch to the RAM 3, the CPU 1 sends the address signal 800 to the address bus 6.
Outputs 0H. That is, the most significant bit A15 of the address bus 6 becomes “1”. When the most significant bit A15 becomes "1", "1" is applied to the CE of the flash EEPROM 2, and the flash EEPROM 2 is disabled. Therefore, as in the first embodiment, during execution of the low power consumption program, the flash EEPROM 2 is disabled, and low power consumption can be realized (step S6). In the second embodiment, a flash EEPROM is used.
The operation state of No. 2 can be switched between the enable state and the disable state by the most significant bit A15 of the address signal, so that a flag for designating the switching control becomes unnecessary, and the circuit can be reduced and data is set in the flag. This eliminates the need for the program code, thereby reducing the consumption of the RAM 3 for storing the low power consumption program code.

Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, the first embodiment shown in FIG.
A serial interface 11 is added to the third embodiment, and an external memory 12 connected via the serial interface 11 is added. The serial interface 11 serving as an interface means takes in the contents of the external memory 12 into the data processing device 10 and outputs the data to the data bus 4. The external memory 12
Is a nonvolatile memory having a built-in serial interface, and has a configuration in which the content can be read out as serial data. In addition, the flash EEPROM
2, the CPU 1 reads a program including a low power consumption program from the external memory 12 and
A program is stored in the AM 3 and thereafter performs an operation of branching to a required address of the RAM 3.

Next, the operation of the third embodiment will be described with reference to FIG.
This will be described with reference to the flowchart of FIG. Assuming that R
The low power consumption program code read from AM3 is 25
6 bytes are stored in the external memory 12 in advance. It is assumed that the flag 5 is “0”. First, the low power consumption program stored in the external memory 12 is transferred to the RAM 3. The CPU 1 reads one byte of the low power consumption program from the external memory 12 through the serial interface 11 and
3 (steps S7, S2). The CPU 1 determines this operation as 256 bytes, which is the number of bytes of the low power consumption program.
It repeats for the number of bytes (step S3). After storing the low power consumption program code in the RAM 3,
Top address 8 of the low power consumption program stored above
000H (step S4). These controls are performed by the CPU 1 according to a program stored in the flash EEPROM 2. Then, similarly to the first embodiment, the flag 5 is set to "1" by the first program of the low power consumption program on the RAM 3, and the flash EEPROM 2 is disabled (steps S5 and S6).

In the third embodiment, since the low power consumption program code executed in the RAM 3 can be read from the external memory 12 outside the data processing device 10 via the serial interface 11, the program in the external memory 12 can be read. By changing the code, there is an effect that different processing can be performed in the low power consumption mode. In this embodiment, the serial interface 1
Although the low power consumption program code is read from the external memory 12 outside the data processing device 10 via the data processing device 1, the same effect can be obtained by reading the low power consumption program code from another data processing device having a serial interface. be able to.

Here, also in the third embodiment,
The flag 5 can be omitted. FIG. 8 is a block diagram of an example of the fourth embodiment, in which the flag 5 in the configuration shown in FIG. 7 is not present, and the CE of the flash EEPROM 2 is replaced with the most significant bit of the address bus 6. A15 is connected.

FIG. 9 is a flowchart showing the operation of the fourth embodiment. The low power consumption program code stored in the external memory 12 is transferred to the RAM 3,
Top address 8 of the low power consumption program stored above
Operation to branch to 000H (steps S7, S2 to S4)
Is the same as in the third embodiment. Also,
The operation after branching to the RAM 3 (step S6) is the same as in the second embodiment, and the address bus 6
The most significant bit A15 of the flash EEPROM
2 is disabled, and low power consumption can be realized. Therefore, the same effects as the respective effects of the second embodiment and the third embodiment can be obtained.

Next, a fifth embodiment of the present invention will be described with reference to FIG. In the fifth embodiment, an interrupt vector generation circuit 7 and a two-input OR gate 8 are added to the configuration of the first embodiment shown in FIG. The interrupt vector generation circuit 7 generates an address signal corresponding to various interrupts when an interrupt occurs, and outputs the address signal to the address bus 6. The two-input OR gate 8 receives the most significant bit A15 of the address bus 6 and the output of the flag 5, and inputs the output to the most significant bit of the address signal of the RAM 3.

The operation of the fifth embodiment will be described in comparison with the operation of the first embodiment shown in FIG. It is assumed that the operation based on the program data read from the flash EEPROM 2 is temporarily terminated, and the operation is executed by the program read from the RAM 3 before an interrupt occurs. Here, when an interrupt occurs during execution of the low power consumption program on the RAM 3 and the most significant bit of the interrupt vector address is "0", the most significant bit A15 of the address bus 6 becomes "0". RAM3
Cannot be accessed, and subsequent interrupt processing cannot be performed by this interrupt program.
However, the low power consumption program code stored in the flash EEPROM 2 is transferred to the RAM 3,
The program branches to the start address 8000H of the low power consumption program stored on M3, sets the flag 5 to "1" by the first program on the RAM 3, and sets the flash EEPROM.
2 to disable state (steps 20 to 2)
By executing 6), the output of the flag 5 becomes “1”, so that the output of the two-input OR gate 8 becomes “1” regardless of the value of the most significant bit A15 of the address bus 6.
Fixed to That is, by setting the flag 5 to “1”, the RAM 3 can be accessed, and even if an interrupt occurs and an interrupt vector address whose most significant bit is “0” is generated, an interrupt program of the RAM 3 can be used. Interrupt processing can be performed. Even when executing this interrupt processing, the flash EEPROM 2
Is in a disabled state, so that low power consumption can be realized. In the fifth embodiment, the access to the RAM 3 is enabled by using the flag 5 for specifying whether the operation state of the flash EEPROM 2 is set to the enable state or the disable state. Similar effects can be obtained by providing and controlling a dedicated flag whose flag becomes "1" when the execution of the program is started.

Next, a sixth embodiment of the present invention will be described with reference to FIG. In this embodiment, an interrupt vector generating circuit 7 and a two-input OR gate 8 similar to those of the fifth embodiment are added to the fourth embodiment shown in FIG. In the fifth embodiment, as in the fourth embodiment, the operation based on the program code read from the flash EEPROM 2 is temporarily terminated,
It is assumed that the operation is performed by the read program from No. 3 and an interrupt occurs. The low power consumption program stored in the external memory 12 is transferred to the RAM 3 and the start address 800 of the low power consumption program stored on the RAM 3 is stored.
0H, the flag 5 is set to "1" by the program code on the RAM 3, and the operation of disabling the flash EEPROM 2 (steps S1 to S4, S
6) is the same as the third embodiment. The operation of the two-input OR gate 8 after setting the flag 5 to “1” is the same as in the fifth embodiment. Therefore, in the fifth embodiment, it is possible to obtain the respective effects of the third embodiment and the fifth embodiment.

In the above-described embodiment, a program for performing a clock operation is shown as an example of the low power consumption program. However, it is needless to say that another program may be used. Also, during execution of the low power consumption program, C
When a command to execute an application program stored in the flash EEPROM 2 is issued from the PU 1, the CE of the flash EEPROM 2 is set to “0” to enable the CPU, and the CPU 1 executes the program processing based on the program read from the flash EEPROM 2. Needless to say,

[0027]

As described above, according to the present invention, a small-capacity RAM for storing a low power consumption program is provided, and a nonvolatile memory in which a program for controlling the operation of a data processing device is stored. Since the operation state can be controlled to be switched between the enable state and the disable state, when the low power consumption program is executed, R
By addressing the AM and disabling the nonvolatile memory, low power consumption can be realized. Accordingly, the data processing device of the present invention is very effective in extending the battery life when applied to a battery-driven portable device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the first embodiment.

FIG. 3 is an address map of an EEPROM and a RAM.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a flowchart for explaining the operation of the second embodiment.

FIG. 6 is a block diagram of a third embodiment of the present invention.

FIG. 7 is a flowchart for explaining the operation of the third embodiment.

FIG. 8 is a block diagram of a fourth embodiment of the present invention.

FIG. 9 is a flowchart for explaining the operation of the fourth embodiment.

FIG. 10 is a block diagram of a fifth embodiment of the present invention.

FIG. 11 is a block diagram of a sixth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Flash EEPROM 3 RAM 4 Data bus 5 Flag 6 Address bus 7 Interrupt vector generation circuit 8 2-input OR gate 10 Data processing device 11 Serial interface 12 External memory

Claims (9)

[Claims] A nonvolatile memory storing a program for controlling the operation of the data processing device; a RAM having a smaller capacity than the nonvolatile memory capable of storing a part of the program; A CPU for addressing the RAM and reading the program stored in the nonvolatile memory or the RAM to decode and execute the instruction. Means for transferring a program; and designating means for designating whether the operation state of the nonvolatile memory is to be enabled or disabled, wherein the designating means executes the program stored in the RAM. The operating state of the non-volatile memory is designated as a disabled state. Data processing device. 2. A nonvolatile memory storing a program for controlling the operation of the data processing device, and a RAM having a smaller capacity than the nonvolatile memory capable of storing another program for controlling the operation of the data processing device. A CPU that addresses the non-volatile memory or the RAM, reads a program stored in the non-volatile memory or the RAM, decodes and executes a command, and an interface unit that acquires data from the outside In the data processing device, means for transferring a program from the outside of the data processing device to the RAM via the interface means, and designation of whether the operation state of the nonvolatile memory is enabled or disabled Specifying means for performing the operation, wherein the specifying means comprises the RAM
A data processing device configured to specify an operation state of the nonvolatile memory to be a disabled state when executing a program stored in the data storage device. 3. The means for transferring a program from the non-volatile memory to the RAM or the means for transferring a program from outside the data processing device to the RAM comprises the CPU. 3. The data processing apparatus according to claim 1, wherein the transfer is performed by reading the program to be transferred via the interface unit and writing the read program into the RAM. 4. A designating means for designating whether the operation state of the nonvolatile memory is enabled or disabled is selected by a first flag accessed by the CPU. The data processing device according to claim 1. 5. A designating means for designating whether the operation state of the nonvolatile memory is to be an enable state or a disable state is performed by a part of bits of an address signal for performing the address specification. 5. The data processing device according to claim 1, wherein the data processing device has a configuration. 6. The data processing device according to claim 5, wherein some bits of the address signal are the most significant bits. 7. A control means for accessing the RAM when an address signal for specifying the address specifies the non-volatile memory,
5. The data processing device according to claim 1, wherein the program stored in M is executed. 8. The data processing device according to claim 7, wherein the control means for accessing the RAM when the address signal specifies the nonvolatile memory is a second flag accessed by the CPU. apparatus 9. The data processing apparatus according to claim 8, wherein the second flag is the same as the first flag.