JPS60245049A - Data processor - Google Patents

Abstract

PURPOSE:To shorten an interruption reaction time without increasing the capacity of a ROM by setting a flag corresponding to a register to be saved by a user through a program, and minimising the number of cycles reqiured to reload the register. CONSTITUTION:The contents of a tag register TR are supplied from an instruction decoder ID to a sequence controller SC through gates g1-gn. A controller SC when an interruption is initiated outputs the contents of only registers corresponding to tab bits set to 1 to a bus BUS except registers corresponding to tag bits set to 0 according to priority predetermined on the basis of the contents of the register TR. Simultaneously, the contents of a stack pointer SP are decreased and data from the BUS are stored in address locations of the stack area in the RAM that the pointer SP indicates. The controller SC when receiving a return interrupt instruction reloads the contents of the stand-by registers in the RAM to the original registers successively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to data processing technology, and relates to a technology that is effective when used, for example, in a register saving method in a microcomputer system.

[Background Art] In a data processing system such as a microcomputer system, when a CPU (microprocessor) receives an interrupt, the program that is being executed is interrupted, jumps to an interrupt routine, and interrupt processing is executed. In that case, if it is necessary to return to the original state when the interrupt processing is finished, before proceeding to the interrupt processing,
The contents of registers such as a program counter must be saved to a stack area such as RAM (random access memory).

Traditionally, register saving as described above has been done in 8-bit microcomputers, for example, by saving all built-in registers related to the user to the stack area of RAM by hardware when an interrupt occurs (for example, in the Showa era). "Microcomputer Basics and 6800J, pages 171 and 180, published by Motorola Semiconductors Japan Co., Ltd. on May 1, 1955).

Therefore, in this method of automatically saving the contents of all registers using hardware, even registers that do not need to be saved (such as unused registers) are saved. Therefore, the number of cycles required to save and restore registers at the time of an interrupt increases, and as the number and capacity of registers increases, the interrupt response time becomes longer and the throughput of the entire system also decreases.

On the other hand, in a 4-bit microcomputer, the contents of the necessary registers are read one by one by a program.
It is designed to be evacuated to the stack area of M.
40 Series User's Manual, page 33).

Therefore, although this method of saving and restoring registers using software reduces the number of cycles required, it increases the burden on the program and increases the ROM capacity to store the program. It's inconvenient.

[Object of the invention] This invention provides a microcomputer system that
The purpose of the present invention is to minimize the number of cycles required for saving and restoring registers executed when an interrupt occurs, thereby shortening the interrupt reaction time without increasing the ROM capacity.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, in a microcomputer system,
Focusing on the fact that there are registers whose contents are not necessarily needed even if they are in use, we created a tag pit (
A tag register consisting of a flag) and a sequential circuit that forms a control signal for saving and restoring the corresponding register based on the contents of this tag register are provided, and the user can program each register in the tag register in advance by using a boo program. By making it possible to set flags corresponding to registers that need to be saved in the tag pit, only the registers specified by the user are saved when one interrupt occurs.

Compared to a method that automatically saves all registers, the number of cycles required for saving and restoring is reduced and interrupt response time is shortened, and compared to a method that saves the contents of necessary registers one by one by a program, it is more efficient.・
This achieves the above object of reducing the ROM capacity by reducing the number of Durham instructions.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a 4-bit single-chip microcomputer.

In the figure, the symbol ROM is a ROM (read-only memory) in which programs for operating the system are stored, and this ROM is a program counter P.
It is accessed by C and outputs the instruction codes that make up the program word by word.

The instruction code read from the ROM is supplied to the instruction decoder ID and decoded, and various control signals for controlling the program counter PC and the various registers and gates described later are formed and output. It is supposed to be done.

RAM (RAM) is a RAM (memory that can be read and written at M times) in which data necessary for program execution and data obtained in response to program execution are stored. This RAM is.

Through the internal bus BUS, the program counter P
C and various registers such as address registers, data registers, and accumulators RE G 11 RE G 2
r...RE G connected to n. Further, an arithmetic logic unit ALU that performs four arithmetic operations, logical operations, etc. is connected to the internal bus BUS.

Although not particularly limited, the internal bus BUS is divided into a bus on which data input to various registers REGI to REGn is carried, and a bus on which data output from registers REG to REGn is carried. , address registers, accumulators, and other registers, the output of the arithmetic logic unit ALU is always inputted through the internal bus.

The registers REG, ~REGn and the arithmetic logic unit ALU are connected to a gate G which is opened and closed by a control signal output from the instruction decoder ID.
It is connected to the bus BUS via i and Go, and when the gate Gi is opened by a control signal, the data on the bus BUS at that time is taken internally, and when the gate Go is opened, the data is transferred onto the bus BUS. It is designed to output data.

In this embodiment, the registers REG'1 to R
In addition to EGn, there is provided a tag register TR consisting of a number of tag bits corresponding to these registers. Tag bits Bt, ~B configuring this tag register TR
tn are each of the above registers REGI to REG.
It corresponds to n.

It is designed to indicate whether the contents of the corresponding register should be saved to the stack area when an interrupt occurs.

Although not particularly limited, for example, if the tag bit Btl is set to 1", this indicates that the contents of the register REG1 corresponding to the tag bit Bt1 need to be saved, and is set to "ago". Register RE G
The content of 1 is designed to indicate that saving is not necessary.

The tag register TR is connected to the bus BUS via gates G, ~Gn, and takes in appropriate data from the bus BUS according to program instructions, and sets each tag bit Btl ~ Btn to 1'' or It07.
1 can be set.

In addition, the above tag register TR is set so that all tag bits Btu to Btn are set to 1111j when the system is reset, although this is not particularly limited.
In this state, all registers RE G 1 to R
The contents of EGn are the RAM R indicated by stack pointer SP.
The data is saved in a stack area within the AM. Therefore, if the user determines that there are no registers that do not need to be saved and writes the program accordingly, the contents of all registers will be automatically saved, just like in conventional 8-bit microcontrollers. It becomes like this.

Moreover, in this embodiment, the registers RE G , ~RE
The contents of the tag register TR itself, which indicates whether Gn needs to be saved or not, are saved after the registers REG to REGn are saved.

In other words, in this embodiment, a sequence controller SC consisting of a sequential circuit constructed by combining appropriate logic gate circuits is provided, and the sequence controller SC is configured by a sequential circuit composed of a combination of appropriate logic gate circuits. The contents of the tag register TR are supplied to the sequence controller SC. When the sequence controller SC generates one interrupt, the tag
In a predetermined priority order based on the contents of register TR, the contents of the register corresponding to the tag bit set to 111?+ are skipped, while skipping the register corresponding to the tag bit set to 10''. Only bus BU
Sequentially output control signals that cause the stack pointer SP to be decremented and the data on the bus BUS to be sequentially stored at the address position of the stack area in the RAM RAM indicated by the stack pointer SP. The sequential circuit is configured to do this.

In addition, the sequence controller SG is configured with a sequential circuit so that the contents of the registers saved in the stack area in the RAM RAM are returned to the original registers in order by the return interleaved instruction executed after the interrupt processing is completed. has been done.

In the above case, although there is no particular restriction, the stack pointer SP is reset to the lowest address of the RAM RAM by system reset, and when registers are saved, the stack pointer SP is set by the sequence controller SC. SP is decremented and the contents of the register are stacked up from the bottom.
stored within. Also, when the register is restored, the stack pointer SP is incremented by one by the sequence controller SC from the address last indicated by the stack pointer SP, and the stored data is read out in order and returned to the original address. It is now returned to the register.

That is, the contents of the registers are stored in the stack area in a FILO (first-in, last-out) manner, ie, what goes in first comes out last. Therefore, the contents of the tag register TR stored last are:
When the register is restored, it is first read and restored, and thereafter, the registers REGI to REGn are restored based on the contents.

Therefore, according to the above embodiment, the tag register T
By setting the contents of R, when an interrupt occurs during program execution, only desired registers can be saved to the stack area.

Furthermore, after the interrupt processing is completed, the data is returned to the original register exactly in the number of cycles equal to the number of saved data.

This reduces the number of cycles required to save and restore registers when one interrupt occurs, compared to the method used in conventional 8-bit microcontrollers that automatically saves all registers, shortens interrupt response time, and System throughput is improved for programs with a large number of

Also, according to the above embodiment, the tag and
Since it is only necessary to set the registers, the number of instructions in the program is less than that of conventional 4-bit microcontrollers, which saves registers one by one in the program when an interrupt occurs, resulting in shorter programs. The capacity of the ROM that stores this can be reduced.

Moreover, according to the above embodiment, by changing the contents of the tag register TR during the program, the designation of the register to be saved can be freely changed, which enables efficient interrupt processing. .

In the above embodiment, the contents of the tag register TR specifying the register to be saved are always saved at the end, but it is not clear whether the contents of the tag register TR itself should also be saved. It may be configured to have a tag pit in which the tag can be set. In that case, in the first reset state, that tag pit is set to a state ("O") indicating that evacuation is not necessary, contrary to the tag pits corresponding to other registers RE01 to REGn, and the program It is also possible to set the evacuation required state (“1”).

Similarly, it is also possible to provide a tag pit for the stack pointer SP, which can set whether or not its contents need to be saved.

In addition, as a method to obtain the same effect as above, for example, provide a tag register similar to the above, set jl I II in the bit corresponding to the register in use, and set it when saving the register. refers to each bit of this tag register one by one, skipping the register corresponding to the bit that is set to "NO", and
A method of saving only the contents of the register corresponding to the bit with 111 set may also be considered. If you do this,
The sequence controller in the above embodiment becomes unnecessary.

However, depending on the contents of the program or user system, not all the contents of registers in use need to be saved at the time of an interrupt.

In other words, even if a certain register contains data,
It is also possible that an interrupt occurs when the data is no longer needed. Therefore.

Saving such registers is wasteful.

According to the above embodiment, if such a state is known, the register can be set in advance not to be saved, which prevents unnecessary saving and is more efficient. There are advantages.

[Effect] In a microcomputer system, there is a tag register consisting of a tag pit (flag) that indicates whether the contents of the register need to be saved or not, and the saving and restoration of the corresponding register based on the contents of this tag register. A sequential circuit is provided to form a control signal for the interrupt, so the user can use a program to set a flag in each tag pit in the tag register corresponding to the register that needs to be saved, so that when an interrupt occurs, the signal specified by the user can be saved. Due to the effect that only the registered registers are saved, the number of cycles required for saving and restoring can be reduced and the interrupt response time can be shortened compared to a method in which all registers are automatically saved. In addition, compared to a method in which the contents of registers required by the program are saved one by one, the number of program instructions is reduced, and the RO
This has the effect of reducing M capacity.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the tag pit corresponding to the register that needs to be saved when an interrupt occurs is set to 1", and the other bits are set to #O.
It is set to II, but on the contrary, #OII may be set for those that require evacuation, and 1"1" may be set for those that are unnecessary.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a 4-bit single-chip microcomputer, which is the field of application that formed the background of the invention, but the invention is not limited to this. It can also be applied to 8-bit microcomputers, 16-bit microcomputers, etc.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a 4-bit single-chip microcomputer system. ROM...ROM (read-only memory), RAM...
...RAM (memory that can be read and written at any time), PC...
...Program counter, ID...Instruction decoder, SP...Stack pointer,
REG1~REGn...Register. T R--Tag register, Bt1 to B'tn, °°
°. Tag pit, SC...control circuit (sequence controller), SUB...internal lotus, G i
, Go, Gz-Gn, gl-gn...gate.

Claims (1)

[Scope of Claims] 1. In a data processing device equipped with a plurality of registers and configured to be capable of interrupt processing, the data processing device is composed of tag pits corresponding to each of the above registers, and each tag bit power is set to ztrIH or ztrIH or A tag register that can be set to 0'', and based on the contents of this tag register, the contents of the corresponding register are saved to the stack area or restored to the original register from the stack area when an interrupt occurs or ends. 2. The tag register also has a bit indicating whether or not its own contents require saving. 3. A data processing device according to claim 1, characterized in that a specific register among the registers is automatically saved and restored when an interrupt occurs, regardless of the tag register. A data processing device according to claim 1 or 2, characterized in that the data processing device is