JPS5685160A - Microcomputer device - Google Patents

Microcomputer device

Info

Publication number
JPS5685160A
JPS5685160A JP14187579A JP14187579A JPS5685160A JP S5685160 A JPS5685160 A JP S5685160A JP 14187579 A JP14187579 A JP 14187579A JP 14187579 A JP14187579 A JP 14187579A JP S5685160 A JPS5685160 A JP S5685160A
Authority
JP
Japan
Prior art keywords
instruction
rank address
higher rank
rst
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14187579A
Other languages
Japanese (ja)
Inventor
Yoshinori Ichiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP14187579A priority Critical patent/JPS5685160A/en
Publication of JPS5685160A publication Critical patent/JPS5685160A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To realize an increase of restart instructions, by executing an original restart instruction fixed to the CPU at the lower rank address region and an instruction set at a higher rank address at the higher rank address region respectively.
CONSTITUTION: For instance, the restart (RST) instruction generating part B as shown in the diagram is provided to the microcomputer device A which contains the CPU1 to execute the RST instruction (the call instruction requiring no designation of the memory address of the jumping destination). Then the original RST instruction fixed to the CPU is executed at the lower rank address region. On the other hand, an instrcution set to a higher rank address is executed at the higher rank address region by switching temporarily the address to a higher rank address in case the CPU reads the RST instruction.
COPYRIGHT: (C)1981,JPO&Japio
JP14187579A 1979-10-31 1979-10-31 Microcomputer device Pending JPS5685160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14187579A JPS5685160A (en) 1979-10-31 1979-10-31 Microcomputer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14187579A JPS5685160A (en) 1979-10-31 1979-10-31 Microcomputer device

Publications (1)

Publication Number Publication Date
JPS5685160A true JPS5685160A (en) 1981-07-11

Family

ID=15302187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14187579A Pending JPS5685160A (en) 1979-10-31 1979-10-31 Microcomputer device

Country Status (1)

Country Link
JP (1) JPS5685160A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839322A (en) * 1981-08-31 1983-03-08 Nec Home Electronics Ltd Data processor
JPS60144836A (en) * 1984-01-07 1985-07-31 Yaskawa Electric Mfg Co Ltd Restart address generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839322A (en) * 1981-08-31 1983-03-08 Nec Home Electronics Ltd Data processor
JPS60144836A (en) * 1984-01-07 1985-07-31 Yaskawa Electric Mfg Co Ltd Restart address generating circuit

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