JPS54120547A - Microprogram memory controller - Google Patents

Microprogram memory controller

Info

Publication number
JPS54120547A
JPS54120547A JP2766878A JP2766878A JPS54120547A JP S54120547 A JPS54120547 A JP S54120547A JP 2766878 A JP2766878 A JP 2766878A JP 2766878 A JP2766878 A JP 2766878A JP S54120547 A JPS54120547 A JP S54120547A
Authority
JP
Japan
Prior art keywords
microinstruction
return
program
counter
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2766878A
Other languages
Japanese (ja)
Inventor
Akira Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2766878A priority Critical patent/JPS54120547A/en
Publication of JPS54120547A publication Critical patent/JPS54120547A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to use one part of a microprogram from any other program as a subroutine, by providing a counter which can be stored with any value by a microinstruction and a FF which is set by a microinstruction.
CONSTITUTION: This controller is equipped with counter 34 which can be stored with one part of the contents of an instruction register through the assignment of a microinstruction and counts down by one at every time when one microinstruction is executed, FF35 which is set by a microinstruction and then reset when the contents of return-address standby register 30 are moved into microprogram counter MPC21, and AND circuit 39. When it is required to return to the original point again during the execution of one part of a program with no return instruction, the number of instructions to be executed until the return to the original program is set to counter 34 firstly, FF35 is set secondary, and then, the output of adder 27 is stored as the return address in register 30 while the contents of MPC21 are substituted with the head address of the program stored in instruction register 24, so that the branch to the head address of an aimed program will be attained.
COPYRIGHT: (C)1979,JPO&Japio
JP2766878A 1978-03-13 1978-03-13 Microprogram memory controller Pending JPS54120547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2766878A JPS54120547A (en) 1978-03-13 1978-03-13 Microprogram memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2766878A JPS54120547A (en) 1978-03-13 1978-03-13 Microprogram memory controller

Publications (1)

Publication Number Publication Date
JPS54120547A true JPS54120547A (en) 1979-09-19

Family

ID=12227318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2766878A Pending JPS54120547A (en) 1978-03-13 1978-03-13 Microprogram memory controller

Country Status (1)

Country Link
JP (1) JPS54120547A (en)

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