JPS62239259A - Microcomputer - Google Patents

Microcomputer

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Publication number
JPS62239259A
JPS62239259A JP61082706A JP8270686A JPS62239259A JP S62239259 A JPS62239259 A JP S62239259A JP 61082706 A JP61082706 A JP 61082706A JP 8270686 A JP8270686 A JP 8270686A JP S62239259 A JPS62239259 A JP S62239259A
Authority
JP
Japan
Prior art keywords
input
buffer
data latch
output
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61082706A
Other languages
Japanese (ja)
Other versions
JPH0664622B2 (en
Inventor
Takaharu Koba
木場　敬治
Masayuki Endo
正之 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61082706A priority Critical patent/JPH0664622B2/en
Publication of JPS62239259A publication Critical patent/JPS62239259A/en
Publication of JPH0664622B2 publication Critical patent/JPH0664622B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE:To cope with the different request of many users to the condition at the time of resetting respective input-output terminals with the changing of the mask of a wiring process by building in a means to set the resetting condition of an internal memory circuit to determine the condition of the input- output terminal to two methods and changing over the means with the wiring. CONSTITUTION:When a resetting signal is connected to the resetting of a data latch 1 by a wiring changing-over part 10, the data latch 1 is reset by the reset ting signal, an output buffer 3 and a buffer 4 come to be an off condition and a buffer 6 comes to be a conducting condition. Consequently, an input-output terminal 11 can fetch the signal of a terminal through the buffer 6 into the internal part as an input terminal. When the resetting signal is connected to the set of the data latch 1 by the wiring changing-over part 10, the data latch 1 is set by the resetting signal, the output buffer 3 comes to be the conducting condition and the contents of a data latch 2 are outputted to the input-output terminal 11. Simultaneously, the buffer 4 comes to be also the conducting condi tion, at the time of reading, the contents of the data latch 2 are read through a reading gate 9.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はマイクロコンピュータに関し、特に入出力端子
を有し、入力端子、出力端子の切替を行うマイクロコン
ピュータに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more particularly to a microcomputer that has an input/output terminal and switches between the input terminal and the output terminal.

〔従来の技術〕[Conventional technology]

従来、マイクロコンピュータは集積回路化されており、
リセット後の入出力端子が入力端子として働くか出力端
子として働くかは、メーカで作成した回路構成で決定さ
れている。仕様を変更してリセット後の端子の状態を変
更するには回路構成を変更し別の品種とする必要がある
。Traditionally, microcomputers have been integrated circuits,
Whether the input/output terminal after reset functions as an input terminal or an output terminal is determined by the circuit configuration created by the manufacturer. To change the specifications and change the state of the pins after reset, it is necessary to change the circuit configuration and use a different type.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

汎用的な集積回路化されたマイクロコンピュータである
＃１ど、多くのユーザによって異なる応用回路で使用さ
れるので、端子ごとにリセット後の入出力の方向に対す
る要求が異ってくのが、上述のようにリセット後の入出
力端子の状態は必ずしも全てのユーザを満足させるもの
とはいえない。Since the microcomputer #1, which is a general-purpose integrated circuit, is used by many users in different application circuits, the requirements for the input/output direction after reset differ for each terminal, as described above. As such, the state of the input/output terminals after reset does not necessarily satisfy all users.

また、メーカも個々のユーザの要求を満足するのが困難
であるという問題がある。Further, there is also the problem that manufacturers have difficulty satisfying the demands of individual users.

〔問題点を解性するだめの手段〕[Means to solve the problem]

本発明のマイクロコンピュータは、回路を初期化するリ
セット信号を発生するリセット手段と、入出力端子とを
有するマイクロコンピュータにおいて、その入出力端子
を入力端子として使用するか出力端子として使用するか
を制御するセット入力及びリセット入力付記憶回路と、
リセット信号をこの記憶回路のセットの力又はリセット
の又のいずれかに配線によって選択的に印加する手段と
を有すること全特徴とする。The microcomputer of the present invention has reset means for generating a reset signal for initializing a circuit, and an input/output terminal, and controls whether the input/output terminal is used as an input terminal or an output terminal. a memory circuit with set input and reset input;
All features include means for selectively applying a reset signal to either the set force or the reset force of the memory circuit by wiring.

〔実施例） 次に、本発明について図面を参照して説明する。〔Example) Next, the present invention will be explained with reference to the drawings.

第１図は大発明の一実施例を表わす回路ブロック図であ
る。データラッチ１はセットリセット付ラッチ、データ
ラッチ２は出力データ保持用のラッチ、出力バッファ３
はトラ−イステート出力のバッファ４，６はトライステ
ィトバッフ・ｒであり、書込み用ゲート７．８はそれぞ
れデータラッチ１゜２にデータを書込む時に導通し、読
出しゲート９は入力信号を内部バスへ入力する時に導通
する。FIG. 1 is a circuit block diagram showing one embodiment of the great invention. Data latch 1 is a latch with set/reset function, data latch 2 is a latch for holding output data, and output buffer 3
The tri-state output buffers 4 and 6 are tri-state buffers, the write gates 7 and 8 are conductive when writing data to the data latches 1 and 2, and the read gate 9 inputs the input signal to the internal bus. Conducts when inputting to.

配線切替部１０はリセット信号が入力され配線によりデ
ータラッチ１のセット入力あるいはリセット入力へ接続
さｎる。データラッチ１の出力は出カパッ７ア３，４の
ゲート信号となり、またインバータ５で反転されてバッ
ファ６のゲート信号となる。データラッチ２の出力は出
力バッファ３に通じて入出力端子１１へ接続されると同
時にバッファ４の入力となる。入力信号は入出力端子１
１からバッファ６に入力される。バッファ６の出力は接
続されて読出ゲート９に入力される。The wiring switching unit 10 receives a reset signal and is connected to the set input or reset input of the data latch 1 by wiring. The output of the data latch 1 becomes the gate signal for the output pads 7a 3 and 4, and is inverted by the inverter 5 to become the gate signal for the buffer 6. The output of the data latch 2 is connected to the input/output terminal 11 through the output buffer 3, and at the same time becomes an input to the buffer 4. Input signal is input/output terminal 1
1 to the buffer 6. The output of buffer 6 is connected and input to read gate 9.

ここで配線切替部１０１Ｃよりリセット信号がデータラ
ッチ１のリセットに接続されている場合、リセット信号
によりデータラッチ１？′ｉリセツトされ、出力バッフ
ァ３、バッファ４はオフ状態となり、バッファ６は導通
状態となる。よっ゛Ｃ入出力端子１１は入力端子として
端子の信号をバッファ６を通じ内部へ順り込むことがで
きろ。Here, if the reset signal from the wiring switching unit 101C is connected to the reset of data latch 1, the reset signal causes data latch 1? 'i is reset, output buffer 3 and buffer 4 are turned off, and buffer 6 is turned on. Therefore, the C input/output terminal 11 can serve as an input terminal and input the terminal's signal to the inside through the buffer 6.

また、配線切替部１０によＩＩ）　１．１セクト信号が
データラッチ１のセットに接続されている場合、リセッ
ト信号によりデータラッチ１はセットさｎ１出力バツフ
ア３は導通となり、データラッチ２の内容が入出力端子
１１へｖｉ力される。同時にバッファ４も導通となり、
読出しを行うとデータラッチ２の内容が読出しゲート９
を通して読出される。In addition, when the wiring switching unit 10 (II) 1.1 sector signal is connected to the set of data latch 1, data latch 1 is set by the reset signal, n1 output buffer 3 becomes conductive, and the contents of data latch 2 are changed. vi is input to the input/output terminal 11. At the same time, buffer 4 becomes conductive,
When reading is performed, the contents of data latch 2 are read out to read gate 9.
read out through

バッファ６はオフ状態であり、入出力端子１１は出力端
子となる。The buffer 6 is in an off state, and the input/output terminal 11 becomes an output terminal.

このようたて本実施例によると配線切替部１ｏの接続を
変更することでリセット信号入力時に入出力端子１１を
入力端子とするか出力端子とするかを選択で０己。According to this embodiment, by changing the connection of the wiring switching unit 1o, it is possible to select whether the input/output terminal 11 is to be used as an input terminal or an output terminal when a reset signal is input.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、入出力端子の状態を決め
る内部記憶回路のリセット状態を二連りに設定できる手
段を内蔵し、その手段を配線で切替える構成とすること
により配暇工程のマスク変更で各入出力端子のリセット
時の状態に対する多くのエーザの咲なった要求に対応で
きるマイクロコンピュータを供給できる効果がある。As explained above, the present invention has a built-in means that can set two reset states of the internal memory circuit that determines the state of input/output terminals, and has a configuration in which the means can be switched by wiring, thereby masking the leisure process. This change has the effect of providing a microcomputer that can meet the increasing demands for the reset state of each input/output terminal.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の回路ブロック図である。。 １・・・・・・データラッチ、２・・・・・・データラ
ッチ、３・・・・・・出力バッファ、４・・−・・・バ
ッファ、５・・・・・・インバータ、６・・・・・・バ
ッファ、７・・・・・・書込ゲート、８・・・・・・書
込ゲート、９・・・・・・読出ゲート、１０・・・・・
−配線切替部、１１・・・・・・入出力端子。FIG. 1 is a circuit block diagram of an embodiment of the present invention. . 1...Data latch, 2...Data latch, 3...Output buffer, 4...Buffer, 5...Inverter, 6... ...Buffer, 7...Write gate, 8...Write gate, 9...Read gate, 10...
- Wiring switching section, 11... Input/output terminal.

Claims (1)

【特許請求の範囲】[Claims] 回路を初期化するリセット信号を発生するリセット手段
と、入出力端子とを有するマイクロコンピュータに於い
て、前記入出力端子を入力端子として使用するか出力端
子として使用するかを制御するセット入力及びリセット
入力付記憶回路と、前記リセット信号を前記記憶回路の
セット入力又はリセット入力のいずれかに配線によって
選択的に印加する手段とを有することを特徴とするマイ
クロコンピュータ。In a microcomputer having a reset means for generating a reset signal for initializing a circuit, and an input/output terminal, a set input and a reset for controlling whether the input/output terminal is used as an input terminal or an output terminal. A microcomputer comprising: a memory circuit with an input; and means for selectively applying the reset signal to either a set input or a reset input of the memory circuit by wiring.
JP61082706A 1986-04-09 1986-04-09 Micro computer Expired - Lifetime JPH0664622B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61082706A JPH0664622B2 (en) 1986-04-09 1986-04-09 Micro computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61082706A JPH0664622B2 (en) 1986-04-09 1986-04-09 Micro computer

Publications (2)

Publication Number Publication Date
JPS62239259A true JPS62239259A (en) 1987-10-20
JPH0664622B2 JPH0664622B2 (en) 1994-08-22

Family

ID=13781845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61082706A Expired - Lifetime JPH0664622B2 (en) 1986-04-09 1986-04-09 Micro computer

Country Status (1)

Country Link
JP (1) JPH0664622B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5425131A (en) * 1977-07-28 1979-02-24 Nec Corp Control system for input-output terminal
JPS59133627A (en) * 1983-01-20 1984-08-01 Seiko Epson Corp Input and output circuit of microcomputer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5425131A (en) * 1977-07-28 1979-02-24 Nec Corp Control system for input-output terminal
JPS59133627A (en) * 1983-01-20 1984-08-01 Seiko Epson Corp Input and output circuit of microcomputer

Also Published As

Publication number Publication date
JPH0664622B2 (en) 1994-08-22

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