JPS59157735A - Data bus control system - Google Patents

Abstract

PURPOSE:To reduce the number of signal terminals to perform an efficient data transfer by transferring another control signal (asynchronous signal) in this period, when data transfer is not performed on a data bus where this time can exist. CONSTITUTION:When an interrupt request signal (asynchronous signal) is issued from an input/output device 6, it is held in a register 16; and thereafter, if decoding of information from a control memory 5 in a decoder 12 results in the detection of a time when a data bus 1 is not used for data transfer, the detection signal is sent to a selecting circuit 14 through a signal line 17, and the interrupt request signal held in the register 16 is selected and is outputted to a specific line of the data bus 1, and the interrupt request signal is stored in an interrupt request receiving register in an LSI3. When the interrupt request signal is permitted by the control of the LSI3, the interrupt request signal is held in a register and is transmitted into an LSI4 through the same process as the above.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data bus control system between logic circuit units, and in particular, the present invention relates to a data bus control system between logic circuit units. It has a remarkable effect on sweat in certain places.

[Prior art]

Conventionally, in an LSI having a data bus, especially in HA B where the number of signals on the data bus is large and the number of signal terminals on the LSI is small, there is a shortage of signal terminals, and the LSI
It was often divided into multiple units, which was unsatisfactory economically.

In addition, there were many periods when data was not transferred on the data bus, resulting in inefficiency. [Object of the invention] By focusing on the period when the data node is not used for data transfer, and by transmitting and receiving other control signal sounds through the data node during this period, the above disadvantages can be resolved without dividing the logic circuit unit. It is to provide the means to overcome it.

[Summary of the invention]

Consider a situation where the signal terminals of an LSI include signals that handle information that can be processed asynchronously (hereinafter referred to as asynchronous signals). The asynchronous signal referred to here refers to the signal generated in Party A's LSI among the signals between LSIs, even after a time period of 1 µm, which is sufficiently long compared to the operating cycle time of the computer, before the signal generated in Party A's LSI is transmitted to Party B's LSI. The present invention focuses on such asynchronous signals contained in the signal terminals of LSIs, and recognizes that there is a "blink period" during which no data is transferred within a certain period of time. In a possible DENTA bus, by transferring the asynchronous signal during the idle period, the signal terminal of the LSI, which is safe for the asynchronous signal, is made unnecessary.
This reduces the number of signal terminals required for SI.

What is needed to realize this function is a logic circuit that first detects that data is not being transferred, and second a circuit that detects whether data is being transferred to the data bus or not. This is a circuit that selects whether to send a signal.

Furthermore, one signal terminal is required for transmitting and receiving a signal indicating that data is not being transferred. That is, if the number of data bus signals is N, then the 9th thickest (N-1
) signal terminals can be reduced.

[Embodiments of the invention] An embodiment of the present invention will be explained below with reference to FIG.

Figure @1 is a block diagram showing the configuration of a data processing device composed of six LSIs.

In the figure, the LSI 2 performs sacrilege processing on the data in the performance unit 1-(ALU).

LSI3 is a microprogram control unit (OU)
The operation is controlled based on the contents of the push-out from the control memory 5.

The LSI 4 is an external control unit (EXTOU) and controls the operation of external devices such as the input/output device 6 and the display 7. Bus line 1 is a data bus, and under normal conditions,
It is used to read data from the register 89 inside the LSI 5 or LSI 4 to the arithmetic unit 15, or to input data from the operator 15 to the register 10% or 11.

Now, when the input/output device 6 issues an interrupt request signal (there are several types. For example, one of them is called interrupt request signal A), that signal is held in the η1j included water holding register 16. . Simply, this signal is the asynchronous signal mentioned earlier. After that, as a result of the information from the control memory 5 being encoded by the decoder 12, when a period which is not used for data transfer on the data bus 1 is detected, the detection signal (hereinafter referred to as a detection signal) is transmitted to the signal line 17. The interrupt enable signal A held in the register 16 is transmitted to the selection circuit 14 via the select circuit 14 and output to a specific one of the data buses 1, and is sent to the interrupt in the LSIW and the Yasugi reception register. 19° Next, when the interrupt request signal A is permitted under the control within the L 813, the interrupt permission signal A is held in the interrupt permission holding register 18. Similarly, this signal is an asynchronous signal.

After -1', when the detection signal is recognized by the decoder 12, it is transmitted to the selection circuit 13, and the interrupt permission signal A held in the interrupt permission holding register 18 is selected.
Output to a specific one of data buses 1, LSI 4
The signal is stored in the yen interrupt permission signal register 20. and,
The reception of the interrupt is displayed on the display 7. The above is the basic operation of this embodiment, but it should be noted that multiple types of interrupt request signals (for example, interrupt Request signals A and B.

C) and interrupt permission signals (for example, interrupt permission signals A', B
, 0) i It is possible to communicate, and it is also possible if the trenches exchange news with each other during the same period.

Next, the effects of the present invention in this example will be described. There are eight interrupt request signals, A to H, and the interrupt permission signal is also A.
If there are eight -H lines, in order to transmit interrupt requests and permissions between LSI3 and LSI4,
Both LS'Is required 16 signal terminals each. However, according to the present invention, only one signal terminal is used for the signal line 17, making the 16 signal terminals unnecessary. That is, the number of signal terminals can be reduced by 15 in each of both LSIs.

This not only saves LSI 9 and LSI 3.4 from being divided into 2 LSIs each due to lack of signal terminals, but also allows LSI 3, which had room for cooking circuit area, to be divided into decode circuit 12 and selection circuit 16. This allows for more effective use of logic circuit area. Furthermore, there is little idle time during the use of the data bus 19, resulting in efficient operation.

〔Effect of the invention〕

As described above, the present invention has the effect of eliminating signal terminals of logic circuit units that are used for asynchronous signals by transmitting asynchronous signals between logic circuit units using the free time of the data bus.

[Brief explanation of the drawing]

The figure shows a professional data processing device showing an embodiment of the present invention.
This is a diagram. 1... Data bus 2... Arithmetic processing unit 3... Micro program control unit 4...
...External control unit 5 ... Control memory 6 ... Input/output device 7 ... Display 15 ... Arithmetic unit

Claims (1)

[Claims] In a data processing device equipped with t g logic circuit units and a data bus commonly connected between the logic circuit units, detect a period during which no data is transferred on the data bus. (2) A data bus control method characterized by transferring information that can be processed asynchronously through a data bus.