JPS62150452A - Peripheral controller - Google Patents

Abstract

PURPOSE:To reduce the power consumption by providing a standby control circuit outputting a control signal and bringing itself into a standby state. CONSTITUTION:An original clock inputted from an original clock input terminal 2 is inputted to the AND circuit 11 of a standby control circuit 1. Further, a, control signal 9 inputted from an input terminal 8 is inputted to the NOR circuit 13 of an output signal control circuit 10, and the output of logic 0, that is, a control signal 7 is inputted to the AND circuit 11 via a NOT circuit 14. Thus, an operating clock 3 is outputted from the AND circuit 11 to an execution circuit 4. When the the peripheral controller at an execution circuit 3 is progressed and a state signal 5 goes to logic 1, the output of a NOR circuit 12 goes to '0' and the control signal 7 of level '1' is outputted from an output terminal 6. Since the control signal 7 is inputted to the AND circuit 11 via the NOT circuit 14 at the same time, no operation clock 3 is outputted and the peripheral controller is in the standby state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peripheral controller, and more particularly to a method for setting a standby mode of a peripheral controller.

[Conventional technology]

Normally, a peripheral controller that exchanges commands and status with the host CPU via memory reads commands from the memory based on control signals from the host, and when the command is executed, writes the status to the memory and controls the host CPU. Sends a signal and ends execution of one command. Thereafter, the above series of operations is performed every time a control signal is received from the host CPU.

At this time, with conventional peripheral controllers, after executing a command, writing the status to memory, and sending a control signal to the CPU (host), there is no need to do anything until the next control signal is received from the CPU (host). , remained in operational mode.

[Problem that the invention seeks to solve]

As mentioned above, traditional peripheral controllers
After sending a control signal to the CPU, it remains in operation mode without doing anything until the next control signal is received, so if this period is long, the power consumption will be wasted. have.

[Means for solving problems]

The peripheral controller of the present invention is a peripheral controller that advances processing while exchanging commands and status with the host CPU, and has a total of two input and output signals that are directly connected to the CPU. In a peripheral controller that has only basic control signals and all commands and status exchanges are performed via external memory using DMA, the above-mentioned system uses a CMOS process and supports standby mode. The device includes a control circuit that controls the output of a control signal and a control circuit that controls an internal standby mode, and has a status signal that simultaneously activates the two control circuits.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

The standby control circuit 1 includes an AND circuit 11 and two N
It is composed of OR circuits 12 and 13 and a NOT circuit 14.

Further, in this embodiment, the output signal control circuit 10 is included in the standby control circuit 1 and is composed of NOR circuits 12 and 13. The original clock input from the original clock input terminal passes through the AND circuit 11, becomes the operating clock 3, and is input to the execution circuit 4. The execution circuit 4 is a circuit that executes the work that should actually be performed by the peripheral controller of this embodiment. The status signal 5 is a signal that becomes ``1'' when the execution circuit 4 enters a certain state, for example, when this peripheral controller finishes writing the status to the external memory.
It is one of the inputs of the OR circuit 12. The control signal 7 is an output signal of the NOR circuit 13 and is outputted to the outside via the output terminal 6. , and the control signal 7 is connected to the NOT circuit 14.
The signal enters the AND circuit 11 through the gate and controls the output of the operating clock 3. The control signal 9 is input from the input terminal 8,
This signal is one of the inputs to the NOR circuit 130.

FIG. 2 is a timing diagram illustrating the operation of the present invention.

It is assumed that immediately after reset, the status signal is 5 to 10''.

Initially, the control signal 9 is set to '1'' via the input terminal 8,
The output of the NOR circuit 13, that is, the control signal 7 becomes 10".The control signal 9 is set to v'0# later.AND
In the circuit 11, the control signal 7 passes through the NOT circuit 14 and becomes '1'.
" Therefore, the operating clock 3 is supplied to the execution circuit 4 through the original clock input from the original clock input terminal 2. Next, in the execution circuit 4, the processing in this peripheral controller progresses and the status signal 5 becomes '1. ", the output of the NOR circuit 12 becomes 0", the control signal 7 becomes 'IN', and the output terminal 6
At the same time, in the standby control circuit 1, the control signal 11" of the control signal 7 is outputted via the NOT
Since the signal passes through the circuit 14 and becomes '0'' and is input to the AND circuit 11, the output of the AND circuit 11 becomes 10''. The operating clock 3 stops and this peripheral controller enters a standby state.

To cancel the standby state, input "1" from input terminal 8.
When input, the output of the NOR circuit 13, that is, the control signal 7 is w″θ′, which passes through the NOT circuit 14 and becomes ``1″.
Therefore, the AND circuit 11 starts supplying the operating clock 3 again.

〔Effect of the invention〕

As described above, the peripheral controller according to the present invention has the effect of reducing power consumption by having a standby control circuit that outputs a control signal and simultaneously puts itself into a standby state.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram of the operation in FIG. 1. 1...Standby control circuit, 2...Original clock input terminal, 3...Operating clock, 4...
...Execution circuit, 5...Status signal, 6...
...Output terminal, 7.9...Control signal, 8.
...Input terminal, 10...Output signal control circuit, 11...AND circuit, 12.13...
...NOR circuit, 14...NOT circuit agent Patent attorney Uchi Hara Sound Figure 1 Figure 2

Claims (1)

[Claims] A peripheral controller that advances processing while exchanging commands and status with the host CPU.
The peripheral controller has only two control signals, one for each input and output, as signals directly connected to the CPU, and all command and status exchanges are performed via external memory using DMA. . A peripheral controller comprising: a control circuit that controls the output of a control signal; and a control circuit that controls an internal standby mode; and a status signal that simultaneously activates the two control circuits.