JPS6349964A - Handshake controller - Google Patents

Abstract

PURPOSE:To improve the efficiency of handshake processing between processors in a dual processor system by detecting a command/parameter readable state and the completion of reading by interruption processing. CONSTITUTION:A CPU 11 sequentially writes commands/parameters in a dual port memory 13. When the writing address reaches a final address for command/ parameter writing which is previously set up in a digital switch 16, a coincident output from a comparator 15 is activated. The coincident output is latched by a flip flop (FF) 17. A CPU 12 starts an interruption routine for executing handshake processing by an output Q from the FF 17. In the interruption routine, the CPU 12 reads out and interpletes the commands/parameters stored in the dual port memory 13. At the time of completing the reading of the commands/parameters by the CPU 12, the FF 17 is restored.

Description

TECHNICAL FIELD The present invention relates to a handshake control device, and particularly to a handshake control device capable of improving the efficiency of handshake processing between processors in a so-called dual processor system.
The present invention relates to a handshake control device.

PRIOR ART FIG. 3 shows a handshake method between processors in a conventional dual processor system.

This will be explained using FIG.

This method uses CPU (1) 11. In a system consisting of a CPU (2) 12 and a dual port memory 13,
A specific flag (rXFERFLAGJ in this case) is stored in the handshake area 14 of the dual port memory 13.
).

In the above method, the CPU (1
) 11 and CPU(2) 12 always need to bore the XFERFLAG, as shown in FIGS. 4(A) and (B), and CPU(1) 11. There is a problem in that the throughput of the CPU (2) 12 may decrease.

Note that although FIGS. 4(A) and 4(B) show the case where commands/parameters are sent from CPU (1) 11 to CPU (2) 12, the same holds true for the reverse case. It's good.

Purpose The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional handshake control method and to improve the efficiency of handshake processing between processors in a dual processor system. It is possible to provide a handshake control table.

Configuration The above-mentioned object of the present invention is to provide two CPUs, and the two CPUs.
In a system with a dual-port memory accessible from the U, one input is connected to the address bus of the CPU sending commands/parameters, the other input is connected to the configuration means, and the comparison has a coincident output of these two inputs. a CPU to which the coincidence output of the comparator is input and which sends out the command/parameter as a clock;
A memory write signal generated from the CPU is input, and one output is the CPU receiving the command parameters.
a flip-flop connected to the interrupt request line of the CPU, the inverted output of which is input to the interrupt request line of the CPU sending the command/parameter; This is achieved by a handshake control device characterized in that it is configured to set a final address value for storing /parameters.

Hereinafter, the configuration of the present invention will be explained in more detail based on FIG. 1.

FIG. 1 is a block diagram of a handshake device in a dual processor system, showing one embodiment of the present invention. In the figure, symbols 11 to 13 indicate the same components as previously shown in FIG.

Further, 15 indicates a comparator, 16 a digital switch, and 17 a flip-flop.

The digital switch 16 has the dual port memory 13 in which commands/parameters are stored.
The command/parameter storage final address value 20 (see FIG. 2) is set.

The operation of this embodiment configured as described above will be explained below. In the following description, a case will be described in which commands/parameters are sent from CPU (1) 11 to CPU (2) 12.

The CP'IJ(1) 11 sequentially writes commands/parameters to the dual port memory 13. This write address is predetermined and written to the digital switch 1.
When the final address of command/parameter writing set to 6 is reached, the match output of comparator 15 (
A=B) becomes active.

The A=B signal is a memory write signal (M
WTC) is latched into the flip-flop 17 to which the clock signal is input, and the Q output of the flip-flop 17 becomes "L".

The Q output of the flip-flop 17 is output from the CPU (2).
)12 interrupt input (INT), so
The CPU (2) 12 then enters an interrupt routine for performing hand X-return processing.

In this interrupt routine, CPtT(2) 12 reads and interprets commands/parameters in dual port memory 13. When the CPU (2) 12 completes reading the command/parameter, the CPU (2) 12 reads the I10
The command output (IOCMD) sets the flip-flop 17, whereby the Q output of the flip-flop 17 returns to <IH''.

Also, at this time, the inverted output Q of the Q output of the flip-flop 17 becomes rzL'', but this inverted output Q is
It is input to the interrupt input (INT) of CPU (1) 11, so that when Q changes to H'', the CPU
U(1) 11 can recognize that CPU(2) 12 has completed reading the command/parameter.

After this, if the CPU (1) 11 needs to send the next command/parameter to the CPU (2) 12,
Write commands/parameters to the dual port memory 13 using the same procedure as above.

According to the above embodiment, the C
The PU(2) 12 can detect the readable state of the command/parameter by interrupt processing, and the CPU(1) 11 that sends the command/parameter can detect the readable state of the command/parameter by the CPU(
2) It is possible to detect by interrupt processing that 12 has completed reading the command/parameter. Therefore,
It is not necessary for any CPU to perform polling for handshake, and the effect is that the throughput of each CPU is improved.

Note that the effect of the above embodiment is that the CPU (2) 12
Needless to say, this can also be obtained when sending commands/parameters to U(1)11.

FIG. 5 shows another embodiment of the invention, which is based on a handshake device in a dual processor system. In the figure, symbols 11 to 1.3.15 and 17
1 indicates the same components as previously shown in FIG. 1, and 18 indicates a register.

In the explanation of the operation of this embodiment as well, the case is shown in which commands/parameters are sent from the CPU (1) 11 to the CPU (2) 12.

The CPU (1) 11 sets the value 20 of the final storage address of the command/parameter in the dual port memory 13 in the register 18 using the I10 command (IOCMD).

The following operation is based on the digital switch 16 of the previous embodiment.
This will be explained by replacing "register 18" with "register 18".

In the case of this embodiment, in addition to obtaining the same effect as the previously described embodiment, the value 20 of the final storage address of the command/parameter set in the register 18 can be easily changed using software. It has the advantage of being possible.

Effects As described above, according to the present invention, in a system having two CPUs and a dual port memory accessible from the two CPUs, one input is connected to the address bus of the CPU that sends commands/parameters. connected to,
a comparator having a coincidence output of these two inputs, the other input of which is connected to a setting means, and a memory write signal generated from a CPU to which said coincidence output of said comparator is input and which sends out said commands/parameters as a clock; a flip-flop whose one output is connected to the interrupt request line of the CPU receiving the command parameters, and whose inverted output is input to the interrupt request line of the CPU sending the command/parameters; and
The handshake control device is configured to set the final address value for storing commands/parameters in the dual-port memory in the setting means, so that the efficiency of handshake processing between processors in a dual-processor system can be improved. This has the remarkable effect of realizing the following.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a handshake device in a dual processor system, showing one embodiment of the present invention;
The figure shows the storage status of commands/parameters in the dual port memory, Figure 3 is a configuration diagram of a handshake device in a conventional dual processor system, Figure 4 is its operation flowchart, and Figure 5 is a diagram showing the storage status of commands/parameters in a dual-port memory. FIG. 2 is a configuration diagram of a handshake device in a dual processor system, showing an embodiment of the present invention. 11: CPU (1), 12: CPU (2), 1
3: Dual port memory, 15: Comparator, 16
: Digital switch, 17: Flip-flop, 1
8: Register. Patent applicant Rico Co., Ltd. -51. Yu, 1-1 Patent Attorney Masatoshi Isomura 1st/No.
2 Figure 3 Figure Φ

Claims (1)

[Claims] (1) In a system having two CPUs and a dual port memory that can be accessed from the two CPUs,
a comparator with one input connected to the address bus of the CPU for sending commands/parameters and the other input connected to the setting means, having a coincidence output of these two inputs, and said coincidence output of said comparator being inputted. , a memory write signal generated from the CPU that sends the command/parameter is input as a clock, and one output is connected to the interrupt request line of the CPU receiving the command parameter, and the inverted output of the output is connected to the interrupt request line of the CPU receiving the command parameter. A flip-flop is provided which is input to an interrupt request line of a CPU on the side that sends the command/parameter, and the setting means is configured to set a final address value for storing the command/parameter in the dual port memory. A handshake control device featuring: