JP2562474B2 - Multi-CPU system adapter and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an adapter for a multi-CPU system and a control method therefor, with the object of reducing the load on the CPU and improving the processing speed of the CPU. In a multi-CPU system consisting of a memory to which commands from are set, an adapter that establishes communication between the CPU and external terminals, and a bus that connects these operating parts, each adapter corresponds to each CPU While the register is provided, the register stores the command and error command indicating the end of processing execution of the adapter,
The configuration is such that the corresponding CPU can be interrupted.

[Industrial applications]

The present invention relates to an adapter, and more particularly to an adapter improved for use in a multi-CPU system so as to reduce the overhead of the CPU.

[Conventional technology]

A multi-CPU system in which a plurality of CPUs are connected to a common bus and a processing result (that is, data) obtained by each CPU is transferred to, for example, a disk has been widely used in recent years. The general example is
It is shown in the figure. The multi-CPU system shown in this figure has a plurality of CPUs 2a, 2b, 2c connected to the system bus 1.
And a main memory 3 for storing processing programs and processing data of each CPU 2a, 2b, 2c, and an adapter 4 for connecting a terminal device such as a disk device for exchanging data with each CPU 2a, 2b, 2c. ing. The adapter 4 receives each data from the system bus 1 to each CPU 2a, 2b, 2c
Corresponding to the input ports 5a, 5b, 5c, a bus 6 provided in the adapter 4, a local memory 7 connected to this bus, and an output connected to the bus for sending data to a disk device or the like. It comprises ports 8 and 9 and a microprocessor 10 which controls the operation of each of these parts. In such a multi-CPU system, either CPU2
a, 2b or 2c (in this case CPU2a as an example) is the C
If a command is issued to the input port 5a corresponding to PU2a and a system bus error or an adapter error occurs during execution of this command, the input port 5a of the adapter 4 raises an interrupt to the access source CPU 2a and at the other CPUs 2b and 2c. Also raise interrupts asynchronously. Based on this, all the CPUs 2a, 2b, 2c that make up the multi-CPU system have the adapter 4
Data is processed in response to an asynchronous interrupt from the side.

[Problems to be Solved by the Invention]

However, in such a conventional adapter 4, when a bus error or an adapter error occurs during execution of a command from one CPU 2a, not only the access CPU 2a but also other CPUs 2b and 2c are interrupted. Therefore, the other CPU2b that has not issued the command to the adapter 4,
The 2c requires a huge amount of complicated software processing to handle asynchronous interrupts, and has a problem of imposing a heavy load on the CPU. In a multi-CPU system, CPUs that do not issue commands, such as the CPUs 2b and 2c, generally perform their own processing. However, such a CPU interrupts from the adapter 4. If the original processing is interrupted by this and interrupt processing must be performed, there is a problem that the processing speed decreases from the viewpoint of the entire system.

The present invention has been made in view of such conventional problems, and an object thereof is to provide an adapter that reduces the load on the CPU and further improves the processing speed of the CPU.

[Means for solving the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. In this figure, reference numeral 11 is a system bus, 12a, 12b, 12c are a plurality of CPUs connected to the system bus, 13 is a main memory for storing various data necessary for the operation of this multi-CPU system, and 14 is this multi-CPU. It is an adapter built into the CPU system. Registers 21a, 21b, 21c corresponding to the CPUs 12a, 12b, 12c are provided in the adapter 14, and these register 21a, 21b, 21c store error commands when an error occurs and An error interrupt is issued to the CPU, and then a command start from another CPU is waited for, and the above error command is specified and interrupted to the other CPU that executed the command.

[Action]

As an operation example of a multi-CPU system, CPUs 12a, 12b, 12
There is a data write or read operation between c and the disk. For example, looking at the operation of CPU-012a,
-012a reads a predetermined processing program from the main memory 13 and executes the program. And the adapter 14
To the I / O connected to the adapter 14, the use request is issued. The adapter 14 analyzes and executes the request from the CPU-012a. When this execution operation ends normally, the adapter 14 sets an end command in the register 021a, raises an interrupt to the CPU-012a, and waits for command activation. On the other hand, if a bus error or an adapter error occurs during execution of the adapter 14, the adapter 14 sets an error command in the internal register 021a, and the CPU-012
Raise interrupt to a. After raising this interrupt, the adapter 14 waits for the command activation of the other CPU-112b, CPU-n12c, and then, for example, if there is a command activation from the other CPU-112b, the register corresponding to the CPU-112b concerned. 1
Set the same error command to 21b and set CPU-112b
Give an interrupt to. Therefore, other CPU-112b and CPU-n12c
Does not receive an error command unless the command is activated, each can execute its own program, improving the operating efficiency of the entire multi-CPU system.

〔Example〕

FIG. 2 is a diagram showing an embodiment of the adapter 14 incorporated in the multi-CPU system shown in FIG. 1, and FIGS. 3 and 4 are flowcharts showing the operation of this embodiment.

In this embodiment, the adapter 14 connects the system bus 11
Connected to the CPU 12a, 12b, 12c provided corresponding to each CPU 12a, 12b, 12c, a bus 16 for data transfer provided in the adapter 14, a local memory 17 connected to the bus 16
And output ports 18 and 19 connected to the bus for sending data to I / O such as a disk device, and a microprocessor 20 for controlling the operation of each of these operating units.
The input ports 15a and 15b are provided with command storage registers 21a and 21b, respectively, so that the commands stored in the registers 21a and 21b can be sent to the CPUs 12a and 12b in an interrupt form.

Adapter 14 and CPU-012a, CPU-112 having such a configuration
The control operation between b will be described with reference to FIGS. 3 and 4. Here, in the flow of CPU1 in FIG. 3, it is assumed that CPU0 accesses the adapter after a bus error or an adapter error occurs at the time of accessing the adapter. Or, when CPU0 accesses the adapter, the buffer is empty.

Multi CPU as shown in Fig. 1 (here, CPU-012a and
In a system in which only the CPU-112b is focused on), when the CPU-012a issues a request to use the adapter 14 in the processing step (indicated by ST in the figure) 1, this CPU-0 program sends a command to the main memory 13 in step 2. writing,
Further, in step 3, it is checked whether the adapter 14 is ready. If the adapter 14 is not ready in this processing step, the check operation is repeated until the adapter 14 becomes ready, and if the adapter 14 is ready,
Activate for 14. However, each CP in this example
The program of U is made so as not to cause the state of Not Ready of the adapter.

On the other hand, in the adapter 14, in step 4, CP
It is checked whether or not the command start flag is set by the U-012a. When the command start flag is set by the CPU-012a, the process proceeds to step 5. Step 5
Then, the firmware reads a command from the main memory 13 to the buffer 22 in the adapter. Then, in step 6, the read command is analyzed and executed. Thereby, for example, as described above, processing such as data transfer from the CPU-012a to the disk device is performed via the input port 015a of the adapter 14. After executing the command in step 6, the adapter 14 proceeds to step 7 and checks whether an error has occurred in the adapter 14 or the bus 11. If no error has occurred in this check operation, the process proceeds to step 8, the end command is set in the register 012a provided in the input port 015a, and the CP is set.
Raise interrupt to U-012a. Thereafter, the adapter 14 resets the command start flag in step 9 and enters the ready state if the buffer is not full, and waits for the command start flag to be set.

On the other hand, when it is determined in step 7 that an error has occurred in the adapter 14 or the bus 11, in step 10, the adapter 14 sets an error command in the register 021a provided in the input port 015a and sends it to the CPU-012a. Raise interrupt. As a result, the CPU-012a recognizes that an error has occurred in the adapter 14 or the bus 11 and executes an error processing routine by interruption. At this stage, the error command interrupt can be issued only to the CPU-012a.
Other CPUs below PU-112b perform their own processing.
After raising the interrupt of the error command, the adapter 14
In step 11, the command activation flag is reset, and if the buffer is not full, it becomes ready and waits for activation from another CPU.

Under this condition, when the CP-112b issues a request to use the adapter 14 in step 12, the program of this CPU-112b writes a command in the main memory 13 in step 13 and the adapter 14 is ready in step 14. Check if there is. If it is determined in this processing step that the adapter 14 is ready, the adapter 14
To start.

For adapter 14, CPU-112b in step 15
From the CPU-112b is checked, and the process proceeds to step S16. Then, in this step 16, the same error command as that described above is set in the register 121b provided in the input port 115b to raise an interrupt to the CPU-112b.
When the processing steps in which the steps ST11, ST15, ST16 are put together are represented by STX, the processing steps are represented as shown in FIG. 4, and are repeated until the CPUs are activated.

That is, as shown in FIG. 4, in response to the activation from the CPU-n, the command activation flag is reset in ST11a after raising an error command interrupt to the CPU-n-1.
In step 15, it is checked whether the command activation flag has been set. When the command is moved from the CPU-n, the same error command as that interrupted so far is set in step 16a, the CPU-n is interrupted, and the command activation flag is reset in ST11b. While such a series of processing loops continues, the adapter 14 waits for an adapter reset in step 17 in FIG.

〔The invention's effect〕

As described above, according to the present invention, the adapter has a register for setting a command, and when the adapter detects a bus error or an adapter error, the error command is interrupted only to the access source CPU, and thereafter, Other C
Since the error interrupt is performed after waiting for the command activation from the PU, the processing program for the asynchronous interrupt of the CPU can be deleted and the software can be simplified. Further, the CPU does not hinder the program execution due to the asynchronous interrupt during the execution of its own program, so that various effects such as an increase in processing speed and an improvement in work efficiency can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of an adapter used in the present invention, and FIG. 3 is a diagram showing the present invention.
Flowchart showing operation example of CPU and adapter, fourth
FIG. 5 is a flow chart showing the error interrupt operation in the operation of the CPU and the adapter, and FIG. 5 is a conventional multi-CPU.
FIG. 6 is a block diagram showing a system, and FIG. 6 is a block diagram showing a configuration example of a conventional adapter. 11 …… Bus 12a, 12b, 12c …… CPU 13 …… Main memory 14 …… Adapter 21a, 21b, 21c …… Register

Claims (2)

(57) [Claims] 1. A data transmission bus (11) is provided with a plurality of CPUs (12).
In a multi-CPU system in which a), (12b), (12c), a main memory (13) for storing commands, and an adapter (14) for establishing communication between a CPU and an external terminal device are connected, When the adapter detects at least one of a bus error and an adapter error, it makes an error interrupt to the access source CPU, and then waits for command activation from another CPU,
An adapter control method for a multi-CPU system, characterized in that the system is controlled by performing an error interrupt to the other CPU that has activated a command. 2. A plurality of CPUs (12a), (12b), (12c), a memory (13) in which a command from the CPU is set, and an adapter (for establishing communication between the CPU and an external terminal device). 1
4) and a bus (11) connecting the CPU to the memory and the adapter,
In the multi-CPU system consisting of, the adapter has a register corresponding to each CPU, stores an error command when an error occurs in this register, issues an error interrupt to the access source CPU, and then other CPUs.
Waiting for command activation from the CPU, and performing an error interrupt by specifying the same error command as above to the other CPU that has activated the command
System adapter.