JPS61118858A - Channel controlling system - Google Patents

Abstract

PURPOSE:To improve the data processing capacity of a channel by executing a data transfer of other channel, while waiting for an MS access end by a CCW fetch of some channel. CONSTITUTION:A staging part 12 is divided into two of A and B, and a data transfer request and a CCW fetch request are brought to staging to a part A and B, respectively. In this state, when waiting an access end by an MS access of a CCW fetch, if a data transfer request exists in the part A, a priority part executes it. In this case, a CS address to a CCW fetch request which is being executed is saved in a CS address holding part 28. When the MS access has been ended, as soon as a data transfer processing which is being executed by a processor at present is ended, the CS address which has been held in the holding register part 28 is delivered to a control part 14, and a CCW fetch processing is restarted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a channel control method in a system in which a plurality of channels are controlled by one microprocessor.

[Conventional technology]

In computer systems, the central processing unit CPU and main memory MS
Usually, the input/output device I10 is connected to the input/output device I10 through a channel device.

If there are a large number of Ilo's, there will be a plurality of channels, and a method is adopted in which these plurality of channels are controlled by one microprocessor.

FIG. 2 is a block diagram showing the configuration of a conventional channel control unit, which includes a processor processing request stack unit 10, a staging unit 12, a C3 (Control Storage) address control unit 14, a CSSi2010 control unit 18, and a processor unit. 20 (the body in FIG. 2 is a microprocessor, and 20 is especially its arithmetic control unit), external register 22, L S (Iocal Storage)
It consists of a data transfer buffer section 24, a data transfer buffer section 26, and the like. There are a large number of input/output devices I10 #0 to #N (channels are the same), and these are connected to the control section 18 and the buffer section 26.

This processing request to the channel control unit is based on the channel, CP
Since these requests are generated from U and the data transfer buffer unit, these requests are input to the stack unit 10 via the path of CPU→10.18→10°26→10 and are stacked in order. CPU
The request from is a start I10 or the like. A request from the buffer section 26 occurs when data has accumulated in the buffer section and data can be sent. When loading data to an MS, the load destination MS address is stored in the external register section 22.
, and every time data is sent, the amount of data sent is subtracted to find the amount of remaining data.
This is performed by the processor section 20.

The processing requests stacked in the stack unit 10 are selected one by one, taking into account the priority, and sent to the staging unit 12, and the CS address is determined according to the content of the processing request.
The C8 unit 16 is accessed via the 111811 unit 14, the required control program is read out, and the above request is processed from there.

The work of the channel is to transfer data, fetch commands from the main memory MS, report the quality of data transfer results to the main memory, etc., but they can be broadly divided into data transfer and other tasks.
Here, the latter is simply referred to as CCW (Channel Com+
5 and Word) fetch. Since data transfer is data exchange between main memory and Ilo, main memory access is frequently performed during this period, but in CCW fetch, except for fetching commands from main memory and writing to main memory for reporting, etc. The processor spends a lot of time parsing commands and checking formats without accessing main memory.

[Problem that the invention seeks to solve]

In FIG. 3(a), channel #A first performs data transfer, then channel #B performs CCW fetch, then channel #C performs data transfer, and channel #B's CC
In W fetch, MS access was performed twice...
・Here is an example. The first MS access in this CCW fetch corresponds to requesting a command from the MS,
The second time, there is a data address in the retrieved command, but this is an intermediate one, and the true data address can be obtained by accessing the MS with that address.
Respond to access. Periods other than MS access include the above-mentioned format check, command analysis, etc. When the MS is accessed, it takes some time until the access is completed, that is, until the read data is sent in the case of MS reading, and during this time there is a waiting (idle) state. If this waiting state can be used for data transfer on other channels, the waiting time can be reduced and the processing capacity can be increased.

Processing a request for another channel while processing a request for one channel generally requires processing such as saving data in a register. However, data transfer only updates the data address of the LS section, the same number of bytes, and sets the address register for memory access in the external register. Even if the above data transfer is executed, the external register set by the CCW fetch of the certain channel is not updated. Therefore, even if the processor performs data transfer processing on other channels while waiting for CCW fetch or memory access to complete, there is no need to save/restore external registers, and the CS address to be executed next is retained when memory access is completed. Just leave it there.

The present invention has been made in view of the above-mentioned problems, and is intended to improve processing performance by performing CCW fetch on a certain channel and transferring data on another channel during the end of MS access.

Means for Solving Problem c] In a channel control method in which multiple channels are controlled by a common microprocessor, the present invention separates channel processing requests into data transfer processing requests and other processing requests, and separates processing requests other than data transfer processing requests. When the memory access is waiting for completion due to execution, the control memory access address at that time is saved and a data transfer processing request from another channel is adopted instead, and the control memory access address for processing the request is saved. The control storage is accessed using the control memory to execute the data transfer process of the other channel, and after the execution is completed, the save address is used to continue the process at the time of the end.

As shown in FIG. 3(b), in the present invention, channel #B is
Immediately after the MS access ends with CW fetch, data transfer for channels #C and #D is performed during this time. In this way, the data transfer of channel #C, which had to wait until the completion of the CCW fetch of channel #B, can be performed in the first half of the CCW fetch period of channel #B, and the data transfer of channel #D can also be performed earlier. can be executed.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which the same parts as in FIG. 2 are given the same reference numerals. That is, 10 is a processor processing request stack unit that holds processor processing requests generated in each channel, 12 is a staging unit that stages processing requests of the staff, and 14 is a stack unit that holds processing requests output from the staging unit. A CS address control section 16 which determines the CS address is a C8 section that holds a microprogram. Further, 20 is a processor section, which starts the I10 instruction from the CPU, and receives the I10 instruction from the I10 control section 18.
CPU or subchannel (Il) by processing interrupts.
o) control, command chaining, data chaining, CCW fetch and check from MS when starting I10, update of data address and number of bytes in LS section 24 by data transfer processing from data transfer buffer section 26, and MS Control the activation of access to, etc. LS section 24
holds the communication engine or subchannel CCW of the I10 control unit 1 and the processor unit 20, and is provided corresponding to each channel. 22 is an external register section, LS
It consists of a work register that holds read data from the section 24 and enables high-speed access to the data, an address register for MS access, a CPU interface register, and others.

The data transfer buffer unit 26 temporarily holds and controls I10 interface data provided corresponding to each channel.

As is clear from a comparison of FIG. 1 and FIG. 2, in the present invention, the staging section 12 is divided into two parts A and B, and a CS address holding register section 28 and a memory access completion wait control section 30 are provided. The reason why there are two staging units 12, A and B, is to stage data transfer and CCW fetch processing requests separately. Here, it is assumed that data transfer requests are staged in part A and CCW fetch requests are staged in part B. The Brioli section of the staging section 12 determines the processing request to be executed next. In other words, the staging unit 12 stores the processing request currently being executed, the data transfer request of the staging A unit, and the CC of the staging 8 unit.
It can be assumed that a maximum of three W fetch requests are received, and it is determined which processing request to be executed next, A or B.

When a CCW fetch MS access waits for the access to end, the priority section causes the staging A section to execute the data transfer request if there is one (because the channel does not issue two processing requests at the same time, the data transfer request is channel) is currently running
It is necessary to save the CS address for the W fetch request (if this is not done, it will be difficult to know where to restart from next), and the CS address holding unit 28 is the destination for this save.

In order to enable jump processing at the end of MS access, the present invention provides two types of micro-orders that indicate the end of a microprogram processing routine. One of them is “
``Completely completed'' indicates that the microprogram processing routine has completely terminated. The other one is "wait for completion of memory access", and when this micro-order is executed, the memory access completion wait control section 30 causes the CS address holding register section 28 to hold the CS address to be executed at the end of MS access, and Waiting for access from .

Also, at this time, a signal is sent to the priority section to cause the staging A section to execute the data transfer process held in it.

That is, the CS address determined by the content of the request (this is determined by the control unit 14) is set in the now empty control unit 14, the C8 unit 16 is read out using the address, and the processor unit is controlled by the read microprogram. 2
Operate 0. CCW held in staging section 8
Fetch requests are not processed until a "complete" micro-order is executed. When the MS access ends, as soon as the data transfer process currently being executed by the processor ends, the CS address held in the holding register unit 28 is passed to the control unit 14, and the CCW fetch process is restarted.

In data transfer, the address of the MS to be fetched/stored and the number of bytes of data to be fetched/stored are stored in the LS section 2.
4, and MS access is performed by setting the MS address in the external register section 22. Since the number of data bytes is in the command, it is written to the LS section 24, and every time data is transferred thereafter, the processor 20 subtracts the number of data bytes from the LS section 24, and writes the result to the LS section 24. . The LS part used for data transfer and the LS part used for CCW fetch are distinct and have nothing in common. The MS access address set in the external register section 22 is not needed after the MS fetches it, so the address is written to the external register section 22 by CCW fetch, and then the address is written to the external register section 22 by data transfer. Even if the address is deleted (the previous address will be deleted), there is no particular problem. In other words, the external register section 22 can be shared by CCW fetch and data transfer. The processor unit 20 uses the register for CCW fetch and stores its contents by simply setting data in the LS register, calculating the amount of remaining data, and updating the LS register based on the calculation results during data transfer. It will not be destroyed (the work registers in the register section 22 are divided into data transfer and CCW fetch angle). Therefore, jump processing is possible while the MS access is being completed.

〔Effect of the invention〕

As explained above, according to the present invention, data transfer processing for other channels is performed while MS access is being completed for processing other than data transfer, so that it is as if the memory access waiting time has been reduced. It is possible to improve the data transfer speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional method, and FIG. 3 is a comparison diagram of the present invention and the conventional method. In the drawing, #0 to #N are l10 (channels), MS is a memory (main memory), C3 is a control memory, and 28 is a CS address saving section.

Claims (1)

[Claims] In a channel control method in which multiple channels are controlled by a common microprocessor, channel processing requests are divided into data transfer processing requests and other processing requests, and processing requests other than data transfer are executed while waiting for completion of memory access. When this occurs, the control memory access address at that time is saved, a data transfer processing request of another channel is adopted instead, and the control memory is accessed using the control memory access address for processing the request. A channel control method characterized in that the data transfer process of the other channel is executed, and after the execution is completed, the process waiting for completion is continued using the save address.