JP2669911B2 - DMA controller and information processing system - Google Patents

Description

TECHNICAL FIELD The present invention relates to a direct memory access controller (hereinafter referred to as a DMA controller) of a microprocessor application device in an information processing system,
In particular, the present invention relates to a DMA controller suitable for executing a high-speed command chain.

[Prior Art] In a microprocessor application device, a DMA controller that directly transfers data between a memory and I / O is controlled by a control command from the microprocessor.

This control command is simply set in the internal register of the DMA controller and as a command descriptor, the microprocessor writes in the common memory of the microprocessor and the DMA controller, the DMA controller reads the command descriptor in the common memory, and the contents There is a method that operates according to.

In the latter descriptor method, if a command sequence is set beforehand in the memory as a descriptor sequence from the microprocessor, the DMA controller will then execute the command descriptor (hereinafter referred to as command).
Are read from the memory, chained and executed sequentially.

For the conventional command chain technology, see Japanese Patent Laid-Open No. 63-
249249.

 Hereinafter, this technique will be described with reference to FIG.

FIG. 6 (a) is a schematic block diagram showing the principle of the prior art.

In the figure, 500 is a post-command generation means, 501 is an identifier addition means,
Reference numeral 510 is an arithmetic processing unit (hereinafter referred to as CPU) for realizing the functions of the command word generating unit 500 and the identifier adding unit 501, 502 is a command, 503 is a main storage unit, 504 is data input / output and
An input / output interface device for performing a DMA process, and a control device 505 for chaining commands to the input / output interface device 504.

FIG. 6 (b) is a diagram showing a command sequence given to the input / output interface device 504 and the control device by the CPU 510 of FIG. 6a.

In FIG. 6A, the CPU 510 has a command word generating means 50.
For the command generated by 0, the identifier adding means 501 adds bit data of "1" or "0" to the most significant bit (MBS) as an identifier. This MBS'1 'indicates the existence of the command itself, and MBS'0' indicates that the next command has not been generated.

Therefore, the control unit 505 reads out the command sequence shown in FIG. 6B stored in the main storage device 503, sequentially processes the commands whose MBS is "1", and the commands whose MSB is "0". When is read, the next command waits.

On the other hand, the CPU 510 generates the next command in parallel with the operation of the input / output interface device 504.

Further, after the command waiting state, the control means 505 does not read the next command from the main storage device 503 but directly fetches and executes the command 502 on the bus.

As described above, according to the conventional technique, by providing the command identifier, the command generation process and the process of command chaining for input / output can proceed simultaneously, so that the processing speed of the entire system is improved.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, although it is possible to achieve the simultaneous progress of the command generation processing of the CPU and the command chain processing for performing the input / output processing, the input / output processing and the command from the main storage device No consideration was given to improving the efficiency of read processing.

In other words, there is a problem that the input / output processing corresponding to one command is terminated and it takes time to access the memory of the main storage device for the next command chain. When the command storage and the command chain occur at the same time, the memory access conflicts, and the command chain processing requires a long time.

A first object of the present invention is to provide a DMA controller capable of speeding up input / output processing by shortening the command chain processing time which is the overhead of input / output processing, and the DMA controller.
An object is to provide an information processing system including a controller.

Further, in the input / output processing, since the input / output data is read or stored in the main storage device, access conflict between the input / output data access of the main storage device and the command access may occur.

A second object of the present invention is to provide a DMA controller capable of accelerating the input / output processing by shortening the memory access contention time between the input / output data and the storage / reading of the command, and an information processing system including the DMA controller. To provide.

Also, in a system in which the command chain control device generates commands in parallel with the process of chaining commands from the CPU, if the command generation process of the CPU is faster than the command chain process, or the memory for setting the commands is limited. Therefore, the waiting time that occurs when the CPU cannot set the command sequence at one time, the CPU can perform other processing, that is, the CPU efficiency should be improved.

A third object of the present invention is to provide a DMA controller capable of speeding up system performance by providing means for easily detecting a chain processing state of a command set by a CPU, and an information processing system including the DMA controller. It is in.

[Means for Solving the Problems] In order to achieve the first object, the present invention provides a command word string temporary storage means for storing one or more command words for instructing DMA transfer executed by a DMA controller, and a command chain. DMA
There is provided a first DMA controller characterized in that, during the transfer processing, it has a means for previously fetching one or more command words for instructing subsequent DMA transfer and storing them in a command word string temporary storage means.

Also provided is a second DMA controller having a function of executing a command chain DMA transfer and having a command port and a DMA transfer target data port that are independent of each other. In addition, in addition, the above-mentioned DMA controller connected to the first bus at the DMA transfer target data port and secondly connected to the command port at the second bus, storage means connected to the first bus, and There is provided a first information processing system characterized by having a CPU (central processing unit) for independently accessing the bus and the second bus.

In order to achieve the first and second objects, the present invention provides a first-in first-out memory that is externally write-accessible and is capable of accumulating one or more command words for instructing DMA transfer to be sequentially read and executed by a DMA controller. And a third DMA controller.

In order to achieve the first, second and third objects, the present invention provides a first-in first-out memory for accumulating one or more command words for instructing DMA transfer to be sequentially read and executed by a DMA controller, and data stored in the first-in first-out memory. A means for counting the number, a storage means capable of setting a predetermined number n (n is an integer less than or equal to the number of data that can be stored in the first-in first-out memory) from the outside, a result of the counting means and a value in the storage means. A fourth DMA controller having means for comparing and means for outputting the result of the comparison to the outside is provided.

In order to achieve the third object, the present invention provides a DMA
It has a storage means for storing a command word for instructing transfer, a CPU (central processing unit) for storing the command word in the means, and a DMA controller for reading the command word stored in the storage means and executing a command chain DMA transfer. In the information processing system, the storage means has an identifier field corresponding to each of the stored command words, and the DMA controller writes the data indicating the identifier field “processed” corresponding to the command word for which the processing is completed. A second information processing system having means is provided.

Further, in order to achieve the third object, a means for executing a command chain DMA transfer according to a command word generated by a CPU (central processing unit) and a number of unexecuted command words among the command words generated by the CPU And a means for generating a command word for instructing the DMA controller to perform a DMA transfer, according to the information related to the number of unexecuted command words output by the DMA controller. A third information processing system is also provided, which includes a CPU for scheduling processing.

The present invention also provides a 1-chip LSI, particularly a 1-chip microcomputer, which is equipped with the DMA controller.

The present invention also provides the DMA controller or the 1
There is provided a fourth information processing system including a chip LSI, particularly a one-chip microcomputer.

[Operation] According to the first DMA controller of the present invention, during command chain DMA transfer processing, one or more command words for instructing subsequent DMA transfer are fetched in advance and stored in the command word temporary storage means. Store. As a result, it is not necessary to read the command word at the time of performing the DMA transfer, the memory access time and the loss time due to the memory bus contention with the CPU and the like can be omitted, and a high-speed command chain can be realized.

Further, according to the second DMA controller of the present invention, the command word is input or input / output from the command port, and the DMA transfer target data is input / output from the DMA transfer target data port.

Further, according to the first information processing system of the present invention, the command word generated by the CPU is fetched into the DMA controller via the second bus, and the DMA transfer target data is fed into the DMA controller via the second bus. Is output. As a result, the access to the input / output data memory and the memory access for storing the new command generated by the CPU do not conflict on the same bus, so that a high-speed command chain can be realized.

Further, according to the third DMA controller of the present invention, one or more command words that instruct the DMA transfer to be sequentially read and executed by the DMA controller are externally transferred to the first-in first-out memory. This eliminates the need to read command words at the time of DMA transfer, saves memory access time and loss time due to memory bus contention with the CPU, etc., and realizes a high-speed command chain because memory access does not conflict. it can.

Further, according to the fourth DMA controller of the present invention, the number of command word data stored in the first-in first-out memory is counted and compared with the predetermined number n set in the storage means. Then, the result of the comparison is output to the outside.

Further, according to the second information processing system of the present invention, the DMA controller writes the data indicating the identifier field “processed” corresponding to the command word for which processing has been completed.

Further, according to the third information processing system of the present invention, the DMA controller executes the command chain DMA transfer according to the command word generated by the CPU, and the unexecuted command among the command words generated by the CPU. Outputs information related to word count. On the other hand, the CPU generates a command word for instructing DMA transfer to the DMA controller, and schedules processing according to the information related to the number of unexecuted command words output from the DMA controller. As a result, the processing efficiency of the CPU is improved and the processing performance of the entire system can be increased.

[Example] Hereinafter, a first example of the present invention will be described.

FIG. 1A shows the configuration of the DMA controller according to this embodiment.

The configuration of the entire system including the CPU and the main storage device of the information processing system according to the present embodiment is the same as the configuration of FIG.

FIG. 1A shows a transmission control LS in which the input / output interface device 504 and the control means 505 shown in FIG. 6 are integrated.
It is shown as a DMA controller such as I.

In FIG. 1 (a), reference numeral 2 denotes an input / output processing unit that performs actual data input / output processing according to one command.

Reference numeral 3 is a command execution control unit that performs command chain processing. Reference numeral 4 denotes a memory interface circuit for reading the command descriptor from the main storage device, which will be referred to as a command read circuit hereinafter. Reference numeral 5 denotes a memory array which is the above-mentioned command sequence temporary storage means, 6 and 7 are control means for the above-mentioned command sequence temporary storage means, 6 is a write pointer for managing the command writing position, and 7 is a command. It is a read pointer that manages the read position.

Next, FIG. 1 (b) shows a flow of command processing according to the present embodiment.

 In FIG. 1 (b), the vertical direction represents the time axis.

In FIG. 1 (b), MM indicates a main memory device, IOC indicates a DMA controller, and IO indicates the input / output processing unit 2 in the DMA controller.

The operation of each component shown in FIG. 1A will be described with reference to FIG.

First, in FIG. 1 (b), the CPU stores the already generated command sequence cmd (1), cmd (2), cmd (3) in the main memory MM. The IOC that is the DMA controller 1 uses the command read circuit 4 to cmd (1) on the main memory MM.
Is read out and set to the position cmdr (1) on the memory array 5 indicated by the write pointer 6. After this, write pointer 6
Updates the contents and points to cmdr (2).

The command execution control unit 3 in the DMA controller 1 uses cmdr (1) indicated by the read pointer 7 as the first command.
Cmd (1), which is the content of, is read out, and command start information cmdS (1) is given to the input / output processing unit 2.

Also, after this, the read pointer 7 updates the contents and cm
Refers to dr (2).

Next, the DMA controller 1 uses the c
Without waiting for the end of the md (1) process, the commands cmd (2) and cmd (3) on the main memory MM are sequentially read out and the memory array 5 is read.
Set to cmdr (2) and cmdr (3) of.

After that, when the input / output processing unit 2 notifies that the processing of cmd (1) has been completed by the command end information cmdE (1), the command execution control unit 3 immediately outputs the information to the main memory without causing it to be saved. Then, the next command cmd (2) can be read from the memory array and the command start information cmds (2) can be given to the input / output processing unit 2.

Therefore, t _w in FIG. 1 (b), which is the time required for the command chain, is shorter than that of the conventional command chain device that reads the command from the main memory each time.

As described above, according to the DMA controller according to the present embodiment, the command chain processing can be speeded up. Therefore, the information processing system including the DMA controller is a CPU.
Can speed up DMA transfer without performing any new processing. Therefore, the processing efficiency of the system can be improved.

 Next, a second embodiment of the present invention will be described.

FIG. 2A shows the configuration of the entire system of the information processing system according to this embodiment.

In the figure, 100 is a command memory as a storage means for storing command descriptors, which is connected to a command memory bus which is a bus different from the main storage device 503.

The other components are the same as those of the same reference numeral in FIG. 6 (a) according to the above-mentioned conventional technique. I / O processor 504a
The actual data input / output processing including the data transfer between the I / O device and the main storage device 503 is performed, and the input / output control device 505a is connected to the command memory bus instead of the main memory bus.

The input / output processing device 504a and the input / output control device 505a are
It is a component of the DMA controller.

FIG. 2B shows the flow of command processing according to this embodiment.

 In the figure, the vertical direction represents the time axis.

In FIG. 2 (b), LM indicates the command memory 100, and IOC
Indicates the input / output control device 505a, and IO indicates the input / output processing device 504a.
MM indicates the main storage device 503.

 The operation of this embodiment will be described with reference to FIG.

First, the CPU 510 uses the command string cmd that has already been generated.
Set (1), cmd (2), cmd (3) to the command memory 100 (L
M). The input / output control device 505a (IOC) reads the command cmd (1) on the command memory 100, and outputs the corresponding command start information cmdS (1) to the input / output processing device.
Give to 504a. The input / output processing device 504a performs data transfer processing between the I / O and the main storage device 503 one or more times, and cmd
Command completion information cmd after completing the process corresponding to (1)
In (1), it responds to the input / output control device 505a.

On the other hand, during this I / O processing, CPU510
Generate cmd (4). This cmd (4) is the main memory 50
Command memory on command bus independent of 3 1
Since it may be stored in 00, it does not conflict with the main memory bus access by the data input / output processing corresponding to the cmd (1).

Therefore, according to this embodiment, it is possible to prevent bus contention at the time of adding a command or the like, so that it is possible to speed up the command chain processing.

Also in this embodiment, the input / output control device 505a reads the command in the command memory 100 prior to the command processing of the input / output processing device 504a, and reads the command start information cm.
It is possible to shorten the command chain time by creating and storing dS in advance. Fig. 2 (b)
The read of cmd (2), cmd (3), and cmd (4) by the IOC of FIG.

In the configuration of this embodiment, a method for realizing this function can be combined with the above-described first embodiment. Since the technique is similar to the method using the FIFO described later, further description will be omitted.

 Next, a third embodiment of the present invention will be described.

FIG. 3 shows the configuration of the DMA controller according to this embodiment.

In the figure, components having the same reference numerals as those in FIG. 1 (a) showing the configuration of the DMA controller according to the first embodiment described above are the same as the modulus encoder of the DMA controller according to the first embodiment, and therefore the description will be omitted. Omit it.

In the figure, 200 is a FIFO and 201 is a register array, which is a command temporary storage means similar to the memory array 5 of the first embodiment.

Reference numeral 202 denotes a comparator as a circuit for generating a FIFO status signal indicating the match between the write pointer and the read pointer, that is, FIFO full. FIFO full means that the FIFO is full.

Now, the difference between this embodiment and the first embodiment is that the first
In the embodiment, the DMA controller 1a reads the command in advance from the main storage device, whereas in the present embodiment, the command storage from the CPU is the register array 201 of the FIFO 200 in the DMA controller, so the DMA controller 1a Does not involve a command read operation to the outside.

Therefore, in this embodiment, the CPU is the DMA controller 1a.
By monitoring that the FIFO 200 does not become full with the FIFO status signal that is the output of the comparator 202 and continuously storing the commands in the FIFO 200, the same function as the command read-ahead of the DMA controller 1a can be realized. .

Therefore, the same effect as that of the first embodiment can be realized.

Furthermore, by providing a bus connecting the FIFO and the CPU and a bus relating to data input / output of the input / output processing unit 2 separately, the same effect as in the second embodiment can be realized.

 Next, a fourth embodiment according to the present invention will be described.

The present embodiment has a configuration in which the FIFO 200 of the third embodiment is replaced with the FIFO according to the present embodiment.

 FIG. 4 shows the configuration of the FIFO according to this embodiment.

In the figure, 300 is a preset register that stores the number of commands, 301 is a computing unit that calculates the number of commands, and 302 is a comparator that detects the number of commands.

The arithmetic unit 301 calculates the number m of unprocessed commands in the register array 201 from the contents of the write pointer 6 and the read pointer 7. On the other hand, an appropriate value n (n is an integer equal to or less than the number of FIFO stages) is preset in the preset register 300 from an external CPU. The comparator 302 compares the value n in the preset register 300 with the unprocessed command number m calculated by the arithmetic unit 301, and determines whether they are coincident or large or small as the FIFO status.
Output to outside of 0a.

Therefore, the CPU continuously stores q (q> p) commands in the FIFO 200 in advance, on the condition that when the number of unprocessed commands in the FIFO 200a becomes p, a new command is generated and stored in the FIFO 200a. , Preset register
If n = p is set to 300, the DMA controller will
-While p command processing is being performed, processing other than command generation is possible.

In particular, if the information processing system is configured by using the FIFO status signal as an interrupt to the CPU, the efficiency of CPU scheduling can be further improved.

As described above, according to the present embodiment, the CPU can easily detect the number of unprocessed commands in the FIFO used for the DMA controller, and by improving the CPU usage efficiency, it is possible to speed up the processing performance of the entire system of the information processing system. realizable.

 Next, a fifth embodiment of the present invention will be described.

FIG. 5 (a) shows the structure of the command sequence used in this embodiment.

This figure particularly shows a direct state in which three commands are stored from the CPU in the command descriptor storage area on the main storage device. It should be noted that, for the sake of simplification of explanation, in the present embodiment, the DMA controller does not perform the above-mentioned command preceding read processing.

Immediately after storage, the conventional identifier described in the above-mentioned conventional technique (see FIG. 6) is set in the REQ field for the commands 1, 2, and 3. Also, the used identifier of the ACK field provided in this embodiment is set to "0" indicating the "necessary state".

FIG. 5B shows commands 1 and 2 of the command sequence on the main memory set in FIG. 5A in a state where the DMA controller has finished processing.

At this time, the ACK field of the commands 1 and 2 is "1" as the "used state", and the ACK field of the command 3 is "0" indicating the "necessary state".

By monitoring the command ACK field, the CPU
The command processing status of the DMA controller can be detected. Therefore, the CPU can schedule processing other than command generation processing to be executed when there are many commands in the "necessary state", and therefore the processing performance of the entire information processing system can be increased.

A specific method for setting the ACK field is, for example, a method in which the command reading means of the DMA controller is a circuit capable of read / modify / write, and the description thereof is omitted here.

Further, when the DMA controller is a device capable of pre-reading as shown in the first embodiment, the timing of setting the ACK field may be the time when the corresponding command is read from the main memory device into the DMA controller. .

As described above, according to the present embodiment, by reading the command descriptor string prior to the actual command processing, there is an effect of speeding up the command chain that the overhead time at the time of command chain can be shortened.

Also, by arranging the storage device of the command descriptor string on a bus that is separate from the data transfer by command execution, there is no bus contention between the command addition process from the CPU and the data transfer process during command execution, so high-speed data Transfer processing becomes possible.

Furthermore, the command chain processing state can be easily detected by the CPU, so that processing other than command generation can be scheduled in the CPU, which has the effect of improving CPU usage efficiency and speeding up system performance.

[Effects of the Invention] As described above, according to the present invention, a DMA controller capable of accelerating the input / output processing by shortening the command chain processing time, which is the overhead of the input / output processing, and the information provided with the DMA controller A system can be provided.

Further, it is possible to provide a DMA controller capable of speeding up input / output processing by shortening a memory access conflict time between input / output data and storing / reading of the command, and an information system including the DMA controller.

Further, it is possible to provide a DMA controller capable of speeding up system performance by providing a means for easily detecting a chain processing state of a command set by the CPU, and an information processing system including the DMA controller.

It is desirable that each DMA controller according to the present embodiment is integrated into one chip LSI alone or together with the CPU. Further, it may be integrated into one chip LSI together with other components.

[Brief description of the drawings]

FIG. 1 (a) is a block diagram showing the configuration of a DMA controller according to the first embodiment of the present invention, and FIG. 1 (b) is an explanatory diagram showing the flow of command processing according to the first embodiment, and FIG. (A) is a block diagram showing a configuration of an information processing system according to a second embodiment of the present invention, FIG. 2 (b) is an explanatory diagram showing a flow of command processing according to the second embodiment, and FIG. 3 is a book. FIG. 5 is a block diagram showing a configuration of a DMA controller according to a third embodiment of the invention, FIG. 4 is a block diagram showing a configuration of a FIFO of a DMA controller according to the fourth embodiment of the present invention, FIGS. FIG. 6B is an explanatory diagram showing the processing of a stored command sequence according to the fifth embodiment of the present invention, and FIG. 6A is a block diagram showing the principle of command chain control according to the prior art.
FIG. 1B is an explanatory diagram showing a storage command sequence according to the related art. 1 ... DMA controller, 2 ... I / O processing unit, 3 ...
Command execution control unit, 4 ... Command reading circuit, 5
...... Memory array, 100 ...... Command memory, 200 ...... FIF
O, 201 ... Register array, 300 ... Preset register, 301 ... Calculator, 302 ... Comparator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-134366 (JP, A)

Claims (5)

(57) [Claims] 1. A D that a DMA controller sequentially reads and executes.
A first-in first-out memory that stores one or more command words for instructing MA transfer, a means for counting the number of stored data in the first-in first-out memory, and a predetermined number n (n is an integer less than or equal to the number of data that can be stored in the first-in first-out memory) from the outside A DMA controller comprising: a settable storage means, a means for comparing the result of the counting means with a value in the storage means, and a means for outputting the result of the comparison to the outside. 2. A storage means for storing a command word for instructing a DMA transfer, a CPU (central processing unit) for storing the command word in the storage means, and a command word stored in the storage means for command chain DMA transfer. An information processing system having a DMA controller for executing, wherein the storage means has an identifier field corresponding to each of the stored command words, and the DMA controller has the identifier field "processed" corresponding to the command word for which processing has ended. An information processing system having means for writing data indicating ". 3. A means for executing command chain DMA transfer according to a command word generated by a CPU (central processing unit), and a means for outputting information related to the number of command words that have not been executed among the command words generated by the CPU. A DMA controller provided with, and means for generating a command word for instructing DMA transfer to the DMA controller, and a CPU for scheduling processing according to information related to the number of unexecuted command words output by the DMA controller, An information system comprising: 4. A one-chip microcomputer provided with the DMA controller according to claim 1. 5. An information processing system comprising the DMA controller according to claim 1.