JPS6121559A - System for transferring data directly between memories - Google Patents

Abstract

PURPOSE:To attain efficient sub CPU and high speed DMA transfer by providing a DMA controller to a sub-processing system and transferring a DMA data between a data register and a sub-memory independently of the sub CPU. CONSTITUTION:The sub CPU5 decodes a command from a main CPU1 and sets respectively a head address and byte number of the sub memory 6 to which a transfer data is stored. A sub supervisory section 21 detects a set signal, transmits a stop request to a CPU5 and sets a data to a sub data register 12. A supervisory section 21 detects the signal to start a main DMA (data direct transfer) controller 22. The controller 22 requests stop to the CPU1 to transfer the data to the main memory 3. A main address generating counter 26 is incremented by ''1'', a main byte counter 28 is decremented by ''1'', and when the value of the counter 28 is not ''0'', the transfer request from the sub-processing system is awaited. The sub DMA controller 23 increments the sub-address counter 27, decrements the sub type counter 29 by ''1'' when they are not ''0'', the transfer request of the main processing system is awaited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inter-memory data direct transfer method (hereinafter referred to as an inter-memory DMA method) for transferring data between memories via registers.

'In recent years, with the development of LSI, microcomputers and their peripheral circuits have been integrated into LSI, and DMA can now be easily realized even in small-scale electronic devices.

DMA transfers data stored in the local memory of the main processing system to the I10 device, and sends data output from the I10 device to the local memory of the main processing system.

The data is transferred without going through the main CPU, and the purpose is to improve the processing efficiency of the main CPU and speed up data transfer. Therefore, it is mainly used for data transfer between sub-processing systems such as disk devices, transmission processing devices, and data collection devices that handle large amounts of data.

When a sub-processing system functions as one Ilo and performs DMA, a method using a buffer register is common. ), the sub CPU transfers data to the main processing system's local memory (
(hereinafter referred to as main memory), and according to the address, the DMA timing signal generating section temporarily stops the main CPU and transfers data between the main memory and the above-mentioned register. On the other hand, data transfer between the registers and the memory of the sub-processing system (hereinafter referred to as sub-memory) is performed by the sub-CPU.

The operation of the sub-processing system requires processing time because the sub-CPU performs read/write operations for each transfer data unit according to the program, and there is a demand for faster data transfer in the sub-processing system. - [Prior Art] An example of a conventional DMA system is shown in FIG.

Figure 2 (al is a block diagram of the DMA transfer part, Figure 2 (
bl is a DMA data transfer operation from the main memory to the sub memory (hereinafter referred to as DMA-READ from the perspective of the sub processing system)
Flow chart of FIG. 2 (cl is DMA data transfer operation from secondary memory to main memory (hereinafter DMA-WRI)
FIG.

In Figure 2+al, 1 is the main CPU consisting of a micro combination, 2 is the DMA timing signal generator, 3 is the main memory which is the local memory of the main processing system, and 5 and above are the parts of the main processing system. constitute the department.

4 is a sub-processing system such as a transmission device, a data collection device, etc.
5 is a sub-CPU 96 consisting of a microcomputer, etc.
7 is a submemory; 7 is a address decoder that specifies a register and generates a read/write control signal when the sub CPU 5 performs successive read/write operations for each register, which will be described later;
8 is the main CP [Jl is the secondary CP] when performing DMA data transfer.
A command register that notifies U5 of the address in main memory 3, number of bytes to be transferred, etc.; 9 is a command register that reports the status of the sub-processing system to the main CP.
11 is a status register that notifies the UI; 10 is a main data register that sets transfer data in the main memory 3;
12 is a sub data register for setting the transfer data in the sub memory 6, and an address register 12 is used to specify an address in the main memory 3 to be transferred or stored, to which the sub CPU 5 writes. Note that 101 and 103 are address lines, 1
02°104 is a data line.

This is a DMA data transfer device having the above configuration.

The data transfer operation will be explained below.

The operation of DMA-REA'D will be explained with reference to FIG. 2 (bl).

(A) When a data transfer request occurs, the main CPU
First, the data to be transferred is stored in the main memory 3, and then the address of the data in the main memory 3 and the number of words to be transferred are set in the command register 8.

(B) The main CPU 1 turns on the start/focus of the command register 8 and starts the sub CPU 5. Deputy CP
U5 decodes the command and writes the status of the subprocessing system to status register 9.

The number of words to be transferred is set in an address in the main memory 3 instructed by the main CPUI and in a byte counter (not shown) in the sub memory 6, respectively.

(C) The DMA timing signal generation section 2
A write signal to the register 12 is detected and a stop request is sent to the main CPUI. When there is a response from the main CPU 1 to stop the CPU, the DMA timing signal generator 2 generates a timing signal, opens the gate of the address register 12, and transfers the data in the main memory 3 specified by the register 12 to the main data register 10. Store in.

(D) The sub CPU 5 detects a transfer request by a write signal to the main data register 10, reads the data, and stores it at a predetermined address in the sub memory 6.

(E) The sub CPU 5 sets the value of the byte counter to -1,
If the value is 0, the transfer is terminated.

(F) If the value of the byte counter is 0, the address
Set the value of register 12 to +1.

(G) The DMA timing signal generator 2 again performs the DMA data transfer operation as described in (C), and repeats this until the byte counter reaches 0.

Next, the DMA WRITE operation will be described below according to FIG. 2(C).

(a) The main CPU secures a storage location for the data transferred from the sub-processing system, and writes its start address, number of transferred hides, etc. to the command register 8.

(b) The sub CPU 5 sets the number of transfer bytes and the transfer data in each register, and then sets the start address of the storage destination main memory 3 in the address register 12.

(C) When an address write signal to the DMA timing signal signal generation section 2 address register 12 is detected, the main CPU
1, and after waiting for the response, the address register 12 is opened and the data is stored in the main memory 3.

(d) The sub CPU 5 detects the above transfer and sets the byte counter to -1. If the result is 0, the transfer is terminated; if not, it adds 1 to the address register 12 after the data is sent.

(6) Repeat the above operation until the byte counter reaches 0.

[Problem to be solved by the invention 1 In the DMA system explained above, the secondary CPU is
After receiving a transfer command from the UI, the operation of the address register 12 and the hide counter and the data transfer operation between the data registers 11 and 12 and the sub memory are repeated for each word transfer, so the sub CPU There was a problem in that it was not possible to improve the efficiency of DMA transfer and increase the speed of DMA transfer.

[Means for solving problems]

The above conventional problem is that each independent processing system has a means for specifying the data transfer start address in the local memory and a means for specifying the number of transfer words, and the processing system uses the information specified by the two specifying means. Each processing system is provided with a transfer means for transferring data between the hasher register and the local memory.

A monitoring means is provided that detects the completion of data transfer by the transfer means of one processing system and requests data transfer to the transfer means of the other processing system, and after setting the above address and the number of words to be transferred, the number of words to be transferred becomes 0. This problem can be solved by the data direct transfer method according to the present invention, in which data is transferred between the local memories of each processing system using the transfer means of each processing system.

[Effect]

According to the present invention, by providing a DMA controller in the sub-processing system, it is possible to perform DMA data transfer between the data register and the sub-memory without going through the sub-CPU.
It is possible to improve the efficiency of the secondary CPU and speed up DMA transfer.

〔Example〕 Embodiments of the present invention will be described with reference to the drawings.

Figure 1 ial is a block diagram of the embodiment, Figure 1 (bl is D
A flow chart showing the operation of MA READ.

FIG. 1(C) is a flow chart showing the operation of DMA WRITE.

The functions of each part will be explained with reference to FIG. 1+al. Note that the same symbols represent the same objects throughout the figures.

22 is a main DMA controller that controls DMA of the main processing system, and 23 is a sub DMA controller that controls DMA of the sub processing system.

DMA controllers 22 and 23 perform DMA operations in their respective processing systems in place of the CPU, and timing signal generators 24 and 25 . Address generation counters 26 and 27 . It consists of byte counters 28 and 29. The functions of DMA controllers 22 and 23 will be explained below.

(a) They mutually accept transfer requests from the main processing system or sub-processing system, issue a stop request to their own CPU, and request the right to use the bus. After the CPU is stopped, it generates control signals and performs memory access operations in place of the CPU.

(b) Address generation counters 26 and 27 are each set with a leading address by its own CPU, and are incremented by 1 every time one word is transferred after the DMA operation is started.

(c) Byte counters 28 and 29 each have their own C
The number of transferred words is set by PtJ, and is decremented by 1 every time one word is transferred, and when it becomes 0, the transfer ends.

(d) The timing signal generators 24 and 25 control the counter, data register, read/write signal generation for the registers 11 and 12, memory access signal generation, and own CP.
Generates a stop request signal to U.

Transfer path - DMA by generating timing signals such as completion signal generation
perform an action.

A main monitoring section 20 monitors the DMA operation of the main processing system, detects that transfer data is set in the main data register 11, and activates the sub DMA controller 23.

A sub-monitoring section 21 monitors the DMA operation of the sub-processing system, detects that transfer data is set in the sub-data register 12, and activates the main DMA controller 22.

In a DMA configuration having the above-mentioned functions.

The DMA operation will be explained with reference to the flow chart of FIG. 1(b) and FIG. 1(C1).

DMA READ operation (1) The main CPUI stores the transfer data in the main memory 3,
After setting command data such as the number of bytes to be transferred in the command register 8, and setting the start address of the transfer data and the number of bytes to be transferred in the main address generation counter 26 and the main byte counter 28, respectively, the command register 8
The start/focus is turned on, the sub-CPU 5 is activated, and the sub-processing system waits for DMA operation preparation.

(2) The sub CPU 5 decodes the above command and sets the address and number of bytes of the sub memory 6 to be stored in the sub address generation counter 27 and sub byte counter 29, respectively.

(3) The sub-monitoring section 21 monitors the set signal and outputs the main DMA.
A transfer request is sent to the controller 22.

(4) In the main DMA controller 22, the main timing signal generator 24 issues a stop signal to the main CPUI.

Upon receiving the response signal, the gate of the main address generation counter 26 is opened, and the main memory 3. The data of H is sent to the main data register 11.

(5) The main monitoring unit 20 detects the set signal and sends the sub DMA
The controller 23 is activated. The sub-timing signal generating section 25 issues a stop request to the sub-CPU 5, waits for the response, and then sends control signals to each section to store the data in the main data register 11 in the sub-memory 6.

(6) The main timing signal generator 24 increments the king address generation counter 26 by 1 and increments the main byte counter 28 by -1.
1 and if the value of the main byte counter 28 is 0, the transfer is terminated; otherwise, a transfer request from the sub-processing system is awaited.

(7) In the secondary DMA controller 23, the secondary address generation counter 27 is increased by 1, the secondary byte counter 29 is decremented by 1, and if the secondary byte counter 2'9 is 0, the process ends; otherwise, a transfer request is issued to the main processing system. .

(8) The above operation is performed until byte counters 28 and 29 are 0.
Continue until .

1) MA WRITE operation (i>The main CPU secures a storage location in the main memory 3 for the data transferred from the sub memory 6, and sets the start address and hide number in the main byte counter 28.

Next, the data is sent to command register 8 and sub-c
Start PU5.

(11) The sub CPU 5 decodes the command and sets the start address and number of bytes of the sub memory 6 where the transfer data is stored.

(iii) The sub-monitoring unit 21 detects the J-recorded Sesotho signal.

A stop request is issued to the sub CPU 5, and the sub data register 12 is
cents the data.

(1v) The sub-monitoring section 21 detects the signal and starts the main DMA controller 22. Main DMA controller 22
Then, the main CPU is requested to stop and the data is transferred to the main memory 3.

(v) The main address generation counter 26 is incremented by 1, the main byte counter 28 is -1, and unless the value of the byte counter 28 is O, a transfer request from the sub-processing system is waited for.

(vi) In the secondary DMA controller 23, the secondary address generation counter 27 is increased by 1, the secondary hide counter 29 is decreased by 1, and if it is not 0, it waits for a transfer request from the main processing system.

For the above DMA read/write operations, both the main processing system and the sub-processing system have address counters for the data to be stored and transferred, and there is also a monitoring section that monitors the DMA operations of each processing system, and writes data to the data register. In order to detect the end of DMA operation in each processing unit and send a transfer request,
Main CPU, secondary CPU until the hide counter reaches O.
DMA transfer can be achieved automatically without going through 5.

Furthermore, high-speed transfer can be achieved because there is no program-based successive read/write operation like DMA transfer by the sub CPU 5.

〔Effect of the invention〕

As a result of realizing internal DMA transfer, the number of secondary CPUs is reduced by 90%, D
The MA transfer speed can be increased, and the effect is great.

[Brief explanation of the drawing]

FIG. 1+8) is a block diagram representing an embodiment of the present invention. Figure 1(b) shows the flow chart representing the DMA READ operation.
chart. FIG. 1 tC) is a flow chart representing a DMA WRITE operation. FIG. 2(a) is a block diagram of a conventional DMA device. 2nd TI! J(b) C Conventional (7) Flow chart of DMA READ operation Figure 2 (C1 is a flow chart representing the conventional DMA WRITE operation. In the figure, 1 is the main CPU, 3 is the raw memory. 5 is the secondary CPU, 6 is the secondary memory. 8 is the command register. 9 is the status register. 11 is the main data register. 12 is the secondary data register. -20 is the main monitoring unit, 21 is the secondary monitoring unit. 22 is the main DMA controller. 23 is the sub-DMA controller. 24 is the main timing signal generator. 25 is the sub-timing signal generator. 26 is the main address generation counter. 27 is the sub-address generation counter. 28 is the main byte counter. 29 is the main byte counter. The secondary byte counter is ′. Tea 1 Concave tea 2 Min (a) * 2 Figure (b,) Kaya 2 Figure

Claims (1)

[Claims] A direct memory-to-memory data transfer method in which data is directly transferred between local memories of independent processing systems via buffer registers, and the method includes a means for specifying a data transfer start address in the local memory and a means for specifying the number of transfer words. Each processing system is provided with a transfer means that transfers data between the buffer register and the local memory based on the information specified by both specifying means, and the data transfer means of one of the processing systems is A monitoring means is provided that detects the end of data transfer and requests data transfer to the transfer means of the other processing system, and after setting the above address and number of transfer words, the transfer means of each processing system waits until the number of transfer words becomes 0. A direct inter-memory data transfer method characterized by transferring data between local memories of each processing system.