JPH01228054A - Adapter and its control method for multiple cpu system - Google Patents

Abstract

PURPOSE:To delete a processing program for interrupting the asynchronization of a CPU by providing a register to set a command to an adapter and executing the interruption to the CPU only when the adapter detects a bus error or an adapter error. CONSTITUTION:Plural CPU 12a, 12b and 12c are coupled with a system bus 11, and share a main memory 13. For an adapter 14, registers 21a, 21b and 21c for setting a command corresponding to respective CPUs are provided. For example, when a CPU 12a is communicated with a disk, the CPU 12a issues the request to communicate with an I/O connected to the adapter 14 for the adapter. The adapter 14 executes this, sets the error command respectively to a register 21a when an abnormality is completed and thereafter, applies the interruption to the CPU 12a. The interruption is applied to the CPU 12a only, it is not applied to other CPUs, and therefore, a processing program is made unnecessary and an execution efficiency is raised.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a multi-CPU system adapter and its control method, and aims to reduce the burden on the CPU and improve the processing speed of the CPU. In a multi-CPU system consisting of a memory in which commands from the CPU are set, an adapter that establishes communication between the CPU and external terminal equipment, and a bus that connects these operating parts, the adapter
A register corresponding to U is provided, and a command indicating the end of processing execution of the adapter and an error command are stored in the register, and the configuration is such that the corresponding CPU is interrupted.

(Industrial Application Field) The present invention relates to an adapter, and particularly to an improved adapter that is used in a multi-CPU system to reduce the overhead of the CPU.

(Prior Art) Multi-CPU systems, in which multiple CPUs are connected to a common bus and the processing results (i.e., data) obtained by each CPU are transferred to, for example, a disk, have been widely used in recent years. A general example of such a multi-CPU system is shown in FIG. Multi-C shown in this figure
The PU system consists of multiple CPUs connected to system bus 1.
An adapter that connects the PU2a, 2b, 2c, the main memory 3 in which processing programs and processing data of each CPU2a, 2b, 2c are stored, and a terminal device such as a disk device that exchanges data with each CPU2a, 2b, 2c. 4
It is composed of. Adapter 4 is system bus 1
each CPU 2a, 2b, 2c to accept data from
Input boats 5a, 5b, 5c provided corresponding to the
A bus 6 provided in the adapter 4, a local memory 7 connected to this bus, output ports 8 and 9 connected to the bus for sending data to a disk device, etc., and a microprocessor that controls the operation of each of these parts. 10. In such a multi-CPU system,
If any of the CPUs 2a, 2b, or 2c (in this case - CPU 2a as an example) issues a command to the input report 5a corresponding to the CPU 2a, and a system bus error or adapter error occurs during the execution of this command, the adapter 4 The input port 5a of the access source CPU 2
At the same time, an interrupt is raised to the other CPUs 2b and 2c asynchronously. Based on this, multi-CP
All CPUs 2a, 2b, and 2c constituting the U system perform data processing in response to asynchronous interrupts from the adapter 4 side.

(Problem to be Solved by the Invention) However, in such a conventional adapter 4, if a bus error or adapter error occurs during command execution from one CPU 2a, the access CPU 2
Since interrupts were issued not only to a, but also to other CPUs 2b and 2c, the other CPUs 2b and 2c, which are not issuing commands to adapter 4, must perform enormous and complex software processing in order to respond to asynchronous interrupts. There was a problem in that it imposed a heavy burden on the CPU. Furthermore, in a multi-CPU system, the CPU
CPU that does not issue commands such as U2b and 2c
Generally, each CPU performs its own processing, but if the original processing of such a CPU is interrupted by an interrupt from the adapter 4 and it has to perform interrupt processing, it will cause problems from the perspective of the entire system. There was a problem that the processing speed decreased.

The present invention was made in view of such conventional problems, and its purpose is to reduce the burden on the CPU, and also to reduce the burden on the CPU.
An object of the present invention is to provide an adapter that improves the processing speed of U.

(Means for solving problems) FIG. 1 is a diagram showing the basic configuration of the present invention.

In this figure, reference numeral 11 indicates a system bus, 12a, 1
2b and 12c are multiple CPUs connected to the system bus
, 13 is a main memory in which various data necessary for the operation of this multi-CPU system is stored, and 14 is a main memory for storing this multi-CPU system.
This is an adapter built into the PU system. adapter 1
4 is provided with registers 21a, 21b, 21c corresponding to each CPU 12a, 12b, 12c, and these registers 21a, 21b, 21c are provided with an adapter 14
A termination command indicating the end of operation and an error command indicating a bus error etc. are temporarily stored, and the corresponding CP
It is now transmitted to the U.

[Effect]

As an example of the operation of a multi-CPU system, CPU12a
, 12b, 12c and the disk. For example, looking at the operation of CPU-012a, this CPU-012a has main memory 1
A predetermined processing program is read from 3 and executed. Then, a usage request is issued to the adapter 14 to communicate with Ilo connected to the adapter 14. The adapter 14 analyzes and executes the request from the CPU-012a. When this execution operation is normally completed, the adapter 14 sets a termination command in the register 021a, raises an interrupt to the CPU-012a, and enters a command activation waiting state. On the other hand, while the adapter 14 is running,
If a disconnection error or adapter error occurs, adapter 1
4 sets an error command in the built-in register 021a and raises an interrupt to the CPU-012a. After raising this interrupt, the adapter 14 connects the other CPU-112b
, the CPU-n12c enters a command activation waiting state. In this case, since the other CPU-112b and CPU-n12c have not received the error command, each can execute its own program, improving the operating efficiency of the multi-CPU system as a whole.

(Embodiment) FIG. 2 is a diagram showing an embodiment of the adapter 14 incorporated in the multi-CPU system shown in FIG. 1, and FIGS. 3 and 4 are flowcharts showing the operation of this embodiment. be.

In this embodiment, adapter 14 connects system bus 1
1 and each CPU 12a, 12b.

15a provided corresponding to 12c.

15b, a data transfer bus 16 provided within the adapter 14, and a local memory 17 connected to the bus 16.
, an output port 18, 19 that is connected to a bus and sends data to Ilo such as a disk device, and a microprocessor 20 that controls the operation of each of these operating sections. The input ports 15a and 15b are provided with registers 21a and 21b for storing commands, respectively.
The commands stored in the registers 21a and 21b are
It is possible to send an interrupt to the PUs 12a and 12b.

The adapter 14 and CPU-012a having such a configuration,
The control operation between the CPU-112b is shown in FIGS. 3 and 4.
This will be explained based on the diagram. Here, the flow of CPU1 in FIG. 3 assumes that CPU0 accesses the adapter after a bus error or adapter error occurs during adapter access. Or, when CPUO accesses the adapter, the buffer is empty.

A multi-CPU (here CPU-
012a and CPU-112b), when the CPU-012a issues a request to use the adapter 14 in processing step (indicated by ST in the figure) l, the program of this CPU-0 is stored in the main memory 13 in step 2. The command is written, and further, in step 3, it is checked whether the adapter 14 is ready.

If the adapter 14 is not ready in this processing step, the check operation is repeated until it becomes ready, and when the adapter 14 becomes ready, the adapter 14 is activated. However, the programs of each CPU in this embodiment are designed so as not to cause the adapter Not Ready state.

On the other hand, in the adapter 14, the C
It is checked whether or not the command activation flag has been set from the CPU-012a, and if the command activation flag is set from the CPU-012a, the process moves to step 5. In step 5, the main memory 1 is set by the firmware.
3 to the internal adapter buffer 22. Then, in step 6, the read command is analyzed and executed. As a result, for example, as described above, the CPU-01
Processing such as data transfer from 2a to the disk device is performed. When the adapter 14 executes the command in step 6, the process moves to step 7, and checks whether an error has occurred in the adapter 14 or the bus 11.

If no error has occurred in this check operation, the process moves to step 8, sets an end command to the register 012a provided at the input port 015a, and then sends the CPU-012
Raise the interrupt to a. Adapter 14 then steps 9
If the command activation flag is reset and the buffer is not full, it enters a ready state and waits for the command activation flag to be set.

On the other hand, if it is determined in step 7 that an error has occurred in the adapter 14 or the bus 11, the adapter 1
4, in step 10, an error command is set in the register 021a provided at the input port 015a, and the C
Raise an interrupt to PU-012a. This allows the CPU
-012a recognizes that an error has occurred in the adapter 14 or the bus 11 and executes an error handling routine using an interrupt. At this stage, error command interrupts are sent to the CPU.
-012a because it can only be raised for CPU-112
The other CPUs below b perform their own processing. After raising the interrupt of the error command, the adapter 14 resets the command activation flag in step 11, and if the buffer is not full, it becomes ready and other CPUs
Wait for startup from.

Under such conditions, the CPU-112b performs step 1.
When a request to use the adapter 14 is issued in step 2, this CP
The U-112b program writes a command to the main memory 13 in step 13, and further checks whether the adapter 14 is ready in step 14. If the adapter 14 is determined to be ready in this processing step, the adapter 14 is activated.

In the adapter 14, the CPU-
It is checked whether the command activation flag from the CPU-112b has been set, and if the command activation flag from the CPU-112b is activated, the process moves to step 16. In this step 16, the same error command as before is set in the register 121b provided in the input port 115b, and the
Raise an interrupt to PU-112b. and each step 5
When the processing steps of TII, 5T15, and 5716 are expressed as STX, this processing step is expressed as shown in FIG. 4, and is repeated until all CPUs are activated.

That is, as shown in FIG. 4, for startup from CPU-n, after raising the error command interrupt to CPU-n-1, the 5T11a scent command startup flag is reset, and the command startup is performed in step 15. Check if the flag is set. When a command is activated from CPU-n, the same error command that has caused the interrupt so far is set in step 16a, and the CPU
- Raise interrupt to n, and to 5711b.

and reset the command activation flag. While this series of processing loops continues, the adapter 14 waits for adapter reset at step 17 in FIG. 3.

(Effects of the Invention) As explained above, according to the present invention, an adapter is provided with a register for command setting, and when the adapter detects a bus error or an adapter error, the error command is allocated only to the accessing CPU. Since the processing program for asynchronous interrupts of the CPU can be deleted, the software can be simplified.

Further, since the CPU is not prevented from executing its own program by the asynchronous interrupt, various effects such as increased processing speed and improved work efficiency can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the adapter used in the present invention, FIG. 3 is a flowchart showing an example of the operation of the CPU and adapter of the present invention, and FIG. 5 is a flowchart showing an error interrupt operation in the operation of the CPU and adapter, FIG. 5 is a block diagram showing a conventional multi-CPU system, and FIG. 6 is a block diagram showing an example of the configuration of a conventional adapter. 11...Bus 12a, 12b, 12c...CPU 13...Main memory 14...Adapter 21a, 21b, 21c...Register or 1 slot, buried II 1 View

Claims (2)

[Claims] (1) Multiple CPUs (12
In a multi-CPU system in which a), (12b), and (12c) are connected to a main memory (13) in which commands are stored and an adapter (14) that establishes communication between the CPU and an external terminal device, When the adapter detects at least one of a bus error and an adapter error, it issues an error interrupt to the accessing CPU, and then interrupts the other CPU.
A method for controlling an adapter in a multi-CPU system, characterized in that the system is controlled by waiting for a command activation from a U. (2) Multiple CPUs (12a), (12b), (12c)
), a memory (13) in which commands from the CPU are set, an adapter (14) that establishes communication between the CPU and an external terminal device, and a bus (11) that connects the CPU, memory, and adapter.
In the multi-CPU system, the adapter is provided with a register corresponding to each CPU, and this register temporarily stores an end command indicating the end of processing execution of the adapter and an error command when an error occurs, A multi-CPU system adapter characterized by being able to interrupt a corresponding CPU.